CN102469658A

CN102469658A - Load drive device and load drive method

Info

Publication number: CN102469658A
Application number: CN201010549986XA
Authority: CN
Inventors: 陈许民
Original assignee: LIANYANG SEMICONDUCTOR CO Ltd
Current assignee: LIANYANG SEMICONDUCTOR CO Ltd; ITE Tech Inc
Priority date: 2010-11-15
Filing date: 2010-11-15
Publication date: 2012-05-23
Anticipated expiration: 2030-11-15
Also published as: CN102469658B

Abstract

The invention provides a load drive device and a load drive method. The load drive device comprises a drive signal generator and a controller. The drive signal generator is used for providing a drive signal to a load. The controller is used for generating and providing a control signal to the drive signal generator. In the load drive device, the drive signal generator generates N integer signals and M fraction signals in a drive cycle according to the control signal so as to form the drive signal, wherein N and M are positive integers, and the amplitudes of the integer signals are greater than that of the fraction signals.

Description

Load drive device and method thereof

Technical field

The present invention relates to a kind of load drive device and method thereof, relate in particular to a kind of reduction electromagnetic interference (Electromagnetic Interference, load drive device EMI) and method thereof.

Background technology

It please is the sketch map of the drive unit of existing light-emitting diode with reference to Figure 1A.Light-emitting diode LD1 wherein is serially connected between current source I1 and supply voltage VDD, and current source I1 receives control signal CTRL and determine whether the luminosity of output current with control light-emitting diode LD1 according to control signal CTRL.

Simultaneously please with reference to Figure 1A and Figure 1B, Figure 1B is the oscillogram of drive unit of the light-emitting diode of Figure 1A.Wherein, when drive unit when carrying out dimming period DIT, can be according to the waveform of PWM signal PWM time as control signal CTRL firing current source I1, make electric current I through light-emitting diode LD1 and make light-emitting diode LD1 luminous.And, when closing dimming period NDIT, then can make light-emitting diode LD1 not luminous with turn off current source I1 through control signal CTRL.Wherein the unit interval unit of being denoted as of control signal CTRL lights time UT, i.e. the inverse of the frequency of light modulation clock signal CK.Thus, only need the time length ratio of carrying out dimming period DIT and closing dimming period NDIT among the control light modulation period L T, just can control the mean flow rate of light-emitting diode LD1.

Be not difficult to learn by above-mentioned explanation,, can improve the frequency of light modulation clock signal CK, perhaps increase the time of light modulation period L T if desire increases the light modulation exponent number of light-emitting diode LD1.Yet more the PWM signal PWM of high frequency also can produce the more serious electromagnetic interference phenomenon of degree except meeting increases the consumption of electric current; And the time of increase light modulation period L T then can be reduced light modulating frequency, because light modulating frequency is the inverse in light modulation cycle; If light modulating frequency is lower than below the 20kHz; To produce the sensitive sound of people's ear, therefore, the general performance of system under above-mentioned dual mode all can influence.

Summary of the invention

The present invention provides a kind of load drive device, comprises driving signal generator and controller.Driving signal generator couples load, in order to provide drive signal to load.Controller couples driving signal generator, controls signal to driving signal generator in order to produce and to provide.Wherein, N integer signal of generation and M fractional signal are to form drive signal in drive cycle according to control signal for driving signal generator, and N and M are positive integer, and the amplitude of integer signal is greater than the amplitude of each fractional signal.

In one embodiment of this invention, load drive device is in order to the driven for emitting lights diode.This light emitting diode drive device comprises driving signal generator and controller.Driving signal generator couples light-emitting diode, in order to provide drive signal to light-emitting diode.Controller couples driving signal generator, and in order to reception PWM signal, and generation controls signal to driving signal generator.Wherein, N integer signal of generation and M fractional signal are to form drive signal in a light modulation cycle according to control signal for driving signal generator, and N and M are positive integer, and the amplitude of integer signal is greater than the amplitude of each fractional signal.

The present invention provides a kind of load driving method in addition, is suitable for control one switch, and switch couples a load, and wherein when switch conduction, a mark electric current is through load, and this load driving method may further comprise the steps: receive a PWM signal; Produce PWM output signal, this a PWM output signal and a light modulation clock signal are synchronous, and wherein this PWM output signal has the dimming period of carrying out, and one closes dimming period; And carrying out dimming period and closing dimming period, the ON time of control switch.

Based on above-mentioned, the present invention utilizes the one or more integer signal of generation and one or more fractional signals to combine to produce complete drive signal and drives load.Make in the time will opening or close complete drive signal, can increase progressively to open drive signal or to successively decrease and open drive signal through fractional signal to close.In addition, the present invention's fractional signal also capable of using comes under the situation that does not increase system frequency, to increase the resolution of drive signal adjustment.Thus, can effectively lower drive signal issuable electromagnetic interference phenomenon when being unlocked or close, promote whole usefulness.

For letting the above-mentioned feature and advantage of the present invention can be more obviously understandable, hereinafter is special lifts embodiment, and cooperates appended graphic elaborating as follows.

Description of drawings

Figure 1A is the sketch map of the drive unit of existing light-emitting diode.

Figure 1B is the oscillogram of drive unit of the light-emitting diode of Figure 1A.

Fig. 2 A is the sketch map of the load drive device 200 of one embodiment of the invention.

Fig. 2 B is the oscillogram of the drive signal of Fig. 2 A embodiment.

Fig. 3 is an execution mode of the driving signal generator 210 of the embodiment of the invention.

Fig. 4 A is an execution mode of the controller of load drive device of the present invention.

Fig. 4 B is the oscillogram of controller 400.

Fig. 5 is the flow chart of load driving method 500.

Reference numeral:

The 200-load drive device; The 210-driving signal generator; The 220-controller;

The 211-selector; 212-drive current generator; The 2121-reference current generator;

The 2122-current mirror; The 410-decoder; The 420-ALU;

CTRLS1～CTRLS3-divides numerical control

CTRLI-integer control section; SW0～SW3-switch;

The system part;

MN、M0～M3、MP1、MP2-

R1-resistance; The BUF1-buffer;

Transistor;

N1, N3, N4-end points; The AMP1-operational amplifier; The Iref-reference current;

IS-integer signal; FS1～FS3-fractional signal; VCC, VDD-supply voltage;

The LD1-light-emitting diode; The main electric current of II1-; IS1～IS3-mark electric current;

The Vref-reference voltage; PWM-PWM signal; The F0-input signal;

NDIT-closes dimming period; DIT-carries out dimming period; The CTRL-control signal;

UT-unit lights the time; The LT-light modulation cycle; The I1-current source;

The I-electric current; The F0-input signal; ENF, PULSE-signal;

DFF1, DFF2, DFF3-are positive and negative

INV1, INV2-not gate OR1, OR2, OR3-or door;

Device;

NOR1, NOR2-NOR gate; AND1～AND4-and door; X, Y, Z-decoded result;

PWMOUT-PWM output letter

CK-light modulation clock signal; CLK-clock pulse end;

Number;

The RST-end of resetting; The Q-output; D-data end;

The 400-controller; The POR-reset signal.

Embodiment

Please with reference to Fig. 2 A, Fig. 2 A is the sketch map of the load drive device 200 of one embodiment of the invention.Load drive device 200 in the present embodiment is coupled to the light-emitting diode LD1 of supply voltage VCC in order to driving.Load drive device 200 comprises driving signal generator 210 and controller 220.Driving signal generator 210 couples the light-emitting diode LD1 as load, with driving signal generator 210 to provide drive signal to light-emitting diode LD1.Above-mentioned drive signal can be drive current or driving voltage.Controller 220 couples driving signal generator 210, and in order to produce and to provide control signal CTRL to driving signal generator 210.

Note that at this N integer signal of generation and M fractional signal are to form drive signal in drive cycle according to control signal CTRL for driving signal generator 210, N wherein and M are positive integer.And the amplitude of these integer signals is greater than the amplitude of each fractional signal.

Below please be simultaneously with reference to Fig. 2 B and Fig. 2 A, Fig. 2 B is the oscillogram of the drive signal of Fig. 2 A embodiment.Wherein, the light modulation cycle is divided into and carries out dimming period DIT and close dimming period NDIT.Controller 220 transmits control signal CTRL and makes driving signal generator 210 produce integer signal IS or fractional signal FS1～FS3.At this embodiment, controller 220 makes driving signal generator 210 in carrying out dimming period DIT through control signal CTRL, produces integer signal IS and fractional signal FS1, and in closing dimming period NDIT, produces fractional signal FS2 and FS3.The amplitude of wherein fractional signal FS1, FS2 and FS3 is all less than the amplitude of integer signal IS.

Note that driving signal generator 210 the fractional signal FS1 that is produced more, FS2, FS3 away from integer signal IS ..., the amplitude of FSn, FSn+1 has trend decrescence, promptly the amplitude of FSn+1 is smaller or equal to the amplitude of FSn.In simple terms; The example that is depicted as with Fig. 2 B; Wherein the amplitude of fractional signal FS3 can be fractional signal FS2 amplitude 1/2nd, the amplitude of fractional signal FS2 then can be fractional signal FS1 amplitude 1/2nd, and fractional signal FS1 be integer signal IS amplitude 1/2nd.

Certainly, above-mentioned fractional signal FS1～FS3 relationship of amplitude also can be other ratio, and the proportionate relationship of the fractional signal FS1～FS3 amplitude of above-mentioned explanation only is an example, and is not used in limit the present invention.

Be not difficult to learn by illustrating of Fig. 2 A and Fig. 2 B; The load drive device 200 of the embodiment of the invention can be adjusted the luminosity of light-emitting diode LD1 through the number of adjustment fractional signal FS1～FS3 and integer signal IS, need not promote the frequency or the time in increase light modulation cycle of light modulation clock signal.And, through the generation of all right more effective reduction electromagnetic interference phenomenon of amplitude fractional signal FS1～FS3 decrescence.

Then please again with reference to Fig. 2 A, driving signal generator 210 comprises selector 211 and drive current generator 212.Drive current generator 212 receives and produces main electric current I I1 and a plurality of mark current IS 1～IS3 according to reference voltage Vref; Wherein current value is unequal to each other for each mark current IS 1, IS2 and IS3, and the current value of main electric current I I1 is greater than the current value of mark current IS 1, IS2 and IS3.

Selector 211 couples drive current generator 212.Selector 211 selects to export main electric current I I1 according to control signal CTRL, with/or select output mark current IS 1, IS2 and IS3.

Please be simultaneously with reference to Fig. 2 A and Fig. 2 B, when driving signal generator 210 needed to produce integer signal IS, selector 211 selected main electric current I I1 to export light-emitting diode LD1 to according to control signal CTRL.When driving signal generator 210 needed to produce fractional signal FS1,211 of selectors selected mark current IS 1 to export light-emitting diode LD1 to according to control signal CTRL.Relative, when driving signal generator 210 needed to produce fractional signal FS2 or FS3,211 of selectors selected mark current IS 2 or IS3 to export light-emitting diode LD1 to respectively according to control signal CTRL.

Below please with reference to Fig. 3, Fig. 3 is an execution mode of the driving signal generator 210 of the embodiment of the invention.Drive current generator 212 in the driving signal generator comprises reference current generator 2121 and current mirror 2122.Reference current generator 2121 receive and according to reference voltage Vref to produce reference current Iref.2122 of current mirrors couple reference current generator 2121.Current mirror 2122 mirror reference current Iref produce main electric current I I1 and mark current IS 1～IS3.

Reference current generator 2121 comprises operational amplifier A MP1, transistor MP1, MP2 and resistance R 1.The input of operational amplifier A MP1 receives reference voltage Vref.Transistor MP1 has first source/drain electrode, second source/drain electrode and the grid, and its first source/drain electrode receives supply voltage VCC, and its grid couples the output of operational amplifier A MP1, and its second source/drain electrode couples another input of operational amplifier A MP1.Transistor MP2 has first source/drain electrode, second source/drain electrode and the grid equally, and its first source/drain electrode receives supply voltage VCC, and its grid couples the grid of transistor MP1, and its second source/drain electrode produces reference current Iref.1 of resistance R is serially connected between the second source/drain electrode and earthed voltage GND of transistor MP1.

Current mirror 2122 comprises transistor MN and M0～M3.First source of transistor MN/drain electrode receives reference current Iref, and its second source/drain electrode couples earthed voltage GND, and its grid couples its first source/drain electrode.Second source/drain electrode of transistor M0～M3 is coupled to earthed voltage GND jointly; And the grid of transistor M0～M3 is coupled to the grid of transistor MN jointly, and first source/drain electrode of transistor M0～M3 produces main electric current I I1 and mark current IS 1～IS3 respectively.

211 of selectors come construction by a plurality of switch SW 0～SW3, and switch SW 0～SW3 is serially connected in respectively between the first source/drain electrode and light-emitting diode LD1 of transistor M0～M3.Switch SW 0 is controlled by the integer control section CTRLI of control signal CTRL, and switch SW 1～SW3 is controlled by mark control section CTRLS1～CTRLS3 of control signal CTRL respectively.Specifically, when switch SW 0 during according to the integer control section CTRLI conducting of control signal CTRL, main electric current I I1 stream is through light-emitting diode LD1.Relative, if during one of them mark control section CTRLS1 at least of switch SW 1～SW3～CTRLS3 conducting according to control signal, then among mark current IS 1～IS3 one of them can flow through light-emitting diode LD1 at least.

Below please with reference to Fig. 4 A and cooperate Fig. 2 A, Fig. 4 A is an execution mode of the controller of load drive device of the present invention.Controller 400 comprises the integer control signal generator of being made up of flip-flop DFF1 and buffer BUF1, and the mark control signal generator of being made up of decoder 410 and ALU 420.

In integer control signal generator, the data end D of flip-flop DFF1 receives PWM signal PWM, and its clock pulse end CLK receives the light modulation clock signal CK of high frequency more than PWM signal PWM, and its end RST that resets receives reset signal POR.Buffer BUF1 then is coupled to the output Q of flip-flop DFF1, and buffer BUF1 is in order to produce the integer control section CTRLI of control signal CTRL.In mark control signal generator, the decoder 410 receiving inputted signal F0 and the input signal F0 that decodes.420 of

ALUs couple decoder

410 and 410 decoded results that produce according to input signal F0 of Rcv decoder.ALU 420 produces mark control section CTRLS1～CTRLS2 according to above-mentioned decoded result and integer control section CTRLI.In addition, in this execution mode, ALU 420 receives the foundation that signal ENF is used as whether producing mark control section CTRLS1～CTRLS2 in addition.

On the running details of controller 400, please be simultaneously with reference to Fig. 4 A and Fig. 4 B, wherein Fig. 4 B is the oscillogram of controller 400.Wherein, flip-flop DFF1 makes PWM signal PWM and light modulation clock signal CK synchronous, produces PWM output signal PWMOUT.Wherein, When PWM output signal PWMOUT is high level; Represent controller 400 affiliated load drive devices to be in and carry out dimming period DI T; Opposite, when PWM output signal PWMOUT is low level, represents controller 400 affiliated load drive devices to be in and close dimming period NDIT.Because PWMOUT is synchronous with light modulation clock signal CK for PWM output signal; So can know that carrying out dimming period DIT lasts several clock pulses; And close dimming period NDIT and last several clock pulses; So controller 400 can be controlled in when carrying out dimming period DI T and cutting out which clock pulse of dimming period NDI T, output mark control signal.

Flip-flop DFF2 and DFF 3, not gate INV1, INV2 or door OR1 and NOR gate NOR1, NOR2 then dispose the falling edge that is used for according to PWM output signal PWMOUT and produce the signal PULSE of pulse.Wherein, signal PULSE produces pulse after a time of delay of the falling edge of PWM output signal PWMOUT.And end points N1, N3 and N4 are respectively the output of NOR gate NOR1, not gate I NV2 and flip-flop DFF3.

Signal PULSE is used for indicating the time point that produces mark control section CTRLS1～CTRLS2, and when signal PULSE was positive pulse, controller 400 produced mark control section CTRLS1～CTRLS2 according to input signal F0 and signal ENF.Explain that further in the present embodiment, decoder 410 decoding input signal F0 also produce decoded result X, Y and Z.Wherein, relation such as the following table of input signal F0 and decoded result X, Y and Z:

F0	X	Y	Z
				Suspension joint	High level	Low level	Low level
Low level	Low level	High level	Low level
				High level	Low level	Low level	High level

Decoded result X, Y and Z also transfer to or door OR2, OR3 and the logical circuit formed with door AND1～AND4; And reach following function: when signal ENF is high level; When input signal F0 is suspension joint; Mark control section CTRLS1 produces positive pulse signal, and not transition of mark control section CTRLS2 (maintenance low level).When input signal F0 is low level, mark control section CTRLS2 produces positive pulse signal, and not transition of mark control section CTRLS1 (maintenance low level).Or when input signal F0 is high level, mark control section CTRLS1 and CTRLS2 produce positive pulse signal.Produce mark current IS 1 and IS2 if mark control section CTRLS1 and CTRLS2 control respectively, then when and when signal ENF is high level, when input signal F0 is suspension joint, reference current generator generation mark current IS 1; When input signal F0 is low level, reference current generator produces mark current IS 2; When input signal F0 is high level, reference current generator produces mark current IS 1+IS2.

The controller of the load drive device shown in Fig. 4 A is the embodiment that is used for producing integer control signal CTRLI and two mark control signal CTRLS1 and CTRLS2.Yet those skilled in the art can spread to the embodiment of the more mark control signals of generation easily.

Fig. 5 is the flow chart of the load driving method 500 of another embodiment of the present invention.One controller when switch conduction, will make a mark electric current through load in order to control one or several switches with a load coupled.As shown in Figure 5, load driving method comprises: in step 502, receive PWM signal PWM; In step 504, make a PWM signal PWM and a light modulation clock signal CK synchronous, produce PWM output signal PWMOUT, wherein this PWM output signal PWMOUT has the dimming period of carrying out DIT, and one closes dimming period NDIT; Then, carry out step 506, promptly carrying out dimming period DIT and closing dimming period NDIT, the ON time of control switch.For example, shown in Fig. 2 B, in carrying out dimming period DIT, control one or time of several switch conductions is when being first and the 9th light modulation clock signal CK, and the mark size of current that flows through load is 1/2nd intensity; Closing among the dimming period NDIT of Fig. 2 B the right; The time of control switch conducting is when being first and second light modulation clock signal CK; Wherein in first light modulation clock signal CK; The amplitude that flows through the mark electric current of load is 1/4th of an integer electric current, and in second light modulation clock signal CK, the amplitude that flows through the mark electric current of load is 1/8th of an integer electric current.

Though the present invention discloses as above with embodiment, be not in order to limit the present invention, any person of ordinary skill in the field; Do not breaking away from the spirit and scope of the present invention; When doing a little change and retouching, therefore, protection scope of the present invention is worked as the scope that defines with claim and is as the criterion.

Claims

1. a load drive device is characterized in that, comprising:

One driving signal generator couples a load, in order to provide a drive signal to this load; And

One controller couples this driving signal generator, in order to producing and to provide one to control signal to this driving signal generator,

Wherein, this driving signal generator comes in a drive cycle, to produce N integer signal and M fractional signal to form this drive signal according to this control signal, and N and M are positive integer, and the amplitude of those integer signals is greater than the amplitude of this fractional signal respectively.

2. load drive device according to claim 1 is characterized in that, wherein this driving signal generator comprises:

One drive current generator receives and foundation one reference voltage produces main electric current and one or more mark electric current; And

One selector couples this drive current generator, selects this main electric current of output according to this control signal, or selects this mark electric current of output.

3. load drive device according to claim 2 is characterized in that, wherein this selector comprises:

Most switches are connected in series with this load, those switches respectively according to this control signal with conducting or disconnection.

4. a light emitting diode drive device is characterized in that, comprising:

One driving signal generator couples a light-emitting diode, in order to provide a drive signal to this light-emitting diode; And

One controller couples this driving signal generator, and in order to receiving a PWM signal, and produce one and control signal to this driving signal generator,

Wherein, this driving signal generator comes in a light modulation cycle, to produce N integer signal and M fractional signal to form this drive signal according to this control signal, and N and M are positive integer, and the amplitude of those integer signals is greater than the amplitude of this fractional signal respectively.

5. light emitting diode drive device according to claim 4 is characterized in that, wherein this driving signal generator comprises:

6. light emitting diode drive device according to claim 5 is characterized in that, wherein this selector comprises:

Most switches are connected in series with this light-emitting diode, those switches respectively according to this control signal with conducting or disconnection.

7. light emitting diode drive device according to claim 4 is characterized in that, wherein this controller comprises:

One flip-flop is used so that this a PWM signal and a light modulation clock signal are synchronous.

8. a load driving method is characterized in that, is suitable for control one switch, and this switch couples a load, and wherein when this switch conduction, a mark electric current is through this load, and this load driving method may further comprise the steps:

Receive a PWM signal;

Produce PWM output signal, this a PWM output signal and a light modulation clock signal are synchronous, and wherein this PWM output signal has the dimming period of carrying out, and one closes dimming period; And

Carry out dimming period and close dimming period at this, control the ON time of this switch.