CN102468306B - Array base plate, liquid crystal display, and manufacturing method for array substrate - Google Patents
Array base plate, liquid crystal display, and manufacturing method for array substrate Download PDFInfo
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- CN102468306B CN102468306B CN201010532011.6A CN201010532011A CN102468306B CN 102468306 B CN102468306 B CN 102468306B CN 201010532011 A CN201010532011 A CN 201010532011A CN 102468306 B CN102468306 B CN 102468306B
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Abstract
The invention discloses an array base plate, a liquid crystal display, and a manufacturing method for the array base plate. The array base plate comprises a substrate base plate; the substrate base plate is provided with a gate line, a data line, a thin film transistor, a pixel electrode and an active layer; the thin film transistor comprises a gate electrode, a source electrode, and a drain electrode; and the drain electrode is formed on the pixel electrode, and is connected with the pixel electrode. According to the technical scheme, the data line, the source electrode, the drain electrode, and the pixel electrode can be formed through one-time composition, so the composition frequency is reduced, and production efficiency is improved.
Description
Technical field
The present invention relates to lcd technology, relate in particular to the manufacture method of a kind of array base palte, liquid crystal display and array base palte.
Background technology
Liquid crystal display is current conventional flat-panel monitor, wherein Thin Film Transistor-LCD (ThinFilm Transistor Liquid Crystal Display, be called for short TFT-LCD) owing to thering is the advantages such as volume is little, low in energy consumption, radiationless, and become the main product in liquid crystal display.Conventionally TFT-LCD comprises liquid crystal panel, drive circuit and backlight.Liquid crystal panel is the critical piece in TFT-LCD, by array base palte and color membrane substrates, box is formed, and is filled with liquid crystal layer therebetween; The voltage providing by control drive circuit deflects ordered liquid crystal molecule, and the light and shade that produces light changes, and wherein the control of voltage is completed by thin-film transistor.The array base palte tft array substrate that is sometimes otherwise known as.
As shown in FIG. 1A and 1B, the structure of prior art tft array substrate comprises: underlay substrate 1, is formed with interface area (not shown) and pixel region on underlay substrate 1.Wherein, pixel region comprises the grid line 2 and the gate electrode 3 that are formed on underlay substrate 1, be formed on gate insulation layer 4, active layer 6 (can comprise semiconductor layer 61 and doping semiconductor layer 62) on gate electrode 3, on be formed with data wire 5, source electrode 7, drain electrode 8, passivation layer 9 and pixel electrode 11.Passivation layer 9 covers whole underlay substrate 1, and the top that is positioned at drain electrode 8 offers passivation layer via hole 10, and pixel electrode 11 is connected with drain electrode 8 by passivation layer via hole 10.Said structure is by several times thin film deposition and composition technique, to form pattern to complete, and one time composition technique forms a layer pattern.Form a layer pattern, first will on underlay substrate, deposit thin film; Then at film surface, apply one deck light-sensitive material, by mask plate, light-sensitive material is carried out to exposure imaging; Then by etching technics, carry out etching and form final pattern; Finally, light sensitive material is peeled off, and formed lower thin film pattern.Wherein, each layer pattern all will cover on another layer pattern accurately in accurate position; Every layer pattern can have identical or different material, and thickness is generally hundreds of nanometer to several microns.
Wherein, in the manufacturing process of array base palte, the number of times of mask used plate is fewer, and production efficiency is just higher, and cost is just lower.And four etching technics of common employing in prior art, use four gray tone mask plates (Gray Tone Mask) could form array base palte, the number of times of the mask plate that visible current manufacturing array substrate adopts need further minimizing, to enhance productivity, to reduce production costs.
Summary of the invention
The invention provides the manufacture method of a kind of array base palte, liquid crystal display and array base palte, in order to reduce the number of times that uses mask plate in array base palte manufacturing process, enhance productivity, reduce production costs.
The invention provides a kind of array base palte, comprise underlay substrate, on described underlay substrate, be formed with grid line, data wire, thin-film transistor, pixel electrode and active layer; Described thin-film transistor comprises gate electrode, source electrode and drain electrode; Described drain electrode is formed on described pixel electrode, and is connected with described pixel electrode.
The invention provides a kind of liquid crystal display, comprise arbitrary array base palte provided by the invention.
The manufacture method that the invention provides a kind of array base palte, comprising:
On underlay substrate, deposit grid metallic film, by composition technique, form the pattern that comprises gate electrode and grid line;
On the underlay substrate that forms above-mentioned pattern, deposit gate insulation layer film, transparent conductive film and source and leak metallic film, by composition technique, form the pattern that comprises gate insulation layer, pixel electrode, data wire, source electrode and drain electrode;
On the underlay substrate that forms above-mentioned pattern, deposit active layer film and passivation layer film, by composition technique, form the pattern that comprises active layer and passivation layer.
The manufacture method of array base palte provided by the invention, liquid crystal display and array base palte, adopts by a photoetching process and forms gate electrode and grid line; By a photoetching process, form gate insulation layer, source electrode, drain electrode, data wire and pixel electrode simultaneously; By photoetching process, form again the technical scheme of active layer and passivation layer, form the present invention and there is drain electrode and be positioned on pixel electrode, and the array base-plate structure being connected with pixel electrode.Technical solution of the present invention adopts third photo etching technique to form array base palte, has reduced the number of times that uses mask plate in array base palte manufacture process compared with four mask technique, has improved the production efficiency of array base palte, has reduced the production cost of array base palte.
Accompanying drawing explanation
Figure 1A is the fragmentary top TV structure schematic diagram of prior art array base palte;
Figure 1B dissects structural representation along the side-looking of A-A line in Figure 1A;
The fragmentary top TV structure schematic diagram of the array base palte that Fig. 2 A provides for the embodiment of the present invention one;
Fig. 2 B dissects structural representation along the side-looking of A-A line in Fig. 2 A;
Fig. 3 A is the local schematic top plan view that the embodiment of the present invention one formation comprises the array base palte after the pattern of grid line and gate electrode;
Fig. 3 B dissects structural representation along the side-looking of A-A line in Fig. 3 A;
Fig. 4 A is the local schematic top plan view that the embodiment of the present invention one formation comprises the array base palte after the pattern of gate insulation layer, pixel electrode, data wire, source electrode and drain electrode;
Fig. 4 B is for dissecing structural representation along the side-looking of A-A line in Fig. 4 A;
Fig. 5 A is the local schematic top plan view that the embodiment of the present invention one formation comprises the array base palte after the pattern of active layer and passivation layer;
Fig. 5 B dissects structural representation along the side-looking of A-A line in Fig. 5 A;
The flow chart of the manufacture method of the array base palte that Fig. 6 A provides for the embodiment of the present invention two;
Fig. 6 B is the flow chart of the implementation method of step 61 in the embodiment of the present invention two;
Fig. 6 C is the flow chart of the implementation method of step 62 in the embodiment of the present invention two;
Fig. 6 D is the flow chart of the implementation method of step 63 in the embodiment of the present invention two.
Reference numeral:
1-underlay substrate; 2-grid line; 3-gate electrode;
4-gate insulation layer; 5-data wire; 6-active layer;
61-semiconductor layer; 62-doping semiconductor layer; 7-source electrode;
8-drain electrode; 9-passivation layer; 10-passivation layer via hole;
11-pixel electrode; 71-transparent conductive film.
Embodiment
For making object, technical scheme and the advantage of the embodiment of the present invention clearer, below in conjunction with the accompanying drawing in the embodiment of the present invention, technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment in the present invention, those of ordinary skills, not making the every other embodiment obtaining under creative work prerequisite, belong to the scope of protection of the invention.
Embodiment mono-
The fragmentary top TV structure schematic diagram of the array base palte that Fig. 2 A provides for the embodiment of the present invention one; Fig. 2 B dissects structural representation along the side-looking of A-A line in Fig. 2 A.As shown in Figure 2 A and 2 B, the array base palte of the present embodiment comprises: underlay substrate 1, is formed with grid line 2, data wire 5, thin-film transistor (TFT), pixel electrode 11 and active layer 6 on underlay substrate 1.Wherein, TFT comprises gate electrode 3, source electrode 7 and drain electrode 8; Gate electrode 3 is connected with grid line 2, and source electrode 7 is connected with data wire 5, and drain electrode 8 is connected with pixel electrode 11.Wherein, drain electrode 8 is formed on pixel electrode 11, and is connected with pixel electrode 11.
In the array base palte that the present embodiment provides, drain electrode is formed at the structure on pixel electrode, can form by composition technique, can reduce the number of times of composition technique, reduces the number of times that uses mask plate, improve array base palte production efficiency, reduce production costs.
On the basis of technique scheme, the array base palte of the present embodiment also comprises gate insulation layer 4, and gate insulation layer 4 is formed at gate electrode 3 tops; Pixel electrode 11 is formed on gate insulation layer 4; And source electrode 7 and drain electrode 8 are formed on pixel electrode 11 with layer, and electrode 7 belows in source have transparent conductive film 71; Active layer 6 is positioned on source electrode 7 and drain electrode 8, and is connected with source electrode 7 and drain electrode 8 respectively.The said structure of array base palte can form by a composition technique, and gate insulation layer 4, pixel electrode 11, source electrode 7, drain electrode 8 and data wire 5 can be by being used a mask plate to form.
Wherein, active layer 6 is filled between source electrode 7 and drain electrode 8 and forms TFT raceway groove; When gate electrode 3 is carried sweep signal, can make source electrode 7 and drain electrode 8 by active layer 6 conductings, so that the data-signal that data wire 5 is carried by source electrode 7, offering pixel electrode 11 to control ordered liquid crystal molecule deflection, the light and shade that produces light changes.
Further again, the array base palte of the present embodiment also comprises passivation layer 9, and passivation layer 9 is formed on active layer 6, and the pattern of the pattern of passivation layer 9 and active layer 6 adapts, and passivation layer 9 only covers active layer 6 tops, does not cover the region outside active layer 6.This structure can be by being used a mask plate to be formed by a composition technique.
The array base palte of the present embodiment, by adopting pixel electrode to be arranged under source electrode, drain electrode, active layer is arranged to the structure on source electrode, drain electrode, make the array base palte of the present embodiment can adopt a photoetching process to form the pattern that comprises gate insulation layer, pixel electrode, source electrode, drain electrode and data wire simultaneously, reduced the number of times of composition technique, improved array base palte production efficiency, reduced production cost.And active layer is formed on source electrode and drain electrode in the structure of the present embodiment array base palte, while having solved etching TFT raceway groove, active layer is caused the problem of damage; And passivation layer above active layer can stop the impact of extraneous oxygen G&W on TFT raceway groove, therefore, the array base palte of the present embodiment has preferably performance.
Further, in the array base palte of the present embodiment, active layer can adopt the metal oxide of high mobility, preferably adopts amorphous metal oxide, for example: amorphous indium oxide gallium zinc (a-IGZO).Because amorphous metal oxide and the work function of the metal that forms source electrode and drain electrode differ less, make the contact resistance of active layer and source electrode and drain electrode smaller, therefore, do not need to increase ohmic contact layer and reduce the contact resistance between active layer and source electrode and drain electrode, active layer can directly contact (as shown in Figure 2 B) with source electrode with drain electrode.Pass through technique scheme, not only can omit and form the manufacturing process of falling ohmic contact layer, improve the production efficiency of array base palte, can also increase substantially array base palte performance (conventionally metal oxide be active layer while directly contacting with source leakage metal performance better).
Fig. 3 A-Fig. 5 B is the manufacture schematic diagram of the partial structurtes of the array base palte of the embodiment of the present invention one.Below in conjunction with the manufacturing process of the array base palte of the present embodiment, describe the technical scheme of the present embodiment in detail.And in the following description, the alleged composition technique of the present invention comprises techniques such as applying photoresist, mask, exposure imaging, etching and removal photoresist.
Fig. 3 A is the local schematic top plan view that the embodiment of the present invention one formation comprises the array base palte after the pattern of grid line and gate electrode; Fig. 3 B dissects structural representation along the side-looking of A-A line in Fig. 3 A.First, on underlay substrate 1, adopt method successive sedimentation a layer thickness of sputter or thermal evaporation to be about
grid metallic film.Wherein, underlay substrate 1 can be transparent glass substrate or quartz base plate.Grid metallic film can be used a kind of material, for example: the metal or alloy such as chromium (Cr), tungsten (W), titanium (Ti), tantalum (Ta), molybdenum (Mo), aluminium (Al), copper (Cu); Also can use the material being combined into by multiple layer metal.Then, by composition technique, grid metallic film is carried out to composition, on underlay substrate 1, form the pattern that comprises grid line 2 and gate electrode 3.Wherein, as shown in Figure 3A, gate electrode 3 is connected with grid line 2, in actual composition technique, is formed in one.Grid line 2 is for transmitting sweep signal, required voltage while providing conducting with the gate electrode 3 to TFT, and select with this TFT needing.
Wherein, the process that the present embodiment forms the composition technique of above-mentioned pattern specifically comprises: on grid metallic film, apply photoresist; Adopt monotone mask plate to carry out exposure imaging to photoresist, form and comprise the photoetching agent pattern of removing region and complete reserved area completely.Then carry out etching, etch away and remove grid metallic film corresponding to region completely, form the pattern that comprises gate electrode and grid line.Finally remove the photoresist of complete reserve area.By above-mentioned concrete composition technique, formed pattern as shown in Figure 3 A and Figure 3 B.
Fig. 4 A is the local schematic top plan view that the embodiment of the present invention one formation comprises the array base palte after the pattern of gate insulation layer, pixel electrode, data wire, source electrode and drain electrode.Fig. 4 B dissects structural representation along the side-looking of A-A line in Fig. 4 A.On the underlay substrate 1 that completes above-mentioned pattern, first using plasma strengthens chemical vapour deposition (CVD) (Plasma Chemical Vapor Deposition; Referred to as: PECVD) method successive sedimentation a layer thickness is about
gate insulation layer film, then adopt sputter or thermal evaporation method to deposit a layer thickness above above-mentioned gate insulation layer film and be about
transparent conductive film; Adopting sputter or thermal evaporation method to deposit a layer thickness above above-mentioned transparent conductive film is about again
source leak metallic film.Wherein, gate insulation layer film can adopt oxide, nitride or oxynitrides, and the reacting gas using in PECVD process can be silane (SiH
4), ammonia (NH
3), nitrogen (N
2) or dichloro hydrogen silicon (SiH
2cl
2), ammonia (NH
3), nitrogen (N
2).Transparent conductive film can adopt the materials such as tin oxide (ITO) or indium zinc oxide (IZO), also can adopt other metal and metal oxide.It can be the metal or alloy such as Cr, W, Ti, Ta, Mo that metallic film is leaked in source, and it can be a kind of single layer structure, can be also a kind of sandwich construction.After having deposited above-mentioned each layer film, by composition technique, above-mentioned three kinds of films are carried out to composition, form the pattern that comprises gate insulation layer 4, pixel electrode 11, data wire 5, source electrode 7 and drain electrode 8.
Wherein, above-mentioned formation comprises that the composition technique of the pattern of gate insulation layer 4, pixel electrode 11, data wire 5, source electrode 7 and drain electrode 8 specifically comprises: first, in source, leak on metallic film and apply photoresist; Adopt mask plate to carry out exposure imaging to photoresist, form and comprise complete reserve area, part reserve area and remove the photoetching agent pattern in region completely; Wherein, the photoresist thickness of part reserve area is less than the photoresist thickness of complete reserve area, is greater than the photoresist thickness of removing region completely.Wherein, mask used plate is gray tone mask plate or intermediate tone mask plate.Then, carry out etching for the first time, etch away and remove region corresponding source leakage metallic film and transparent conductive film completely, form the pattern that comprises gate insulation layer 4, source electrode 7 and data wire 5; Wherein gate insulation layer 4 is covered on whole underlay substrate 1, and electrode 7 belows in source are provided with transparent conductive film 71.Then, according to the photoresist thickness of part reserve area, carry out ashing and process removal photoresist.After this step, the photoresist of part reserve area is removed completely, and the photoresist of reserve area is partly removed completely.Next, carry out etching for the second time, etch away the source that part reserve area is corresponding and leak metallic film, form the pattern that comprises pixel electrode 11 and drain electrode 8.Finally, carry out photoresist Transformatin, according to the photoresist thickness of complete reserve area, remove photoresist, and obtain the structure shown in Fig. 4 B.
Further, in technique scheme, when formation comprises the pattern of source electrode 7 and data wire 5, can also directly form data-interface region.By this technical scheme, can further save the manufacture craft of array base palte, improve the production efficiency of array base palte.
Fig. 5 A is the local schematic top plan view that the embodiment of the present invention one formation comprises the array base palte after the pattern of active layer and passivation layer; Fig. 5 B dissects structural representation along the side-looking of A-A line in Fig. 5 A.First, on comprising the underlay substrate 1 of pattern of gate insulation layer 4, pixel electrode 11, data wire 5, source electrode 7 and drain electrode 8, formation adopt sputtering method deposition a layer thickness to be about
active layer film.Then, on above-mentioned active layer film, adopt method successive sedimentation a layer thickness of PECVD to be
passivation layer film.Wherein, active layer film can adopt metal oxide, is preferably amorphous metal oxide, for example: amorphous indium oxide gallium zinc (a-IGZO).Passivation layer film can adopt oxide, nitride or oxynitrides, and the reacting gas using in PECVD process can be silane (SiH
4), ammonia (NH
3), nitrogen (N
2) or dichloro hydrogen silicon (SiH
2cl
2), ammonia (NH
3), nitrogen (N
2).After the above-mentioned film of deposition, by composition technique, above-mentioned active layer film and passivation layer film are carried out to composition, form the pattern that comprises active layer 6 and passivation layer 9.
Wherein, the present embodiment formation comprises that the composition technique of the pattern of active layer 6 and passivation layer 9 comprises the following steps: first, on passivation layer film, apply photoresist; Adopt mask plate to carry out exposure imaging to photoresist, form and comprise complete reserve area and remove the photoetching agent pattern in region completely; Then, carry out etching, etch away and remove passivation layer film corresponding to region and active layer film completely, form the pattern that comprises active layer 6 and passivation layer 9; Then, according to the photoresist thickness in complete reserve area, remove residue photoresist, obtain pattern as shown in Figure 5 B.
In technique scheme, when forming active layer and passivation layer, can also form grid interface area.Concrete, grid interface area is also corresponding to the region of removal completely on mask plate, by etching technics, etch away successively this and remove passivation layer film corresponding to region, active layer film and gate insulation layer completely, grid interface using exposed portions serve grid line as the present embodiment, for being connected with external drive circuit.The technical scheme of the formation grid interface area that the present embodiment provides does not need additionally to increase the manufacturing process of array base palte equally, has guaranteed the production efficiency of array base palte.
In the above-mentioned technical solutions of this embodiment, in composition technique for the second time, formed the pattern of gate insulation layer, source electrode, drain electrode and pixel electrode simultaneously, and then made to have completed by three composition technique the array base palte of the embodiment of the present invention.Compared with existing four composition techniques, in the manufacture process due to the array base palte of the present embodiment, reduced the number of times of composition technique, therefore the array base palte of the present embodiment has higher production efficiency; In addition; the present embodiment is in manufacture process; owing to having adjusted the position relationship of passivation layer, active layer, pixel electrode and source electrode and drain electrode; after active layer is formed at source electrode and drain electrode; avoided the damage while forming TFT raceway groove, active layer being caused, and passivation layer is positioned on active layer, active layer has been played to protective effect; the performance of the array base palte that therefore, the present embodiment provides is better.
Embodiment bis-
The flow chart of the manufacture method of the array base palte that Fig. 6 A provides for the embodiment of the present invention two.As shown in Figure 6A, the method for the present embodiment comprises:
The array base palte that the manufacture method of the array base palte of the present embodiment can provide for the preparation of the embodiment of the present invention, the method possesses the step that forms corresponding construction.The manufacture method of the array base palte of the present embodiment forms by a composition technique pattern that comprises gate insulation layer, pixel electrode, data wire, source electrode and drain electrode simultaneously, makes to complete by three composition techniques the array base palte of the present embodiment.Compared with four composition techniques of the prior art, the manufacture method of the present embodiment has reduced the number of times of composition technique, can improve the efficiency of manufacturing array substrate, reduces production costs.Meanwhile, the manufacture method of the array base palte of the present embodiment, adopts first and leaks metallic film by deposition gate insulation layer film, transparent conductive film and source, after utilizing composition technique formation gate insulation layer, pixel electrode, source electrode and drain electrode; On above-mentioned pattern, deposit again active layer film, and by the technical scheme of composition technique formation active layer, making active layer be formed at source electrode forms with after drain electrode and is directly connected with both, solved while forming TFT raceway groove in prior art active layer has been caused to the problem of damage, and then improved the performance of the array base palte producing.
In technique scheme, in the present embodiment, step 61 specifically can be comprised of deposition and two techniques of composition, and depositing operation and composition technique is two independently processes, does not interdepend.The preferred implementation of a kind of deposition and composition technique wherein, is provided respectively in description below the present invention; , on the basis of above-mentioned preferred implementation, the step 61 of the present embodiment specifically comprises the operations such as deposition step, coating photoresist step, exposure imaging step, etch step and photoresist removal step.Specifically as shown in Figure 6B, the concrete enforcement of step 61 comprises:
Method deposit thickness on underlay substrate of step 611, employing sputter or thermal evaporation is
grid metallic film.
Further, in the present embodiment, step 62 specifically can be comprised of deposition and two techniques of composition, and depositing operation and composition technique is two independently processes, does not interdepend.The preferred implementation of a kind of deposition and composition technique wherein, is provided respectively in description below the present invention; , on the basis of above-mentioned preferred implementation, the step 62 of the present embodiment specifically comprises the operations such as deposition step, coating photoresist step, exposure imaging step, etch step and photoresist removal step.As shown in Figure 6 C, the step 62 of the present embodiment specifically comprises:
Step 620, adopt PECVD method in formation, to comprise successive sedimentation gate insulation layer film on the underlay substrate of pattern of grid line and gate electrode;
Step 621, employing sputter or thermal evaporation method deposit thickness on gate insulation layer film are
transparent conductive film;
Further, in the step 625 of the present embodiment, when generating source electrode and data wire, can also form data-interface region.Concrete, the region of removal completely of the photoetching agent pattern that this data-interface region forms corresponding to step 624, therefore, can be when etching for the first time and source electrode and data wire form data-interface region simultaneously.The present embodiment technical scheme can form data-interface region when forming source electrode and data wire, does not increase composition technique, makes the present invention can produce array base palte by three composition techniques, has guaranteed the production efficiency of array base palte.
On the basis of technique scheme, in the present embodiment, step 63 can be comprised of deposition and two techniques of composition equally, and depositing operation and composition technique is two independently processes, does not interdepend.The preferred implementation of a kind of deposition and composition technique wherein, is provided respectively in description below the present invention; , on the basis of above-mentioned preferred implementation, the step 63 of the present embodiment specifically comprises the operations such as deposition step, coating photoresist step, exposure imaging step, etch step and photoresist removal step.As shown in Figure 6 D, the step 63 of the present embodiment specifically comprises:
Step 632, employing PECVD method successive sedimentation thickness on active layer film are
passivation layer film;
Step 634, employing mask plate carry out exposure imaging to photoresist, form and comprise complete reserve area and remove the photoetching agent pattern in region completely;
In the present embodiment, when forming active layer and passivation layer, can be by etching away passivation layer film, active layer film and gate insulation layer on underlay substrate edge so that part grid line exposes to form grid interface area, this technical scheme does not need to increase the manufacturing process of array base palte, has guaranteed the production efficiency of array base palte.
Implement three
The embodiment of the present invention three provides a kind of liquid crystal display, comprises the parts such as outside framework, liquid crystal panel and drive circuit.Wherein liquid crystal panel is by color membrane substrates and array base palte provided by the invention, box to be formed, and is filled with liquid crystal layer betwixt.Wherein, array base palte can adopt the manufacture method manufacture of the array base palte that the embodiment of the present invention provides to form.About the structure of array base palte and the method flow of manufacturing array substrate, discuss no longer in detail in the present embodiment, can refer to the above embodiment of the present invention.
In sum, liquid crystal display of the present invention, owing to having array base palte provided by the invention, therefore, has advantages of that production efficiency is high, better performances equally.
One of ordinary skill in the art will appreciate that: all or part of step that realizes said method embodiment can complete by the relevant hardware of program command, aforesaid program can be stored in a computer read/write memory medium, this program, when carrying out, is carried out the step that comprises said method embodiment; And aforesaid storage medium comprises: various media that can be program code stored such as ROM, RAM, magnetic disc or CDs.
Finally it should be noted that: above embodiment only, in order to technical scheme of the present invention to be described, is not intended to limit; Although the present invention is had been described in detail with reference to previous embodiment, those of ordinary skill in the art is to be understood that: its technical scheme that still can record aforementioned each embodiment is modified, or part technical characterictic is wherein equal to replacement; And these modifications or replacement do not make the essence of appropriate technical solution depart from the spirit and scope of various embodiments of the present invention technical scheme.
Claims (13)
1. an array base palte, comprises underlay substrate, is formed with grid line, data wire, thin-film transistor, pixel electrode, active layer and passivation layer on described underlay substrate; Described thin-film transistor comprises gate electrode, source electrode and drain electrode; It is characterized in that:
Described drain electrode is formed on described pixel electrode, and is connected with described pixel electrode;
Described passivation layer only covers described active layer top.
2. array base palte according to claim 1, is characterized in that, described source electrode and described drain electrode are formed on described pixel electrode with layer; Described active layer is formed on described source electrode and described drain electrode, and is connected with described source electrode and described drain electrode.
3. array base palte according to claim 2, is characterized in that, also comprises: gate insulation layer; Described gate insulation layer is formed at described gate electrode top; Described pixel electrode is formed at described gate insulation layer top.
4. according to the array base palte described in claim 1-3 any one, it is characterized in that: the material of described active layer is amorphous metal oxide.
5. array base palte according to claim 4, is characterized in that: described amorphous metal oxide is amorphous indium oxide gallium zinc.
6. one kind comprises the liquid crystal display of the array base palte described in claim 1-5 any one.
7. a manufacture method for array base palte, is characterized in that, comprising:
On underlay substrate, deposit grid metallic film, by composition technique, form the pattern that comprises gate electrode and grid line;
On the underlay substrate that forms above-mentioned pattern, deposit gate insulation layer film, transparent conductive film and source and leak metallic film, by composition technique, form the pattern that comprises gate insulation layer, pixel electrode, data wire, source electrode and drain electrode;
On the underlay substrate that forms above-mentioned pattern, deposit active layer film and passivation layer film, by a composition technique, form the pattern that comprises active layer and passivation layer.
8. the manufacture method of array base palte according to claim 7, is characterized in that, deposits gate insulation layer film, transparent conductive film and source leakage metallic film and comprise on the underlay substrate that forms above-mentioned pattern:
Using plasma strengthens chemical gaseous phase depositing process successive sedimentation thickness on the underlay substrate that forms above-mentioned pattern
described gate insulation layer film;
Adopt sputter or thermal evaporation method deposit thickness on described gate insulation layer film to be
described transparent conductive film;
Adopt sputter or thermal evaporation method deposit thickness on described transparent conductive film to be
described source leak metallic film.
9. the manufacture method of array base palte according to claim 8, is characterized in that, the step that forms the pattern that comprises gate insulation layer, pixel electrode, data wire, source electrode and drain electrode by composition technique specifically comprises:
In described source, leak on metallic film and apply photoresist;
Adopt mask plate to carry out exposure imaging to described photoresist, form and comprise complete reserve area, part reserve area and remove the photoetching agent pattern in region completely;
Carry out etching for the first time, etch away described described source corresponding to region of removing completely and leak metallic film and described transparent conductive film, form the pattern that comprises described gate insulation layer, described source electrode and described data wire;
According to the photoresist thickness ashing of described part reserve area, remove photoresist;
Carry out etching for the second time, etch away the described source that described part reserve area is corresponding and leak metallic film, form the pattern that comprises described drain electrode and described pixel electrode;
Remove the photoresist of described complete reserve area.
10. the manufacture method of array base palte according to claim 7, is characterized in that, the step that deposits active layer film and passivation layer film on the underlay substrate that forms above-mentioned pattern comprises:
Adopt sputtering method deposit thickness on the underlay substrate that forms above-mentioned pattern to be
described active layer film;
Using plasma strengthens chemical gaseous phase depositing process successive sedimentation thickness on described active layer film
described passivation layer film.
The manufacture method of 11. array base paltes according to claim 10, is characterized in that, by a composition technique formation, comprises that the step of the pattern of active layer and passivation layer comprises:
On described passivation layer film, apply photoresist;
Adopt mask plate to carry out exposure imaging to described photoresist, form and comprise complete reserve area and remove the photoetching agent pattern in region completely;
Carry out etching, etch away described described passivation layer film corresponding to region and the described active layer film removed completely, form the pattern that comprises described active layer and described passivation layer;
Remove the photoresist of described complete reserve area.
The manufacture method of 12. array base paltes according to claim 11, is characterized in that: when forming described passivation layer and described active layer, form grid interface area.
13. according to the manufacture method of the array base palte described in claim 7-12 any one, it is characterized in that, the material of described active layer is amorphous metal oxide.
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| CN102779784A (en) * | 2012-06-15 | 2012-11-14 | 上海大学 | Thin film transistor array substrate manufacturing method |
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| CN102854685A (en) * | 2012-09-26 | 2013-01-02 | 南京中电熊猫液晶显示科技有限公司 | Metallic oxide fringing field switching mode liquid crystal display panel and manufacture method thereof |
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| CN104218041B (en) * | 2014-08-15 | 2017-12-08 | 京东方科技集团股份有限公司 | Array base palte and preparation method and display device |
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| US9793409B2 (en) | 2016-01-14 | 2017-10-17 | Hon Hai Precision Industry Co., Ltd. | Thin film transistor array panel |
| CN106601689B (en) * | 2016-12-08 | 2019-04-09 | 惠科股份有限公司 | Active switch array substrate and preparation method thereof |
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| CN113867043B (en) * | 2020-06-30 | 2023-01-10 | 京东方科技集团股份有限公司 | Light-emitting substrate, preparation method thereof and display device |
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| KR101363555B1 (en) * | 2006-12-14 | 2014-02-19 | 삼성디스플레이 주식회사 | Thin film transistor substrate and method of manufacturig the same |
| CN101634783B (en) * | 2008-07-23 | 2011-03-23 | 北京京东方光电科技有限公司 | Pixel structure of liquid crystal display panel of thin film transistor and manufacturing method |
| JP5602390B2 (en) * | 2008-08-19 | 2014-10-08 | 富士フイルム株式会社 | Thin film transistor, active matrix substrate, and imaging device |
| CN101807549B (en) * | 2009-02-18 | 2013-02-13 | 北京京东方光电科技有限公司 | TFT-LCD (Thin Film Transistor Liquid Crystal Display) array substrate and manufacture method thereof |
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