CN102457263A - Circuit and method for improving level shifter - Google Patents
Circuit and method for improving level shifter Download PDFInfo
- Publication number
- CN102457263A CN102457263A CN2010105283973A CN201010528397A CN102457263A CN 102457263 A CN102457263 A CN 102457263A CN 2010105283973 A CN2010105283973 A CN 2010105283973A CN 201010528397 A CN201010528397 A CN 201010528397A CN 102457263 A CN102457263 A CN 102457263A
- Authority
- CN
- China
- Prior art keywords
- level shifter
- circuit
- transistor
- set point
- voltage source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Logic Circuits (AREA)
Abstract
The invention discloses a circuit and method for improving a level shifter. Current-limiting circuits are connected in series between a latch and a voltage source of the level shifter, so as to limit a drive current of the latch within a set value, thereby reducing the current consumption of the level shifter during conversion; furthermore, the latch can be realized with a transistor having a relatively short channel length, so that the circuit area of the level shifter is reduced. More preferably, the set value is adjustable, so that the output drive capability of the level shifter can be adjusted, and the conversion speed of the level shifter is accelerated.
Description
Technical field
The present invention relates to a kind of level shifter (level shifter), particularly about a kind of circuit and method that improves level shifter.
Background technology
In general circuit, often need use the voltage source of multiple different potentials, when the signal of the voltage source of different potentials will be communicated with each other, signal needed earlier through level shifter the signal of different potentials to be adjusted to same potential, makes that circuit can normal operation.For example shown in Figure 1, change in the high-tension level shifter in existing low-voltage, transistor M1, M2 are used for amplifying low voltage complementary property input signal In1, In2; This input signal In1, In2 are generally logical one (maximum potential of low-voltage source VDD) or logical zero (SS is idiostatic with voltage source V), and In1, In2 be signal complimentary to one another, when signal In1 is logical one; Signal In2 is a logical zero; Otherwise when signal In1 was logical zero, signal In2 was a logical one; Transistor M3, M4 are the latchs that source electrode is received high voltage source VHH and grid, the mutual coupling of drain electrode, are used for the logical one of low-voltage source VDD input is converted to the logical one of high voltage source VHH input.At the complementary signal In1 of input low-voltage source VDD, when In2 arrives this level shifter; Can obtain complementary signal Out1, the Out2 of high voltage source VHH at output; And the logic of output signal Out1 can be identical with the logic of input signal In1, and the logic of output signal Out2 can be identical with the logic of input signal In2.For instance, when signal In1 is a logical one, when signal In2 was logical zero, output Out1 can produce the logical one of high voltage source VHH, and output Out2 can produce logical zero (current potential VSS).
Suppose that present input signal In1, In2 are respectively logical one and logical zero, then export signal Out1, Out2 can be fixed on logical one and logical zero.Under this state, transistor M1, M4 are in conducting state, and transistor M2, M3 are in cut-off state.If input signal In1, In2 are transformed into logical zero and logical one suddenly; Then transistor M2 meeting conducting; Transistor M1 can end, and still is in original state (logical one and logical zero) but export signal Out1, Out2 this moment, does not convert logical zero and logical one as yet to; Therefore transistor M4 still is in conducting state, and transistor M3 still is in cut-off state.Under this transient state, owing to transistor M2, M4 are in conducting state simultaneously, therefore there is leakage current to flow to low-voltage source VSS through transistor M2, M4 from high voltage source VHH, cause power loss.In addition; After input signal conversion, output signal Out1 will be when logical one converts logical zero to, but because transistor M2, M4 conducting simultaneously; Cause transistor M2 will output signal Out1 be pulled low to the VSS current potential, and transistor M4 to draw high the dragsaw phenomenon to the VHH current potential with output signal Out1.In order to let output signal Out1 change smoothly, prior art takes to increase the passage length of transistor M4, makes its current driving ability be lower than transistor M2.But can increase circuit area like this, make the IC cost improve.
Summary of the invention
One of the object of the invention is to propose a kind of level shifter that reduces current sinking.
One of the object of the invention is to propose a kind of level shifter that reduces circuit area.
One of the object of the invention is to propose a kind of level shifter of adjusting the output driving force.
According to the present invention; A kind of circuit and method that improves level shifter; Be between the latch of this level shifter and voltage source, to be connected in series the drive current that current-limiting circuit limits this latch to be no more than certain set point; Thereby reduce the current sinking of this level shifter when conversion, and can use than the transistor of jitty length and realize this latch, the circuit area of this level shifter dwindled.
The preferably, this set point is adjustable, uses the output driving force of this level shifter of adjustment, accelerates the conversion speed of this level shifter.
Description of drawings
Accompanying drawing described herein is used to provide further understanding of the present invention, constitutes the application's a part, does not constitute qualification of the present invention.In the accompanying drawings:
Fig. 1 changes high-tension level shifter for existing low-voltage;
Fig. 2 is the first embodiment of the present invention;
Fig. 3 is the voltage level of logical states of the level shifter of Fig. 2;
Fig. 4 is the second embodiment of the present invention; And
Fig. 5 is the voltage level of logical states of the level shifter of Fig. 4.
Drawing reference numeral:
10 level shifters
12 current-limiting circuits
The voltage level of 14 input signals
16 output voltage of signals positions are accurate
18 level shifters
20 current-limiting circuits
The voltage level of 22 input signals
24 output voltage of signals positions are accurate
Embodiment
For making the object of the invention, technical scheme and advantage clearer, the embodiment of the invention is explained further details below in conjunction with accompanying drawing.At this, illustrative examples of the present invention and explanation thereof are used to explain the present invention, but not as to qualification of the present invention.
As shown in Figure 2, to change high-tension level shifter 10 with the low-voltage of Fig. 1 and be the basis, serial connection current-limiting circuit 12 is between its latch and high voltage source VHH.Current-limiting circuit 12 comprises between the latch and high voltage source VHH that transistor M5 is connected level shifter 10, and suspension control signal Ctrl1 controls its electric current.When control signal Ctrl1 was lower voltage, transistor M5 can provide bigger electric current, otherwise when control signal Ctrl1 was higher voltage, the available electric current of transistor M5 was less.This Improvement type level shifter is when normal running, and control signal Ctrl1 is certain specific voltage, to set the maximum current that transistor M5 can produce.This specific voltage can be any reference voltage source.Suppose that present input signal In1, In2 are respectively logical one and logical zero, then export logical one and logical zero that signal Out1, Out2 can be fixed on high voltage source VHH.The voltage level that voltage level that the logical states of low-voltage source VDD is corresponding and the logical states of high voltage source VHH are corresponding is as shown in Figure 3, and waveform 14 is pointed out the voltage level of input signal In1, In2, and waveform 16 points out to export the voltage level of signal Out1, Out2.When input signal In1, In2 are transformed into logical zero and logical one suddenly; Transistor M2, M4 are in conducting state simultaneously; Thereby produce a drain current path from high voltage source VHH to low-voltage source VSS; But because of the relation of transistor M5, this leakage current can be limited in the electric current that transistor M5 can provide, and therefore reduces the consumed power of level shifter when conversion of signals.In addition; When transistor M2, M4 dragsaw; Because the current limitation effect of transistor M5, the electric current that draws on the transistor M4 have only the size of restriction electric current, make and draw ability force rate available circuit little much on it; Therefore need the passage length of transistor M4 not strengthened and limit its drive current, the output signal is changed smoothly.Thus, just can use less area to realize the function of position quasi displacement circuit.
The preferably, the restriction electric current of transistor M5 is adjustable, with the output driving force of adjustment position quasi displacement circuit.For example shown in Figure 2, current-limiting circuit 12 comprises between the grid Ctrl and voltage source V SS that transistor M6 is connected transistor M5, and suspension control signal Ctr2 control is with the restriction electric current of adjustment transistor M5.When the load of level shifter hour, control signal Ctrl2 is fixed on logical zero, so transistor M6 is cut-off state, the electric current of transistor M5 is by the voltage control of control signal Ctrl1.When load is big; Control signal Ctrl2 is set in logical one, high and low voltage source all can, so transistor M6 is a conducting state; The grid voltage Ctrl of transistor M5 is pulled down to logical zero; Make the complete conducting of transistor M5 to reach the effect that increases drive current, thereby accelerate the conversion speed of position quasi displacement circuit.
Fig. 4 is the second embodiment of the present invention, and wherein level shifter 18 is available circuits, is used for the current potential VSS of the logical zero of input signal is transformed into than its lower VLL current potential.With reference to Fig. 5, waveform 22 is pointed out the voltage level of input signal In1, In2, and waveform 24 points out to export the voltage level of signal Out1, Out2.In this Improvement type level shifter, current-limiting circuit 20 is serially connected between the latch and voltage source V LL of level shifter 18.Current-limiting circuit 20 comprises the control of transistor M7 suspension control signal Ctrl3, and the transistor M5 among its function and Fig. 2 is identical.In addition, the transistor M8 in the current-limiting circuit 20 is connected between the grid Ctrl3 and voltage source V DD of transistor M7, suspension control signal Ctr4 control, and the transistor M6 among its function and Fig. 2 is identical.
More than be stated as the purpose of illustrating for what preferred embodiment of the present invention was done; And be not intended to limit the present invention accurately is the form that is disclosed; Based on above instruction or to make an amendment or change from embodiments of the invention study be possible; Embodiment is for explaining orally principle of the present invention and let those skilled in the art utilize the present invention in practical application, to select with various embodiment and narrate, and technological thought of the present invention is decided by claim scope and equalization thereof.
Claims (12)
1. a circuit of improveing level shifter is characterized in that, has the drive current that a current-limiting circuit limits said latch between the latch of said level shifter and the voltage source and is no more than a set point.
2. the circuit of improvement level shifter as claimed in claim 1 is characterized in that, said set point is adjustable.
3. the circuit of improvement level shifter as claimed in claim 1 is characterized in that, said current-limiting circuit comprises a strings of transistors and is connected between said latch and the said voltage source, has a control end and accepts a control signal to determine said set point.
4. the circuit of improvement level shifter as claimed in claim 3 is characterized in that, said circuit more comprises another transistor and is connected between said control end and another voltage source, has a control end and accepts another control signal to adjust said set point.
5. the circuit of improvement level shifter as claimed in claim 4 is characterized in that, said another control signal is according to the said set point of load size adjustment of said level shifter.
6. the circuit of improvement level shifter as claimed in claim 5 is characterized in that, said set point is bigger value when the load of said level shifter is big.
7. a method that improves level shifter is characterized in that, between the latch of said level shifter and voltage source, is connected in series the drive current that a current-limiting circuit limits said latch and is no more than a set point.
8. the method for improvement level shifter as claimed in claim 7 is characterized in that, said set point is adjustable.
9. the method for improvement level shifter as claimed in claim 7 is characterized in that, said method comprises and applies the transistor that control signal control one is serially connected between said latch and the said voltage source, to determine said set point.
10. the method for improvement level shifter as claimed in claim 9 is characterized in that, said method more comprises the said control signal of change to adjust said set point.
11. the method for improvement level shifter as claimed in claim 10 is characterized in that, said control signal changes according to the load size of said level shifter.
12. the method for improvement level shifter as claimed in claim 11 is characterized in that, said set point is adjusted to bigger value when the load of said level shifter is big.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010105283973A CN102457263A (en) | 2010-11-01 | 2010-11-01 | Circuit and method for improving level shifter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010105283973A CN102457263A (en) | 2010-11-01 | 2010-11-01 | Circuit and method for improving level shifter |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102457263A true CN102457263A (en) | 2012-05-16 |
Family
ID=46040018
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010105283973A Pending CN102457263A (en) | 2010-11-01 | 2010-11-01 | Circuit and method for improving level shifter |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102457263A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5162681A (en) * | 1990-12-12 | 1992-11-10 | Samsung Electronics Co., Ltd. | Differential sense amplifier |
| CN1720585A (en) * | 2002-12-06 | 2006-01-11 | 桑迪士克股份有限公司 | Current-limited latch |
| US20070115041A1 (en) * | 2004-04-21 | 2007-05-24 | Fujitsu Limited | Level conversion circuit |
-
2010
- 2010-11-01 CN CN2010105283973A patent/CN102457263A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5162681A (en) * | 1990-12-12 | 1992-11-10 | Samsung Electronics Co., Ltd. | Differential sense amplifier |
| CN1720585A (en) * | 2002-12-06 | 2006-01-11 | 桑迪士克股份有限公司 | Current-limited latch |
| US20070115041A1 (en) * | 2004-04-21 | 2007-05-24 | Fujitsu Limited | Level conversion circuit |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9531350B2 (en) | Level shifters for IO interfaces | |
| CN101944905B (en) | A voltage level shifter | |
| CN103856205B (en) | Level shifting circuit, for driving the drive circuit of high tension apparatus and corresponding method | |
| CN102324922B (en) | Low voltage difference signal drive circuit and digital signal conveyer | |
| CN101420223B (en) | Differential transmitter | |
| CN104348473A (en) | High speed level shifter with amplitude servo loop | |
| CN102420594A (en) | Comparator | |
| CN105207658B (en) | Output buffer | |
| CN101951246B (en) | Quiescent voltage level restorer | |
| CN105897252A (en) | Level shifter circuit applied to display device | |
| CN101741374B (en) | Voltage level converter without phase distortion | |
| CN111294042B (en) | Level shift circuit | |
| CN107835011A (en) | A kind of high reliability tristate output circuit | |
| CN110098830B (en) | Substrate switching circuit and level conversion circuit of transistor | |
| CN108712166B (en) | Self-adaptive level conversion circuit | |
| CN106330172B (en) | The transmission gate of high voltage threshold device and its subsequent pull-down circuit structure | |
| CN103684420A (en) | Buffer for raising voltage driving capability | |
| CN102457263A (en) | Circuit and method for improving level shifter | |
| US11476839B2 (en) | LVDS driver | |
| US7227414B2 (en) | Apparatus for receiver equalization | |
| CN204794932U (en) | Pin drive circuit | |
| CN209562534U (en) | A kind of universal serial bus high-speed driving circuit | |
| TW201218627A (en) | capable of reducing the current consumption of a level shifter during logic transition and downsizing the circuit area of a level shifter | |
| CN112532230A (en) | Level conversion circuit | |
| CN102025365B (en) | Driver for reducing voltage swing |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20120516 |