CN102456663B - 半导体器件及其制造方法 - Google Patents
半导体器件及其制造方法 Download PDFInfo
- Publication number
- CN102456663B CN102456663B CN201110309782.3A CN201110309782A CN102456663B CN 102456663 B CN102456663 B CN 102456663B CN 201110309782 A CN201110309782 A CN 201110309782A CN 102456663 B CN102456663 B CN 102456663B
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- Prior art keywords
- semiconductor chip
- electrode
- semiconductor device
- semiconductor
- electrically connected
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- 238000000034 method Methods 0.000 title claims abstract description 51
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- 238000000227 grinding Methods 0.000 description 5
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000004411 aluminium Substances 0.000 description 3
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- 229910052737 gold Inorganic materials 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 238000009434 installation Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
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- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
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Abstract
本发明提供一种半导体器件及其制造方法。该半导体器件包括:第一半导体芯片,其包括穿透其至少一部分的第一穿透电极和第二穿透电极,第一穿透电极具有第一突出高度,第二穿透电极具有高于第一突出高度的第二突出高度;第二半导体芯片,其与第一穿透电极电连接;以及第三半导体芯片,其与第二穿透电极电连接。
Description
技术领域
本发明涉及一种半导体器件及其制造方法,更具体地说涉及一种具有穿透电极的半导体器件及其制造方法。
背景技术
目前,电子工业的趋势是以低廉的价格来制造轻量化、小型化、高速化、多功能化、以及高性能化的产品。为了实现该目标,使用多芯片堆叠封装技术或者***级封装技术。多芯片堆叠封装技术或者***级封装技术使用穿透电极(硅穿孔电极或者硅贯通电极,throughsiliconvia)。
多芯片堆叠封装或者***级封装可以在一个半导体封装件中执行多个单元的半导体器件的功能。多芯片堆叠封装或者***级封装与普通的单芯片封装相比多少变厚,但是平面上与单芯片封装的大小大致相同,因此主要用于如便携式电话机、笔记本电脑、存储卡、便携式摄像机等那样既是高功能且同时要求小型或者移动性的产品中。
发明内容
本发明的一个目的在于,提供一种半导体器件,其具有用于堆
叠大小不同的多个半导体器件的穿透电极。
本发明的另一个目的在于,提供一种半导体器件的制造方法,该半导体器件具有用于堆叠大小不同的多个半导体器件的穿透电极。
本发明的再一个目的在于,提供一种包括所述半导体器件的半导体封装件。
本发明的目的不限于上面提及的目的,本领域的技术人员能够通过下面的记载来明确地理解没有提及的其它目的。
为了实现上述一个目的,本发明提供一种半导体器件。该半导体器件可以包括第一半导体芯片,所述第一半导体芯片包括穿透其至少一部分的第一穿透电极和第二穿透电极,第一穿透电极具有第一突出高度且第二穿透电极具有与第一突出高度不同的第二突出高度。
第二突出高度可以大于第一突出高度。
第二穿透电极可以设置在比第一穿透电极距第一半导体芯片的中央更远的距离处。
第二穿透电极可以具有宽于第一穿透电极的宽度。
所述半导体器件还可以包括与第一穿透电极电连接的第二半导体芯片,以及与第二穿透电极电连接的第三半导体芯片。
第三半导体芯片的平面面积可以大于第二半导体芯片的平面面积。
所述半导体器件还可以包括置于第二半导体芯片和第三半导体芯片之间的粘合材料层。
第一至第三半导体芯片可以是非易失性存储器器件、动态随机存取存储器器件以及逻辑器件中的相互不同的器件。
第一半导体芯片还可以包括第三穿透电极,其具有大于第二突出高度的第三突出高度。
第三穿透电极可以设置在比第二穿透电极距第一半导体芯片的中央更远的距离处。
所述半导体器件还可以包括与第三穿透电极电连接的第四半导体芯片。
第四半导体芯片的平面面积可以大于第三半导体芯片的平面面积。
为了实现上述另一个目的,本发明提供了一种半导体器件的制造方法。该方法可以包括:形成穿透第一半导体芯片的至少一部分的第一和第二穿透电极;将第二半导体芯片与第一穿透电极电连接;以及将第三半导体芯片与第二穿透电极电连接。第一穿透电极具有第一突出高度,第二穿透电极具有第二突出高度,第二突出高度与第一突出高度不同。
第二突出高度可以大于第一突出高度。
第二穿透电极可以被形成在比第一穿透电极距第一半导体芯片的中央更远的距离处。
形成穿透第一半导体芯片的至少一部分的第一和第二穿透电极的步骤可以包括:制备具有第一面和与第一面相对的第二面的衬底;形成暴露衬底的第一面的将要形成第一通孔的部分的第一光致抗蚀剂图案;通过以第一光致抗蚀剂图案为掩模的刻蚀工艺来形成第一深度的第一通孔;去除第一光致抗蚀剂图案;形成暴露衬底的第一面的将要形成第二通孔的部分的第二光致抗蚀剂图案;通过以第二光致抗蚀剂图案为掩模的刻蚀工艺来形成与第一深度不同的第二深度的第二通孔;去除第二光致抗蚀剂图案;形成分别填充第一和第二通孔的第一和第二穿透电极;以及从衬底的第二面去除衬底的一部分来暴露第一和第二穿透电极。
形成穿透第一半导体芯片的至少一部分的第一和第二穿透电极的步骤可以包括:制备具有第一面和与第一面相对的第二面的衬底;形成暴露衬底的第一面的将要形成第一和第二通孔的部分的光致抗蚀剂图案;通过以光致抗蚀剂图案为掩模的刻蚀工艺来形成第一和第二通孔;去除光致抗蚀剂图案;形成分别填充第一和第二通孔的第一和第二穿透电极;以及从衬底的第二面去除衬底的一部分来暴露第一和第二穿透电极。光致抗蚀剂图案可以具有暴露衬底的第一面的将要形成第一通孔的部分的第一开口和暴露衬底的第一面的将要形成第二通孔的部分的第二开口,第一和第二开口的宽度彼此不同。
第二通孔可以被形成为具有宽于第一通孔的宽度。
第二通孔可以被形成在比第一通孔距第一半导体芯片的中央更远的距离处。
第三半导体芯片的平面面积可以大于第二半导体芯片的平面面积。
将第二和第三半导体芯片分别与第一和第二穿透电极电连接的步骤可以包括:将第二半导体芯片的焊垫与第一穿透电极电连接;在第二半导体芯片的第二面上形成粘合材料层,其中第二半导体芯片的第二面与设置了焊垫的第一面相对;以及将第三半导体芯片的焊垫与第二穿透电极电连接。第三半导体芯片的设置了焊垫的第一面可以通过粘合材料层与第二半导体芯片的第二面粘接。
将第二和第三半导体芯片分别与第一和第二穿透电极电连接的步骤可以包括:在第三半导体芯片的设置了焊垫的第一面上,以不覆盖焊垫的方式形成粘合材料层;将第二半导体芯片安装在粘合材料层上,使得第二半导体芯片的与设置了焊垫的第一面相对的第二面朝向粘合材料层;以及将第二和第三半导体芯片的焊垫同时分别与第一和第二穿透电极电连接,其中,在第三半导体芯片上安装了第二半导体芯片。
所述的半导体器件的制造方法还可以包括:形成穿透第一半导体芯片的第三穿透电极;以及将第四半导体芯片与第三穿透电极电连接。第三穿透电极可以大于第一和第二突出高度。
第四半导体芯片的平面面积可以大于第三半导体芯片的平面面积。
将第四半导体芯片与第三穿透电极电连接的步骤可以包括:将第四半导体芯片的焊垫与第三穿透电极电连接。第四半导体芯片的设置了焊垫的第一面和第三半导体芯片的与设置了焊垫的第一面相对的第二面可以通过粘合材料层来粘接。
为了实现上述再一个目的,本发明提供一种半导体封装件。该半导体封装件可以包括:配线板,具有设置在第一面上的焊盘和设置在与第一面相对的第二面上的球焊盘;以及半导体器件,其安装在配线板的第一面上。半导体器件可以包括:第一半导体芯片,其包括穿透其至少一部分的第一穿透电极和第二穿透电极,第一穿透电极具有第一突出高度,第二穿透电极具有高于第一突出高度的第二突出高度;第二半导体芯片,其与第一穿透电极电连接;以及第三半导体芯片,其与第二穿透电极电连接。第一和第二穿透电极的一端与配线板的焊盘电连接,所述一端与电连接至第二和第三半导体芯片的第一和第二穿透电极的另一端相对。
所述半导体封装件还可以包括设置在配线板的球焊盘上的焊球。
第一和第二穿透电极的所述一端可以通过连接端子与配线板的焊盘电连接。
第一和第二穿透电极的所述一端可以通过焊线与配线板的焊盘电连接。
如上所述,根据本发明的目的实现方式,半导体器件具有具备相互不同的突出高度的穿透电极,因此能够堆叠大小不同的多个半导体器件。由此,能够提供半导体器件以及包括该半导体器件的半导体封装件,所述半导体器件包括具有多种大小和功能的多个半导体器件。
附图说明
图1是用于说明根据本发明的一个实施例的半导体器件的截面图。
图2a至图2e是用于说明根据本发明的一个实施例的半导体器件的制造方法的一个例子的截面图。
图3a至图3d是用于说明根据本发明的一个实施例的半导体器件的制造方法的其它例子的截面图。
图4是用于说明根据本发明的另一实施例的半导体器件的截面图。
图5是用于说明根据本发明的再一实施例的半导体器件的截面图。
图6是用于说明根据本发明的再一实施例的半导体器件的截面图。
图7是用于说明根据本发明的再一实施例的半导体器件的截面图。
图8是用于说明根据本发明的再一实施例的半导体器件的截面图。
图9至图11是表示根据本发明的实施例的半导体封装件的截面图。
图12是表示根据本发明的实施例的封装件模块的平面图。
图13是表示根据本发明的实施例的存储卡的框图。
图14是表示根据本发明的实施例的电子***的框图。
图15是根据本发明的实施例的电子装置的立体图。
具体实施方式
下面,参照附图详细地说明本发明的优选实施例。通过参照附图详细进行说明的实施例,能够明确本发明的优点和特征、以及实现这些的方法。但是,本发明不限于在说明书中所说明的实施例,而是能够以其他方式来具体实现。在说明书中公开的实施例是为了能够使公开的内容充分完整,并且能够向本领域的技术人员充分传达本发明的思想而提供的。本发明的范围只由权利要求所限定。在整个说明书中,相同的附图标记表示相同的结构元素。
在本说明书中所使用的术语是为了说明实施例,并不是用于限定本发明。在本说明书中,除了特别提及之外,单数形式也可以表示多个。在说明书中使用的“包括”以及/或者“包括…的”并不排斥除了所提及的结构要素、工艺、动作以及/或者器件之外还存在或者追加一个以上的其它结构要素、工艺、动作以及/或者器件。另外,由于附图标记是按照优选实施例来出现的,因此根据说明顺序出现的附图标记并没有限定必须是该顺序。此外,在本说明书中,在提到某个层位于其它层或者衬底上的情况下,这意味着能够直接形成在其它层或者衬底上、或者能够在它们之间存在中间层。
另外,在本说明书中所记载的实施例将参照作为本发明的理想的示意截面图以及/或者平面图来进行说明。在附图中,为了技术内容的有效说明,对层以及区域的厚度进行了放大。因此,示意图的形态能够根据制造技术以及/或者允许误差等而变化。由此,本发明的实施例不限于图示的特定方式,还包括根据制造工艺所产生的方式的变化。例如,图示为直角的刻蚀区域可以是圆形或具有规定曲率的方式。由此,在附图中例示的区域具有概要属性。在附图中例示的区域的形态是为了例示器件的区域的特定方式,并不是限定本发明的范围。
图1是用于说明根据本发明的一个实施例的半导体器件的截面图。为了说明的便利,以半导体芯片和穿透电极为主简单地进行图示。
参照图1,半导体器件100包括第一半导体芯片110a、第二半导体芯片120以及第三半导体芯片130。第一至第三半导体芯片110a、120、130可以包括集成电路(未图示)。集成电路可以设置在第一至第三半导体芯片110a、120、130的内部。集成电路可以是堆叠能够实现高容量化、集成化、***化的器件而形成的。集成电路可以包括晶体管或者存储器器件。
与集成电路电连接的焊垫122或者132可以设置在第一、第二或者/以及第三半导体芯片110a、120或者/以及130上。焊垫122或者132可以由铝(A1)或者铜(Cu)形成。在焊垫122或者132由铝形成的情况下,焊垫122或者132可以设置在集成电路上。在焊垫122或者132由铜形成的情况下,焊垫122或者132可以以金属镶嵌结构包括在集成电路内。
第一和第二穿透电极115a、115b被设置为与第一半导体芯片110a的集成电路隔离开而穿透第一半导体芯片110a。第一和第二穿透电极115a、115b可以包括银(Ag)、金(Au)、铜、钨(W)或者铟(In)。第一和第二穿透电极115a、115b可以设置在***电路区域(未图示)。可替换地,在第一半导体芯片110a与第二和第三半导体芯片120、130相同地具有焊垫122或者132的情况下,第一和第二穿透电极115a、115b可以形成为穿透焊垫122或者132、或者与焊垫122或者132重叠。
虽未图示,但是第二和第三半导体芯片120、130也可以分别具有穿透它们的穿透电极(参照图11的124或者134)。
第一和第二穿透电极115a、115b可以从第一半导体芯片110a的一个表面突出。第一和第二穿透电极115a、115b可分别具有作为相互不同的突出高度的第一和第二突出高度。优选地,根据本发明的实施例,穿透半导体器件100的第一半导体芯片110a的第一和第二穿透电极115a、115b中的第二穿透电极115b的第二突出高度大于第一穿透电极115a的第一突出高度。此时,第二穿透电极115b可以设置在比第一穿透电极115a距第一半导体芯片110a的中央更远的距离处。即,位于距第一半导体芯片110a的中央较近的距离处的第一穿透电极115a具有较小的第一突出高度,位于比第一穿透电极115a距第一半导体芯片110a的中央更远的距离处的第二穿透电极115b具有比第一穿透电极115a的第一突出高度更高的第二突出高度。而且,可以另外设置附加穿透电极(参照图7的115c),该附加穿透电极可以设置在比第二穿透电极115b距第一半导体芯片110a的中央更远的距离处,并可以具有比第二穿透电极115b的第二突出高度更高的第三突出高度。其结果,第一半导体芯片110a可以具有从其中央到边缘突出高度依次变高的穿透电极结构。
第二和第三半导体芯片120、130可以分别与第一和第二穿透电极115a、115b电连接。第二和第三半导体芯片120、130可以通过分别设置在第二和第三半导体芯片120、130上的焊垫122、132来与第一和第二穿透电极115a、115b电连接。第三半导体芯片130的平面面积可以比第二半导体芯片120的平面面积大。但是,第三半导体芯片130的平面面积可以与第一半导体芯片110a的平面面积相同或比它更小。在第二和第三半导体芯片120、130之间,可以布置用于实现它们之间的粘接的粘合材料层125。
根据本发明的实施例的半导体器件100,可以具有如下结构:第一半导体芯片110a具有从其中央到边缘突出高度依次变高的穿透电极结构,因此可以具有大小以及功能不同的多个半导体芯片120、130、……堆叠在第一半导体芯片110a上的结构。由此,可以提供包括具有多种大小以及功能的多个半导体芯片110a、120、130、……的半导体器件100。
例如,第一半导体芯片110a可以是非易失性存储器(NVM)器件,第二半导体芯片120可以是动态随机存取存储器(DRAM)器件,而且第三半导体芯片130可以是逻辑器件。包括这种第一至第三半导体芯片110a、120、130的半导体器件100可以用作电子***。
另外,例如,第一和第二半导体芯片110a、120可以是存储器器件,而第三半导体芯片130可以是如印刷电路板等那样的配线板。包括这种第一至第三半导体芯片110a、120、130的半导体器件100可以是半导体封装件的一种形式。
图2a至图2e是用于说明根据本发明的一个实施例的半导体器件的制造方法的一个例子的截面图。
参照图2a,制备具有第一面和与第一面相对的第二面的衬底110。衬底110可以是硅晶片。可以在衬底110内部或者在第一面上形成集成电路(未图示)。在集成电路上可以形成与集成电路电连接的焊垫(未图示)。例如在由铝形成焊垫的情况下,焊垫可以形成在集成电路上。例如在由铜形成焊垫的情况下,焊垫可以形成为以金属镶嵌结构包括在集成电路内。
在衬底110的第一面上形成第一光致抗蚀剂图案112a。第一光致抗蚀剂图案112a可以暴露衬底110的第一面的将要形成第一通孔114a的部分。
通过以第一光致抗蚀剂图案112a为掩模的刻蚀工艺,形成从衬底110的第一面凹进至第一深度的第一通孔114a。第一通孔114a可以形成在***电路区域(未图示)中。可替换地,第一通孔114a可以形成为穿透焊垫或者与焊垫重叠。
第一通孔114a可以利用干法刻蚀、湿法刻蚀、利用激光的钻孔或者机械钻孔来形成。第一通孔114a的第一深度比集成电路的厚度大,比衬底110的厚度小,因此可以与衬底110的第二面隔离开。
参照图2b,在去除了第一光致抗蚀剂图案112a之后,在形成第一通孔114a的衬底110上形成第二光致抗蚀剂图案112b。第二光致抗蚀剂图案112b可以暴露衬底110的第一面的将要形成第二通孔114b的部分。
根据以第二光致抗蚀剂图案112b为掩模的刻蚀工艺,形成从衬底110的第一面凹进至不同于第一通孔114a的第一深度的第二深度的第二通孔114b。根据本发明的实施例的第一和第二通孔114a、114b可以具有相互不同的深度。优选地,第二通孔114b的第二深度大于第一通孔114a的第一深度。由此,第二通孔114b可以形成在比第一通孔114a距被衬底110的划片道区域划分的各个裸片的中央更远的距离处。第二通孔114b可以形成在***电路区域中。可替换地,第二通孔114b可以形成为穿透焊垫或者与焊垫重叠。
第二通孔114b可以利用干法刻蚀、湿法刻蚀、利用激光的钻孔或者机械钻孔来形成。第二通孔114b的第二深度比第一通孔114a的第一深度大,比衬底110的厚度小,因此可以与衬底110的第二面隔离开。
参照图2c,在去除了第二光致抗蚀剂图案112b之后,形成分别填充第一和第二通孔114a、114b的第一和第二穿透电极115a、115b。可以通过利用穿透电极用配线图案填充第一以及第二通孔114a、114b的内部并对其进行图案化来形成第一以及第二穿透电极115a、115b。穿透电极用配线图案可以使用电镀方法、非电解镀层方法或者选择性沉积方法来形成在第一和第二通孔114a、114b的内部。电镀方法可以包括:在第一和第二通孔114a、114b各自的内表面形成晶种层之后,利用晶种层来对穿透电极用配线图案进行电镀。晶种层可以通过溅射方法来形成。第一和第二穿透电极115a、115b可以包括银、金、铜、钨或者铟。
由于第二通孔114b的第二深度比第一通孔114a的第一深度大,因此第二穿透电极115b可以具有比第一穿透电极115a长的长度。第一和第二穿透电极115a、115b可以形成为在衬底110的第一面上延伸,或者可以形成为穿透焊垫或与焊垫重叠,使得与焊垫电连接。
虽未图示,但是还可以在衬底110上形成附加的至少一个通孔。即,可以在衬底110上形成具有与第一和第二通孔114a、114b不同的深度的附加的第三通孔。
参照图2d,从形成了第一和第二穿透电极115a、115b的衬底110的第二面去除衬底110的一部分来暴露第一和第二穿透电极115a、115b。可以通过两个步骤的工艺来暴露第一和第二穿透电极115a、115b。第一步骤工艺可以是如下的研磨工艺:在衬底110的第一面上利用粘合材料层(未图示)来附着载体衬底(未图示)之后,研磨衬底110的第二面直到接近第二穿透电极115b。第二步骤工艺可以是如下的刻蚀工艺:选择性地刻蚀衬底110的第二面使得第一和第二穿透电极115a、115b从衬底110的第二面突出。第一步骤工艺可以利用研磨方式,而第二步骤工艺可以利用湿法刻蚀或者干法刻蚀方式。
载体衬底可以用于如下目的:在研磨衬底110的第二面的第一步骤工艺中缓和作用于衬底110的机械应力,防止通过第一步骤工艺实现薄型化的衬底110中可能产生的翘曲。载体衬底可以包括玻璃衬底或者树脂衬底。粘合材料层可以包括在粘接后容易分离的可再加工粘接剂,即紫外线粘接剂或者热塑性粘接剂。
由于第二穿透电极115b具有比第一穿透电极115a长的长度,因此从衬底110的第二面突出的第二穿透电极115b的突出高度可以比第一穿透电极115a的突出高度大。
在从衬底110的第二面暴露第一以及第二穿透电极115a、115b之后,去除载体衬底以及粘合材料层。
在从衬底110的第二面暴露第一以及第二穿透电极115a、115b之后,通过衬底切割装置按照衬底110的划片道区域进行切割,由此被划片道区域划分的裸片被分离,可以分离成各个第一半导体芯片110a。
参照图2e,将第二和第三半导体芯片120、130分别与第一半导体芯片110a的第一和第二穿透电极115a、115b电连接。第三半导体芯片130的平面面积可以比第二半导体芯片120的平面面积大。
可以通过以下方法将第二和第三半导体芯片120、130分别与第一和第二穿透电极115a、115b电连接:将第二半导体芯片120的焊垫122与第一穿透电极115a电连接,在第二半导体芯片120的与设置了焊垫122的第一面相对的第二面上形成粘合材料层125,并且将第三半导体芯片130的焊垫132与第二穿透电极115b电连接。此时,第三半导体芯片130的设置了焊垫132的第一面能够通过粘合材料层125与第二半导体芯片120的第二面进行粘接。
可替换地,可以通过下述方法将第二和第三半导体芯片120、130分别与第一和第二穿透电极115a、115b电连接:在第三半导体芯片130的设置了焊垫132的第一面上,以不覆盖焊垫132的方式形成粘合材料层125,并将第二半导体芯片120安装在粘合材料层125上,使得第二半导体芯片120的与设置了焊垫122的第一面相对的第二面朝向粘合材料层125,由此将第二半导体芯片120安装在第三半导体芯片130上,之后,将第二和第三半导体芯片120、130的焊垫122、132同时分别与第一和第二穿透电极115a、115b电连接。
可替换地,还可以在将衬底110分离成各个第一半导体芯片110a之前,将第二和第三半导体芯片120、130分别与第一和第二穿透电极115a、115b电连接。可以通过上述两个方法将第二和第三半导体芯片120、130分别与第一和第二穿透电极115a、115b电连接。在将第二和第三半导体芯片120、130分别与第一和第二穿透电极115a、115b电连接之后,通过衬底切割装置按照衬底110的划片道区域进行切割,由此被划片道区域划分的裸片被分离,可以分离成各个半导体器件(参照图1的100)。
图3a至图3d是用于说明根据本发明的一个实施例的半导体器件的制造方法的其它例子的截面图。在前述的根据本发明的实施例的半导体器件的制造方法中已经说明的结构要素使用相同的附图标记,并省略对其的详细说明。
参照图3a,制备具有第一面和与第一面相对的第二面的衬底110。在衬底110的第一面上形成光致抗蚀剂图案112c。光致抗蚀剂图案112c可以暴露衬底110的第一面的将要形成第一和第二通孔114a1、114b1的部分。
光致抗蚀剂图案112c可以具有暴露衬底110的第一面的将要形成第一通孔114a1的部分的第一开口以及暴露衬底110的第一面的将要形成第二通孔114b1的部分的第二开口。光致抗蚀剂图案112c的第一和第二开口的宽度可以相互不同。优选地,暴露衬底110的第一面的将要形成第二通孔114b1的部分的第二开口的宽度比暴露衬底110的第一面的将要形成第一通孔114a1的部分的第一开口的宽度宽。
通过以光致抗蚀剂图案112c为掩模的刻蚀工艺来形成从衬底110的第一面凹进相互不同的深度的第一和第二通孔114a1、114b1。第一和第二通孔114a1、114b1根据刻蚀工艺凹进相互不同的深度,这是因为光致抗蚀剂图案112c的第一和第二开口的宽度相互不同,从而衬底110被刻蚀的速度具有差异。根据本发明的实施例的第一和第二通孔114a1、114b1可以具有相互不同的深度和宽度。优选地,第二通孔114b1的第二深度可以比第一通孔114a1的第一深度大,而且第二通孔114b1的宽度可以比第一通孔114a1的宽度宽。由此,第二通孔114b1可以形成在比第一通孔114a1距被衬底110的划片道区域划分的各个裸片的中央更远的距离处。
第一和第二通孔114a1、114b1各自的第一和第二深度比集成电路(未图示)的厚度大,比衬底110的厚度小,因此可以与衬底110的第二面隔离开。
虽未图示,但在衬底110中还可以形成附加的至少一个通孔。即,可以在衬底110上形成具有与第一和第二通孔114a1、114b1不同的深度和宽度的附加的第三通孔。
参照图3b,在去除了光致抗蚀剂图案112c之后,形成分别填充第一和第二通孔114a1、114b1的第一和第二穿透电极115a1、115b1。可以通过利用穿透电极用配线图案填充第一和第二通孔114a1、114b1的内部,并对其进行图案化来形成第一和第二穿透电极115a1、115b1。
由于第二通孔114b1的第二深度比第一通孔114a1的第一深度大,因此第二穿透电极115b1可具有比第一穿透电极115a1长的长度。
参照图3c,从形成了第一和第二穿透电极115a1、115b1的衬底110的第二面去除衬底110的一部分来暴露第一和第二穿透电极115a1、115b1。暴露第一和第二穿透电极115a1、115b1可以通过两个步骤的工艺来进行。第一步骤工艺可以是如下的研磨工艺:在衬底110的第一面上使用粘合材料层(未图示)来附着载体衬底(未图示)之后,研磨衬底110的第二面直到接近第二穿透电极115b1。第二步骤工艺可以是如下的刻蚀工艺:选择性地刻蚀衬底110的第二面使得第一和第二穿透电极115a1、115b1从衬底110的第二面突出。
由于第二穿透电极115b1具有比第一穿透电极115a1长的长度,因此从衬底110的第二面突出的第二穿透电极115b1的突出高度比第一穿透电极115a1的突出高度大。
在使第一和第二穿透电极115a1、115b1从衬底110的第二面暴露之后,去除载体衬底以及粘合材料层。
在从衬底110的第二面暴露第一和第二穿透电极115a1、115b1之后,通过衬底切割装置按照衬底110的划片道区域进行切割,由此被划片道区域划分的裸片被分离,可以分离成各个第一半导体芯片110a。
参照图3d,将第二和第三半导体芯片120、130分别与第一半导体芯片110a的第一和第二穿透电极115a1、115b1电连接。第三半导体芯片130的平面面积可以比第二半导体芯片120的平面面积大。
可以通过下述方法将第二和第三半导体芯片120、130分别与第一和第二穿透电极115a1、115b1电连接:将第二半导体芯片120的焊垫122与第一穿透电极115a1电连接,在第二半导体芯片120的与设置了焊垫122的第一面相对的第二面上形成粘合材料层125,并且将第三半导体芯片130的焊垫132电连接在第二穿透电极115b1上。此时,第三半导体芯片130的设置了焊垫132的第一面可以通过粘合材料层125与第二半导体芯片120的第二面相互粘接。
可替换地,可以通过下述方法将第二和第三半导体芯片120、130分别与第一和第二穿透电极115a1、115b1电连接:在第三半导体芯片130的设置了焊垫132的第一面上以不覆盖焊垫132的方式形成粘合材料层125,将第二半导体芯片120安装在粘合材料层125上,使得第二半导体芯片120的与设置了焊垫122的第一面相对的第二面朝向粘合材料层125,由此将第二半导体芯片120安装在第三半导体芯片130上,之后,将第二和第三半导体芯片120,130的焊垫122,132同时分别与第一和第二穿透电极115a1、115b1电连接。
可替换地,还可以在分离为各个第一半导体芯片110a之前,将第二和第三半导体芯片120、130分别与第一和第二穿透电极115a1、115b1电连接。可以通过上面说明的两个方法来将第二和第三半导体芯片120、130分别与第一和第二穿透电极115a1、115b1电连接。在将第二和第三半导体芯片120、130分别与第一和第二穿透电极115a1、115b1电连接之后,通过衬底切割装置按照衬底110的划片道区域进行切割,由此被划片道区域划分的裸片被分离,可以分离成各个半导体器件。
图4是用于说明根据本发明的其它实施例的半导体器件的截面图。在图4中,通过前述的本发明的实施例所说明的结构要素使用相同的附图标记,省略对其的详细说明。
参照图4说明的根据本发明的其它实施例的半导体器件与前述的根据本发明的实施例的半导体器件(图1的100)的不同点在于,具有如下结构:还包括设置在第一半导体芯片110a和与其电连接的第二和第三半导体芯片120、130之间的底部填充物质(underfill)150。
底部填充物质150可以在覆盖第二和第三半导体芯片120,130的侧面的同时被填充在第一半导体芯片110a和与其电连接的第二和第三半导体芯片120、130之间。底部填充物质150可以是注入在第一半导体芯片110a和与其电连接的第二和第三半导体芯片120、130之间的液态树脂固化而成的。
图5是用于说明根据本发明的另外其它实施例的半导体器件的截面图。在图5中,通过前述的本发明的实施例所说明的结构要素使用相同的附图标记,省略对其的详细说明。
参照图5说明的根据本发明的其它实施例的半导体器件与前述的根据本发明的实施例的半导体器件(图1的100)的不同点在于,具有如下结构:第一半导体芯片110a的第一和第二穿透电极115a、115b穿透第一半导体芯片110a的一部分。
半导体芯片110a可以包括形成在衬底110的第一面上的集成电路116。集成电路116的种类可以根据半导体芯片110a的种类而不同。例如,可以包括选自存储器电路、逻辑电路或者其组合中的至少一种。集成电路116可以包括晶体管或者存储器器件。另外,集成电路116可以是包括电阻器或者电容器的无源器件。集成电路116可以通过绝缘层111从外部得到保护。
第一和第二穿透电极115a、115b可以形成为在形成集成电路116之前穿透衬底110。第一和第二穿透电极115a、115b可以通过设置在绝缘层111内部的配线图案(未图示)来与集成电路116电连接。
前述的根据本发明的实施例的半导体器件(图1的100)的第一半导体芯片的穿透电极,形成为在形成半导体芯片之后完全穿透半导体芯片,相反地,根据本实施例的半导体器件的第一半导体芯片110a的第一和第二穿透电极115a、115b,形成为在形成半导体芯片的过程中穿透作为半导体芯片110a的一部分的衬底110。
图6和图7是用于说明根据本发明的另外其它实施例的半导体器件的截面图。在图6和图7中,通过前述的本发明的实施例所说明的结构要素使用相同的附图标记,省略对其的详细说明。
参照图6所说明的根据本发明的其它实施例的半导体器件与前述的根据本发明的实施例的半导体器件(图1的100)的不同点在于,具有如下结构:还包括附加的第一半导体芯片110aa。
附加的第一半导体芯片110aa可以具有与第一半导体芯片110a类似的结构。但是,附加的第一半导体芯片110aa与第一半导体芯片110a不同之处在于,穿透电极115aa都具有相同的突出高度。附加的第一半导体芯片110aa可以通过穿透电极115aa堆叠在第一和第二穿透电极115a、115b的一端上来与其电连接,所述一端与电连接至第二和第三半导体芯片120、130的第一和第二穿透电极115a、115b的另一端相对。
在第一半导体芯片110a和附加的第一半导体芯片110aa为存储器器件的情况下,可以实现半导体器件的高容量化。
参照图7所说明的根据本发明的其它实施例的半导体器件与前述的根据本发明的实施例的半导体器件(图1的100)不同点在于,具有如下结构:第一半导体芯片110a还包括第三穿透电极115c。
第三穿透电极115c设置在比第二穿透电极115b距第一半导体芯片110a的中央更远的距离处,并且可以具有比第二穿透电极115b的第二突出高度更大的第三突出高度。其结果,第一半导体芯片110a可以具有如下穿透电极结构:从其中央越接近边缘,突出高度越高。
第四半导体芯片140以与第三穿透电极115c电连接。第四半导体芯片140可以通过设置在第四半导体芯片140上的焊垫142来与第三穿透电极115c电连接。第四半导体芯片140的平面面积可以比第三半导体芯片130的平面面积大。在第三和第四半导体芯片130、140之间可以存在用于它们之间的粘接的粘合材料层135。
在第四半导体芯片140为具有与第一至第三半导体芯片110a、120、130不同的大小以及功能的器件的情况下,可以实现半导体器件的高集成化以及多功能化。
图8是用于说明根据本发明的另外其它实施例的半导体器件的截面图。在图8中,通过前述的本发明的实施例所说明的结构要素使用相同的附图标记,省略对其的详细说明。
参照图8所说明的根据本发明的其它实施例的半导体器件与前述的根据本发明的实施例的半导体器件(图1的100)的不同点在于,具有如下结构:第一半导体芯片110a包括具有相同突出高度的穿透电极115。
第一半导体芯片110a的穿透电极115都具有相同的突出高度。但是,在位于距第一半导体芯片110a的中央更远的距离处的穿透电极115上附加设置了凸块115ab,因此在与第一半导体芯片110a的中央邻近的穿透电极115和位于距第一半导体芯片110a的中央更远的距离处的附加了凸块115ab的穿透电极115之间产生突出高度之差。由此,第二半导体芯片120可以与邻近第一半导体芯片110a的中央的具有小的突出高度的穿透电极115电连接,而第三半导体芯片130可以与位于距第一半导体芯片110a的中央更远的距离处的具有大的突出高度的附加了凸块115ab的穿透电极115电连接。
图9至图11是表示根据本发明的实施例的半导体封装件的截面图。
参照图9,半导体封装件200a包括半导体器件100、配线板210、连接端子220s以及模塑层230。参照图1所说明的实施例可以应用于半导体器件100。半导体器件100包括:第一半导体芯片110a,其包括具有第一突出高度的第一穿透电极115a以及具有比第一突出高度高的第二突出高度的第二穿透电极115b;第二半导体芯片120,其与第一穿透电极115a电连接;以及第三半导体芯片130,其与第二穿透电极115b电连接。
配线板210可以包括连接至其内部的电路图案(未图示)的上部面的焊盘212以及下部面的球焊盘214。半导体器件100可以安装在配线板210的上部面上。配线板210可以是印刷电路板。配线板210的焊盘212与半导体器件100的第一半导体芯片110a的第一和第二穿透电极115a、115b电连接。在配线板210的球焊盘214上可以设置用于与外部电路电连接的焊球216。
在半导体器件100中,第一和第二穿透电极115a、115b的一端可以通过连接端子220s与配线板210的焊盘212连接,所述一端与电连接至第二和第三半导体芯片120、130的第一和第二穿透电极115a、115b的另一端相对。即,半导体器件100以倒装芯片(F/C)方式安装在配线板210的上部面上。连接端子220s可以是从由导电凸块、焊球、导电隔板、引脚网格阵列(PGA)以及它们的组合构成的组中选择的一个。
模塑层230可以覆盖配线板210的上部面以及半导体器件100。模塑层230可以包括环氧模塑料(EMC)。
虽未图示,但还可以包括底部填充物质(参照图4的150),所述底部填充物质在覆盖第二和第三半导体芯片120、130的侧面的同时,填充第一半导体芯片110a和与其电连接的第二和第三半导体芯片120、130之间。
参照图10,半导体封装件200b包括半导体器件100、配线板210、焊线220w以及模塑层230。为了说明的便利,省略对与图9相同的结构的详细说明,重点说明不同点。
半导体器件100可以以粘合材料层215为媒介安装在配线板210的上部面上。即,采用的是半导体器件100的第三半导体芯片130的第二面以粘合材料层215为媒介粘接在配线板210上的方式。配线板210的焊盘212与半导体器件100的第一半导体芯片110a的第一和第二穿透电极115a、115b电连接。在半导体器件100中,第一和第二穿透电极115a、115b的一端可以通过焊线220w与配线板210的焊盘212连接,所述一端与电连接至第二和第三半导体芯片120、130的第一和第二穿透电极115a、115b的另一端相对。
参照图11,半导体封装件200c包括半导体器件100、配线板210、连接端子(未图示)以及模塑层230。为了说明的便利,省略对与图9相同的结构的详细说明,重点说明不同点。
第二和第三半导体芯片120、130可以具有各自的穿透电极124、134。第二半导体芯片120的穿透电极124可以与第一半导体芯片110a的第一穿透电极115a电连接,而第三半导体芯片130的穿透电极134可以与第一半导体芯片110a的第二穿透电极115b电连接。第二半导体芯片120的穿透电极124与第三半导体芯片130的焊盘131连接,可以将第二半导体芯片120和第三半导体芯片130之间彼此电连接。这是因为:设置在第三半导体芯片130内部的配线图案(未图示)将第三半导体芯片130的焊盘131和穿透电极134彼此电连接。在第二半导体芯片120的穿透电极124的一端和与其电连接的第三半导体芯片130的焊盘131的一端之间还可以设置连接端子(图9的220s)。
在半导体器件100中,第三半导体芯片130的穿透电极134的一端可以与配线板210的焊盘212连接,所述一端面对电连接至第一半导体芯片110a的穿透电极134的另一端。在第三半导体芯片130的穿透电极134的所述一端和配线板210的焊盘212之间还可以设置连接端子(图9的220s)。即,半导体器件100以倒装芯片的方式安装在配线板210的上部面上。
图12是表示根据本发明的实施例的封装件模块700的平面图。
参照图12,封装件模块700可以包括:具备外部连接端子708的模块衬底702、安装在模块衬底702上的半导体芯片704以及QFP(四侧引脚扁平封装)的半导体封装件706。半导体芯片704以及/或者半导体封装件706可以包括根据本发明的实施例的半导体器件。封装件模块700可以通过外部连接端子708与外部电子装置连接。
图13是表示根据本发明的实施例的存储卡800的概要图。
参照图13,存储卡800可以在外壳810内包括控制器820和存储器830。控制器820和存储器830可以交换电信号。例如,根据控制器820的命令,存储器830和控制器820可以发送和接收数据。由此,存储卡800可以向存储器830存储数据或者从存储器830向外部输出数据。
控制器820以及/或者存储器830可以包括根据本发明的实施例的半导体器件或者半导体封装件中的至少一个。例如,控制器820可以包括***级封装(图9的200a、图10的200b或者图11的200c),存储器830可以包括多芯片封装(包括如图6所示的堆叠第一半导体芯片110a和110aa的半导体器件的封装件)。或者,控制器820以及/或者存储器830可以以堆叠型封装件(堆叠如图9的200a或者/以及图10的200b那样的封装件的封装件)来提供。这种存储卡800可以用作多种便携用设备的数据存储介质。例如,存储卡800可以包括多媒体卡(MMC)或者安全数字(SD)卡。
图14是表示根据本发明的实施例的电子***900的框图。
参照图14,电子***900可以包括至少一个根据本发明的实施例的半导体器件或者半导体封装件。电子***900可以包括移动设备或计算机等。例如,电子***900可以包括存储器***912、处理器914、随机存取存储器916,以及用户接口918,它们可以利用总线920来互相进行数据通信。处理器914可以起到执行程序并控制电子***900的作用。随机存取存储器916可以用作处理器914的操作存储器。例如,处理器914以及随机存取存储器916可以分别包括根据本发明的实施例的半导体器件或者半导体封装件。或者,处理器914和随机存取存储器916可以包括在一个封装内。用户接口918可以用于向电子***900输入数据或者从电子***900输出数据。存储器***912可以存储用于处理器914的操作的代码、被处理器914处理的数据或者从外部输入的数据。存储器***912可以包括控制器以及存储器,可以与图13的存储卡800实质上相同地构成。
电子***(图14的900)可以适用于多种电子设备的电子控制装置中。图15图示了电子***(图14的900)适用于便携式电话1000的例子。除此之外,电子***(图14的900)可以适用于笔记本电脑、MP3播放器、导航仪、固态硬盘(SSD)、汽车或者家电产品中。
以上参照附图说明了本发明的实施例,但是在本发明所属的技术领域中具有普通知识的技术人员应该理解能够在不变更技术思想或必要特征的情况下以不同的具体方式来实施本发明。因此,应当理解以上记述的实施例中都用于例示而不用于限定。
附图标记说明
100:半导体器件;110:衬底;110a、110aa、120、130、140:半导体芯片;111:绝缘层;112a、112b、112c:光致抗蚀剂图案;114a、114a1、114b、114b1:通孔;115、115a、115a1、115aa、115b、115b1、115c、124、134:穿透电极;115ab:凸块;116:集成电路;122、132、142:焊垫;125、135、215:粘合材料层;131、212:焊盘;150:底部填充物质;200a、200b、200c:半导体封装件;210:配线板;214:球焊盘;216:焊球;220s:连接端子;220w:焊线;230:模塑层;700:封装件模块;702:模块衬底;704:半导体芯片;706:半导体封装件;708:外部连接端子;800:存储卡;810:外壳;820:控制器;830:存储器;900:电子***;912:存储器***;914:处理器;916:随机存取存储器;918:用户接口;920:总线;1000:便携式电话。
Claims (28)
1.一种半导体器件,包括:
第一半导体芯片,所述第一半导体芯片包括穿透其至少一部分的第一穿透电极和第二穿透电极,第一穿透电极和第二穿透电极从所述第一半导体芯片的一个表面突出,第一穿透电极具有第一突出高度且第二穿透电极具有与所述第一突出高度不同的第二突出高度;
第二半导体芯片,其与所述第一穿透电极的突出的一端电连接;以及
第三半导体芯片,其与所述第二穿透电极的突出的一端电连接,
其中,在所述第一半导体芯片与所述第二半导体芯片之间以及在所述第一半导体芯片与所述第三半导体芯片之间形成有空间,使得所述第一穿透电极延伸至所述第一半导体芯片与所述第二半导体芯片之间的空间,并且所述第二穿透电极延伸至所述第一半导体芯片与所述第三半导体芯片之间的空间。
2.如权利要求1所述的半导体器件,其特征在于,
所述第二突出高度大于所述第一突出高度。
3.如权利要求2所述的半导体器件,其特征在于,
所述第二穿透电极设置在比所述第一穿透电极距所述第一半导体芯片的中央更远的距离处。
4.如权利要求2所述的半导体器件,其特征在于,
所述第二穿透电极具有宽于所述第一穿透电极的宽度。
5.如权利要求1所述的半导体器件,其特征在于,
所述第三半导体芯片的平面面积大于所述第二半导体芯片的平面面积。
6.如权利要求1所述的半导体器件,其特征在于,
还包括置于所述第二半导体芯片和所述第三半导体芯片之间的粘合材料层。
7.如权利要求1所述的半导体器件,其特征在于,
所述第一至第三半导体芯片是非易失性存储器器件、动态随机存取存储器器件以及逻辑器件中的相互不同的器件。
8.如权利要求1所述的半导体器件,其特征在于,
所述第一半导体芯片还包括第三穿透电极,其具有大于所述第二突出高度的第三突出高度。
9.如权利要求8所述的半导体器件,其特征在于,
所述第三穿透电极设置在比所述第二穿透电极距所述第一半导体芯片的中央更远的距离处。
10.如权利要求8所述的半导体器件,其特征在于,
还包括与所述第三穿透电极电连接的第四半导体芯片。
11.如权利要求10所述的半导体器件,其特征在于,
所述第四半导体芯片的平面面积大于所述第三半导体芯片的平面面积。
12.一种半导体封装件,其特征在于,包括:
配线板,其具有设置在第一面上的焊盘和设置在与所述第一面相对的第二面上的球焊盘;以及
半导体器件,其安装在所述配线板的第一面上,
其中,所述半导体器件包括:
第一半导体芯片,其包括穿透其至少一部分的第一穿透电极和第二穿透电极,第一穿透电极和第二穿透电极从所述第一半导体芯片的一个表面突出,所述第一穿透电极具有第一突出高度,所述第二穿透电极具有高于所述第一突出高度的第二突出高度;
第二半导体芯片,其与所述第一穿透电极的突出的一端电连接;以及
第三半导体芯片,其与所述第二穿透电极的突出的一端电连接,
所述第一和第二穿透电极的另一端与所述配线板的焊盘电连接,所述另一端与电连接至所述第二和第三半导体芯片的所述第一和第二穿透电极的突出的一端相对。
13.如权利要求12所述的半导体封装件,其特征在于,
还包括设置在所述配线板的球焊盘上的焊球。
14.如权利要求12所述的半导体封装件,其特征在于,
所述第一和第二穿透电极的所述一端通过连接端子与所述配线板的焊盘电连接。
15.如权利要求12所述的半导体封装件,其特征在于,
所述第一和第二穿透电极的所述一端通过焊线与所述配线板的焊盘电连接。
16.一种半导体器件的制造方法,其特征在于,包括以下步骤:
形成穿透第一半导体芯片的至少一部分的第一穿透电极和第二穿透电极,第一穿透电极和第二穿透电极从所述第一半导体芯片的一个表面突出;
将第二半导体芯片与所述第一穿透电极的突出的一端电连接;以及
将第三半导体芯片与所述第二穿透电极的突出的一端电连接,
其中,所述第一穿透电极具有第一突出高度,所述第二穿透电极具有第二突出高度,所述第二突出高度与所述第一突出高度不同。
17.如权利要求16所述的半导体器件的制造方法,其特征在于,
所述第二突出高度大于所述第一突出高度。
18.如权利要求17所述的半导体器件的制造方法,其特征在于,
所述第二穿透电极被形成在比所述第一穿透电极距所述第一半导体芯片的中央更远的距离处。
19.如权利要求16所述的半导体器件的制造方法,其特征在于,
形成穿透所述第一半导体芯片的至少一部分的第一和第二穿透电极的步骤包括:
制备具有第一面和与所述第一面相对的第二面的衬底;
形成暴露所述衬底的第一面的将要形成第一通孔的部分的第一光致抗蚀剂图案;
通过以所述第一光致抗蚀剂图案为掩模的刻蚀工艺来形成第一深度的第一通孔;
去除所述第一光致抗蚀剂图案;
形成暴露所述衬底的第一面的将要形成第二通孔的部分的第二光致抗蚀剂图案;
通过以所述第二光致抗蚀剂图案为掩模的刻蚀工艺来形成与所述第一深度不同的第二深度的第二通孔;
去除所述第二光致抗蚀剂图案;
形成分别填充所述第一和第二通孔的第一和第二穿透电极;以及
从所述衬底的第二面去除所述衬底的一部分来暴露所述第一和第二穿透电极。
20.如权利要求16所述的半导体器件的制造方法,其特征在于,
形成穿透所述第一半导体芯片的至少一部分的第一和第二穿透电极的步骤包括:
制备具有第一面和与所述第一面相对的第二面的衬底;
形成暴露所述衬底的第一面的将要形成第一和第二通孔的部分的光致抗蚀剂图案;
通过以所述光致抗蚀剂图案为掩模的刻蚀工艺来形成所述第一和第二通孔;
去除所述光致抗蚀剂图案;
形成分别填充所述第一和第二通孔的第一和第二穿透电极;以及
从所述衬底的第二面去除所述衬底的一部分来暴露所述第一和第二穿透电极,
其中,所述光致抗蚀剂图案具有暴露所述衬底的第一面的将要形成所述第一通孔的部分的第一开口和暴露所述衬底的第一面的将要形成所述第二通孔的部分的第二开口,所述第一和第二开口的宽度彼此不同。
21.如权利要求20所述的半导体器件的制造方法,其特征在于,
所述第二通孔被形成为具有宽于所述第一通孔的宽度。
22.如权利要求21所述的半导体器件的制造方法,其特征在于,
所述第二通孔被形成在比所述第一通孔距所述第一半导体芯片的中央更远的距离处。
23.如权利要求16所述的半导体器件的制造方法,其特征在于,
所述第三半导体芯片的平面面积大于所述第二半导体芯片的平面面积。
24.如权利要求16所述的半导体器件的制造方法,其特征在于,
将所述第二和第三半导体芯片分别与所述第一和第二穿透电极电连接的步骤包括:
将所述第二半导体芯片的焊垫与所述第一穿透电极电连接;
在所述第二半导体芯片的第二面上形成粘合材料层,其中所述第二半导体芯片的第二面与设置了所述焊垫的第一面相对;以及
将所述第三半导体芯片的焊垫与所述第二穿透电极电连接,
其中,所述第三半导体芯片的设置了焊垫的第一面通过所述粘合材料层与所述第二半导体芯片的第二面粘接。
25.如权利要求16所述的半导体器件的制造方法,其特征在于,
将所述第二和第三半导体芯片分别与所述第一和第二穿透电极电连接的步骤包括:
在所述第三半导体芯片的设置了焊垫的第一面上,以不覆盖所述焊垫的方式形成粘合材料层;
将所述第二半导体芯片安装在所述粘合材料层上,使得所述第二半导体芯片的与设置了焊垫的第一面相对的第二面朝向所述粘合材料层;以及
将所述第二和第三半导体芯片的焊垫同时分别与所述第一和第二穿透电极电连接,其中,在所述第三半导体芯片上安装了所述第二半导体芯片。
26.如权利要求16所述的半导体器件的制造方法,其特征在于,还包括:
形成穿透所述第一半导体芯片的第三穿透电极;以及
将第四半导体芯片与所述第三穿透电极电连接,
其中,所述第三穿透电极的突出高度大于所述第一和第二突出高度。
27.如权利要求26所述的半导体器件的制造方法,其特征在于,
所述第四半导体芯片的平面面积大于所述第三半导体芯片的平面面积。
28.如权利要求26所述的半导体器件的制造方法,其特征在于,
将所述第四半导体芯片与所述第三穿透电极电连接的步骤包括:
将所述第四半导体芯片的焊垫与所述第三穿透电极电连接,
其中,所述第四半导体芯片的设置了焊垫的第一面和所述第三半导体芯片的与设置了焊垫的第一面相对的第二面通过粘合材料层来粘接。
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