CN102456621A - Semiconductor device structure and method for manufacturing same - Google Patents
Semiconductor device structure and method for manufacturing same Download PDFInfo
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- CN102456621A CN102456621A CN2010105249667A CN201010524966A CN102456621A CN 102456621 A CN102456621 A CN 102456621A CN 2010105249667 A CN2010105249667 A CN 2010105249667A CN 201010524966 A CN201010524966 A CN 201010524966A CN 102456621 A CN102456621 A CN 102456621A
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Abstract
The invention provides a semiconductor device structure and a method for manufacturing the same, wherein the method is characterized in merging a high dielectric constant/metal gate core device and a SiON/polysilicon gate input-output device. In the sub 45 nanometers CMOS (complementary metal oxide semiconductor) technology, when the SiON/polysilicon gate technology is used for the input-output device, the high dielectric constant/metal gate is adopted for the core device. According to the method provided by the invention, the traditional SiON/polysilicon gate input-output device and the high dielectric constant/metal gate core device can be merged effectively, thus the integral performances of the semiconductor device can be improved, and the technology process can be simplified.
Description
Technical field
The present invention relates to semiconductor fabrication process, particularly semiconductor device structure and the method for making this semiconductor device structure.
Background technology
The manufacturing of integrated circuit need form a large amount of circuit elements according to the circuit layout of appointment on given chip area.Consider service speed, power consumption and cost-efficient excellent specific property, the CMOS technology is one of the most promising method that is used to make complicated circuit at present.When using the CMOS technology to make complicated integrated circuit, there are millions of transistors (for example, N channel transistor and p channel transistor) to be formed on the substrate that comprises crystalline semiconductor layer.No matter be N channel transistor or p channel transistor; MOS transistor all contains so-called PN junction, and PN junction is to be formed by following both interface: the drain/source region of high-concentration dopant and be disposed at this drain region and this source area between the counter-doping raceway groove.
Control the conductance of channel region with near the gate electrode that is formed at the channel region and separate with this channel region, for example control the current drive capability of conducting channel through thin dielectric layer.After applying suitable control voltage formation conducting channel on the gate electrode, the conductance of channel region depends on the mobility of doping content and most electric charge carriers.For the given extension of transistor width direction, the conductance of channel region depends on the distance between source area and the drain region for channel region, and this distance also is known as channel length.
Grid has the minimum physical size in the semiconductor fabrication process usually, and its width crucial critical dimension on the wafer normally, and therefore the making of grid is a critical step in the flow process in fabrication of semiconductor device.
Because that polycrystalline silicon material has is high temperature resistant, can stop that injecting the atom mixed with ion gets into advantages such as channel region; So, when making typical CMOS transistor, can use polycrystalline silicon material to make transistorized grid usually.But polysilicon gate has some shortcomings, and for example, polysilicon gate has higher resistance value, is easy to generate depletion effects and boron penetration to channel region etc.Therefore, as far as the semiconductor wafer of inferior 45 nanometers, adopt metal gates to replace conventional polysilicon gate usually.
Semiconductor device mainly is divided into I/O (I/O) device and core (core) device according to function.According to the electrical kind of device, the I/O device can be divided into I/O PMOS and I/O NMOS, just as the PMOS and the NMOS of I/O device.Likewise, core devices also comprises as the PMOS of core devices with as the NMOS of core devices.Traditional method that adopts stress memory technique at the I/O nmos device and as the core nmos device of core devices.
Intel has issued the 32nm technological process about " Gate last " high-k and metal gate, wherein forms puppet (dummy) polysilicon gate figure on the surface of oxide skin(coating).Silicon chip is being leaked/source region ion implant operation, and after The high temperature anneal subsequently, deposition interlayer dielectric layer 0 and the chemico-mechanical polishing completion, removing polysilicon gate.Then NMOS and PMOS metal gate material are deposited, and figure forms high-k and metal gate transistor.Said technology has core and input and output device, below high dielectric constant film, the high-k/metal gate of the silicon-oxygen nitride of different-thickness is arranged.
Gate last arts demand can use the different metallic material to come manufacturing grid in PMOS and NMOS pipe, uses Gate last technology, employed gate metal material during manufacturer just can free adjustment PMOS/NMOS manages.Gate last technology can make metal gates avoid the high annealing work step, the metal material that is used to make metal gates is required lower, but corresponding technology is also more complicated.
The high dielectric constant dielectric of bond grid technique generally has been used in the logic CMOS operation of inferior 45 nanometers.In technological process, high-k/metal gate has replaced traditional Si ON gate dielectric and polysilicon gate conductor.
But there are some defectives in the method for above-mentioned making semiconductor device structure: on the one hand, for NMOS and PMOS, because the demand of metal gate service behaviour is different, be different so be used for the metal alloy of these two kinds of transistor types; On the other hand, the demand major part of the input and output device that produces for each device all is identical, and for example the 2.5v input and output about 90nm, 65nm, 45nm, 32nm do not have too many variation.Therefore, the technology situation that needs the input and output device can curing as much as possible to generate in the past, suitably the adjusting process flow process makes the needs of their coupling service behaviours simultaneously, and coordinates mutually with used high dielectric constant materials.
Therefore, be necessary manufacture method to the conventional semiconductor device architecture the improve performance and the effect of semiconductor device structure, thereby improve quality of semiconductor devices, with the overall performance that improves semiconductor device and simplify technological process.
Summary of the invention
In the summary of the invention part, introduced the notion of a series of reduced forms, this will further explain in the embodiment part.Summary of the invention part of the present invention does not also mean that key feature and the essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range of attempting to confirm technical scheme required for protection.
For overall performance that semiconductor device is provided and simplify technological process; The invention provides a kind of processing method that merges high-k/metal gate core devices and SiON/ polysilicon gate input and output device; In the CMOS of inferior 45 nanometers technology; When the input and output device used silicon oxynitride SiON/ polysilicon gate process, core devices used high-k/metal gate.It is characterized in that, comprise the following steps:
A) front end device layer structure is provided; Said front end device layer structure comprises substrate; Said substrate have at least above that first device that forms and left by shallow trench isolation and with opposite polarity second device of said first device, wherein, the surface of said first device is formed with the first grid oxide layer and first polysilicon gate successively; The surface of said second device is formed with second gate oxide and second polysilicon gate successively; The both sides of the both sides of said first polysilicon gate and said second polysilicon gate by side wall around, the zone in the outside that is arranged in said side wall of said substrate is formed with the source region, on said active area, forms silicide layer;
B) form first interlayer dielectric layer on the surface of said front end device layer structure;
C) surface of said first interlayer dielectric layer of planarization to surface that exposes said first polysilicon gate and said second polysilicon gate;
D) above said second device, form the cover layer that covers said second polysilicon gate;
E) remove the said first polysilicon gate best through etching and expose said first grid oxide layer, to be formed for holding the groove of metal gates;
F) remove said cover layer;
G) in said groove, fill metal, to form metal gate structure;
H) surface of the said metal gate structure of planarization to the surface that exposes metal gates, said second polysilicon gate and the surface of said first interlayer dielectric layer;
I) form the self-aligned silicide layer on the surface of said second polysilicon gate;
J) at surface and the surface of said first interlayer dielectric layer and the surface formation etching stop layer of said self-aligned silicide layer of said metal gates, form second interlayer dielectric layer on the surface of said etching stop layer.
Further, said first device and second device are selected from nmos device and PMOS device.
Further, said metal gates is the N type metal gates utmost point or the P type metal gates utmost point.
Further, the said N type metal gates utmost point is positioned at N type trap core space or N type trap I/O area.
Further, the said P type metal gates utmost point is positioned at P type trap core space or P type trap I/O area.
Further, said metal gate structure is formed with gate dielectric layer, work function setting metal level and the grid electrode layer of high-k from bottom to top successively.
The present invention also provides a kind of semiconductor device structure, it is characterized in that, comprising:
Substrate, said substrate have at least above that first device that forms and left by shallow trench isolation and with opposite polarity second device of said first device;
The first grid oxide layer and second gate oxide, said first grid oxide layer is positioned at the surface of said first device, and said second gate oxide is formed on the surface of said second device;
Metal gates, said metal gates is formed on the surface of said first grid oxide layer;
Polysilicon gate, said polysilicon gate is positioned at the surface of said second gate oxide;
Side wall, said side wall is around said polysilicon gate and said metal gates;
Active area, said active area are formed on the zone in the outside that is arranged in said side wall of said substrate;
Silicide layer, said silicide layer is formed on the surface of said active area;
First interlayer dielectric layer, said first interlayer dielectric layer is formed on the surface of said silicide layer;
The self-aligned silicide layer, said self-aligned silicide layer is formed on the surface of said polysilicon gate;
Etching stop layer, said etching stop layer are formed on the surface of the surface of said metal gates, said first interlayer dielectric layer and the surface of said self-aligned silicide layer;
Second interlayer dielectric layer, said second interlayer dielectric layer is formed on the surface of said etching stop layer.
Further, said first device and second device are selected from nmos device and PMOS device.
Further, said metal gates is the N type metal gates utmost point or the P type metal gates utmost point.
Further, the said N type metal gates utmost point is positioned at N type trap core space or N type trap I/O area.
Further, the said P type metal gates utmost point is positioned at P type trap core space or P type trap I/O area.
Further, said metal gate structure is formed with gate dielectric layer, work function setting metal level and the grid electrode layer of high-k from bottom to top successively.
According to the invention method, can merge traditional SiON/ polysilicon gate input and output device and high-k/metal gate core devices effectively, with the raising semiconductor device overall performance and simplify technological process.
Description of drawings
Attached drawings of the present invention is used to understand the present invention at this as a part of the present invention.Embodiments of the invention and description thereof have been shown in the accompanying drawing, have been used for explaining principle of the present invention.In the accompanying drawings,
Figure 1A to Fig. 1 H shows the cross-sectional view according to the making semiconductor device structure of one embodiment of the present invention;
Fig. 2 shows the method flow diagram according to the making semiconductor device structure of one embodiment of the present invention;
Fig. 3 shows the sketch map of the semiconductor device structure of producing according to one embodiment of the present invention.
Embodiment
In the description hereinafter, a large amount of concrete details have been provided so that more thorough understanding of the invention is provided.Yet, it will be apparent to one skilled in the art that the present invention can need not one or more these details and be able to enforcement.In other example,, describe for technical characterictics more well known in the art for fear of obscuring with the present invention.
It should be noted that employed term only is in order to describe specific embodiment here, but not the intention restriction is according to exemplary embodiment of the present invention.As used herein, only if context spells out in addition, otherwise singulative also is intended to comprise plural form.In addition; It is to be further understood that; When using a technical term " comprising " and/or " comprising " in this manual; It indicates and has said characteristic, integral body, step, operation, device and/or assembly, does not exist or additional one or more other characteristics, integral body, step, operation, device, assembly and/or their combination but do not get rid of.
For the ease of describing; Here can the usage space relative terms; As " ... under ", " ... on ", " following ", " in ... top ", " top " etc., be used for describing spatial relation like a device shown in the figure or characteristic and other devices or characteristic.Should be understood that the space relative terms is intended to comprise the different azimuth in using or operating the orientation of being described in the drawings except device.For example, if the device in the accompanying drawing is squeezed, then be described as to be positioned as " above other devices or characteristic " or " on other devices or characteristic " after the device of " in other devices or beneath " or " under other devices or characteristic ".Thereby exemplary term " in ... below " can comprise " in ... top " and " in ... below " two kinds of orientation.This device also can other different modes location (revolve turn 90 degrees or be in other orientation), and employed space relative descriptors is here made respective explanations.
Now, will describe in more detail according to exemplary embodiment of the present invention with reference to accompanying drawing.Yet these exemplary embodiments can multiple different form be implemented, and should not be interpreted as the embodiment that is only limited to here to be set forth.Should be understood that, provide these embodiment of the present inventionly to disclose thoroughly and complete, and the design of these exemplary embodiments fully conveyed to those of ordinary skills in order to make.In the accompanying drawings, for the sake of clarity, exaggerated the thickness in layer and zone, and used the identical Reference numeral to represent identical device, thereby will omit description of them.
In order thoroughly to understand the present invention, will in following description, detailed steps be proposed, so that how explanation the present invention merges high-k/metal gate core devices and SiON/ polysilicon gate input and output device.Obviously, execution of the present invention is not limited to the specific details that the technical staff had the knack of of semiconductor applications.Preferred embodiment of the present invention is described in detail as follows, yet except these were described in detail, the present invention can also have other execution modes.Input and output device involved in the present invention comprises the device of 1.5V, 1.8V, 2.5V, 3.3V and 5V.
Specify method step below in conjunction with Figure 1A to Fig. 1 H and Fig. 2 according to the making semiconductor device structure of one embodiment of the present invention.Figure 1A to Fig. 1 H is depicted as the cross-sectional view according to the making semiconductor device structure of one embodiment of the present invention.
At first, shown in Figure 1A, front end device layer structure is provided.
Under normal conditions, front end device layer structure comprises formed device architecture layer in the preorder technology.
As an example, front end device layer structure comprises substrate 101, said substrate 101 have at least above that first device 103 that forms and isolated by shallow trench 102 and with first device, 103 opposite polarity second devices 104.Wherein, The surface of said first device 103 is formed with the first grid oxide layer 105a and the first polysilicon gate 106a successively; The surface of said second device 104 is formed with the second gate oxide 105b and the second polysilicon gate 106b successively; The both sides of the both sides of the said first polysilicon gate 106a and the said second polysilicon gate 106b by side wall 107 around, the zone in the outside that is arranged in said side wall 107 of substrate 101 is formed with source region 108.Wherein, first device 103 can be nmos device, also can be the PMOS device.And, on said active area 108, form silicide layer 109, wherein block polysilicon by hard mask.
Further, the material that constitutes substrate 101 can be unadulterated monocrystalline silicon, be doped with the monocrystalline silicon or the silicon on the dielectric substrate (SOI) of impurity, can also comprise other material, for example indium antimonide, lead telluride, indium arsenide, GaAs or gallium antimonide etc.
Should be noted in the discussion above that front end device layer structure as herein described is not to be restrictive, but can also have other structures.For example, the surface of substrate 101 can also have the groove (not shown) that is formed with germanium silicon stressor layers; Active area can also be formed has lightly doped drain (LDD) structure; The surface of the first polysilicon gate 106a and the second polysilicon gate 106b can also have mask layer etc. respectively.
The second, shown in Figure 1B, form first interlayer dielectric layer 110 on the surface of the first polysilicon gate 106a, the surface of the second polysilicon gate 106b, the surface of side wall 107 and the surface of silicide layer 109; Then, planarization first interlayer dielectric layer 110 is to the surface of the surface that exposes the first polysilicon gate 106a and the second polysilicon gate 106b.
As an example, adopt cmp (CMP) method that first interlayer dielectric layer 110 is carried out planarization.
Under preferred situation, just first interlayer dielectric layer 110 is planarized to the top surface of the first polysilicon gate 106a and the second polysilicon gate 106b.But; Should be noted that; Because the size of semiconductor transistor is more and more littler, be difficult to and there is no need too accurately to confirm the particular location after the planarization, therefore; Can first interlayer dielectric layer 110 be planarized to below the top surface of the first polysilicon gate 106a and the second polysilicon gate 106b, this is conspicuous to those skilled in the art.
The 3rd, shown in Fig. 1 C, above second device 104, form the cover layer 111 that covers the second polysilicon gate 106b.
As an example, above second device 104, apply photoresist layer, and make public and technology such as development so that photoresist layer covers second device, 104 districts, and expose first device, 103 districts.
The 4th, shown in Fig. 1 D, remove the first polysilicon gate 106a to exposing first grid oxide layer 105a, to be formed for holding the groove 112 of metal gates through etching; Then, remove cover layer 111.
As an example, adopt dry etch process to remove the first polysilicon gate 106a.
It should be noted; For the ease of understanding accompanying drawing and making accompanying drawing can more clearly express different layer structures, no longer mark the Reference numeral of substrate 101, shallow trench 102, first grid oxide layer 105a, the second gate oxide 105b, the first polysilicon gate 106a, the second polysilicon gate 106b, side wall 107, active area 108 and silicide layer 109 among following Fig. 1 E.
The 5th, shown in Fig. 1 E, in groove 112, fill metal 113, to form metal gate structure.
As an example, the metal 113 of filling can be followed successively by gate dielectric layer 113a, work function setting metal level 113b and the grid electrode layer 113c of high-k (k) from bottom to top.
Further; For N type metal gates electrode structure; The metal that its work function is set metal level 113b is the metal that is applicable to nmos device, and material can comprise such as titanium, tantalum, aluminium, zirconium, hafnium and alloy thereof, for example comprises the metal carbides, nitride of these elements etc.The method that forms this N type work function setting metal level can be PVD (physical vapour deposition (PVD)) or CVD (chemical vapour deposition (CVD)) method.
Under preferred situation, the work function of N type metal gates electrode structure is set metal level 113b and is followed successively by tantalum, titanium nitride layer and calorize titanium layer from bottom to top; Perhaps be tantalum nitride layer, titanium nitride layer and calorize titanium layer.
Again further; For P type metal gates electrode structure; The metal that its work function is set metal level 113b is the metal that is applicable to the PMOS device, and material can comprise such as ruthenium, palladium, platinum and metal nitride, for example the nitride of titanium, tungsten, tantalum, ruthenium and titanium aluminium.The method that forms this P type work function setting metal level can be PVD (physical vapour deposition (PVD)) or CVD (chemical vapour deposition (CVD)) method.
Under preferred situation, the work function of P type metal gates electrode structure is set metal level 113b and is followed successively by titanium nitride layer, tantalum and calorize titanium layer from bottom to top; Perhaps be titanium nitride layer, tantalum nitride layer and calorize titanium layer.
Further, the material of grid electrode layer 113c is an aluminum or aluminum alloy.Under preferred situation, grid electrode layer 113c is followed successively by titanium aluminide and aluminium from bottom to top.
The 6th, shown in Fig. 1 F, the surface of planarization material grid structure to the surface that exposes metal gates 114, the second polysilicon gate 106b and the surface of first interlayer dielectric layer 110.
As an example, adopt cmp (CMP) method that metal gate structure is carried out planarization.
Under preferred situation, just metal gate structure is planarized to the top surface of groove 112.But; Should be noted that; Because the size of semiconductor transistor is more and more littler, be difficult to and there is no need too accurately to confirm the particular location after the planarization, therefore; Can metal gate structure be planarized to below the top surface of groove 112, this is conspicuous to those skilled in the art.
As an example, metal gates 114 can be the N type metal gates utmost point, also can be the P type metal gates utmost point.Wherein, the N type metal gates extremely can be positioned at N type trap core space or N type trap I/O area; The P type metal gates extremely can be positioned at P type trap core space or P type trap I/O area.Further, the metal of the N type metal gates utmost point is the metal that work function is applicable to nmos device, and the metal of the P type metal gates utmost point is the metal that work function is applicable to the PMOS device.
The 7th, shown in Fig. 1 G, form self-aligned silicide layer 115 on the surface of the second polysilicon gate 106b.
As an example, at the surface deposition of the second polysilicon gate 106b material of metallic nickel or platinum nickel for example, with final formation self-aligned silicide layer 115.
At last, shown in Fig. 1 H, form etching stop layer 116, form second interlayer dielectric layer 117 on the surface of etching stop layer 116 on the surface of metal gates 114, the surface of first interlayer dielectric layer 110 and the surface of self-aligned silicide layer 115.
According to embodiment of the present invention, in the CMOS of inferior 45 nanometers technology, when the input and output device used silicon oxynitride SiON/ polysilicon gate process, core devices used high-k/metal gate.
In sum; The method of making semiconductor device structure of the present invention just forms the self-aligned silicide layer after metal gates forms; Remove in the technology at the core devices polysilicon gate; Increase one or more mask layer and protect the input and output polysilicon gate, the situation that does not therefore exist high temperature that the performance of self-aligned silicide layer is exerted an influence, thus guaranteed the performance of device; Second; In the high-k/metal gate process flow process of routine, have independent silicide for the input and output polysilicon gate and form technology, the method for making semiconductor device structure of the present invention; Make full use of existing equipment, material and technology; Can not increase the complexity of production line, and manufacture method is simple, need expend extra man power and material; The 3rd, the self-aligned silicide layer of semiconductor device structure of the present invention has preferable performance higher resistance can not occur; Thereby improve the overall performance of semiconductor device and simplify technological process.
As shown in Figure 2, be method flow diagram according to the making semiconductor device structure of one embodiment of the present invention.
In step 201, front end device layer structure is provided.
Under normal conditions, front end device layer structure comprises formed device architecture layer in the preorder technology.
As an example, front end device layer structure comprises substrate, said substrate have at least above that first device that forms and left by shallow trench isolation and with opposite polarity second device of said first device.Wherein, The surface of said first device is formed with the first grid oxide layer and first polysilicon gate successively; The surface of said second device is formed with second gate oxide and second polysilicon gate successively, the both sides of the both sides of said first polysilicon gate and said second polysilicon gate by side wall around, the zone that substrate is arranged in the outside of said side wall is formed with the source region; On said active area, form silicide layer, wherein block polysilicon by hard mask.First device and second device are selected from nmos device and PMOS device.
Further, the material that constitutes substrate can be unadulterated monocrystalline silicon, be doped with the monocrystalline silicon or the silicon-on-insulator (SOI) of impurity, can also comprise other material, for example indium antimonide, lead telluride, indium arsenide, GaAs or gallium antimonide etc.
In addition, should be noted that front end device layer structure as herein described is not to be restrictive, but can also have other structures.For example, the surface of substrate can also have the groove (not shown) that is formed with germanium silicon stressor layers; Active area can also be formed has lightly doped drain (LDD) structure; The surface of first polysilicon gate and second polysilicon gate can also have mask layer respectively; Deng.
In step 202, form first interlayer dielectric layer on the surface of first polysilicon gate, the surface of second polysilicon gate, the surface of side wall and the surface of silicide layer; Then, the surface of planarization first interlayer dielectric layer to the surface that exposes first polysilicon gate and second polysilicon gate.
As an example, adopt cmp (CMP) method that first interlayer dielectric layer is carried out planarization.
Under preferred situation, just with the top surface of first interlayer dielectric layer flatening to first polysilicon gate and second polysilicon gate.But; Should be noted that; Because the size of semiconductor transistor is more and more littler, be difficult to and there is no need too accurately to confirm the particular location after the planarization, therefore; Can be below the top surface of first polysilicon gate and second polysilicon gate with first interlayer dielectric layer flatening, this is conspicuous to those skilled in the art.
In step 203, above second device, form the cover layer that covers second polysilicon gate.
As an example, above second device, apply photoresist layer, and make public and technology such as development so that photoresist layer covers second device region, and expose first device region.
In step 204, remove the first polysilicon gate best through etching and expose first grid oxide layer, to be formed for holding the groove of metal gates; Then, remove cover layer.
As an example, adopt dry etch process to remove first polysilicon gate.
In step 205, in groove, fill metal, to form metal gate structure;
As an example, the metal of filling can be followed successively by gate dielectric layer, work function setting metal level and the grid electrode layer of high-k (k) from bottom to top.
Further; For N type metal gates electrode structure; The metal that its work function is set metal level is the metal that is applicable to nmos device, and material can comprise such as titanium, tantalum, aluminium, zirconium, hafnium and alloy thereof, for example comprises the metal carbides, nitride of these elements etc.The method that forms this N type work function setting metal level can be PVD (physical vapour deposition (PVD)) or CVD (chemical vapour deposition (CVD)) method.
Under preferred situation, the work function of N type metal gates electrode structure is set metal level and is followed successively by tantalum, titanium nitride layer and calorize titanium layer from bottom to top; Perhaps be tantalum nitride layer, titanium nitride layer and calorize titanium layer.
Again further, for P type metal gates electrode structure, the metal that its work function is set metal level is the metal that is applicable to the PMOS device, and material can comprise such as ruthenium, palladium, platinum and metal nitride, for example the nitride of titanium, tungsten, tantalum, ruthenium and titanium aluminium.The method that forms this P type work function setting metal level can be PVD (physical vapour deposition (PVD)) or CVD (chemical vapour deposition (CVD)) method.
Under preferred situation, the work function of P type metal gates electrode structure is set metal level and is followed successively by titanium nitride layer, tantalum and calorize titanium layer from bottom to top; Perhaps be titanium nitride layer, tantalum nitride layer and calorize titanium layer.
Further, the material of grid electrode layer is an aluminum or aluminum alloy.Under preferred situation, grid electrode layer is followed successively by titanium aluminide and aluminium from bottom to top.
In step 206, the surface of planarization material grid structure to the surface that exposes metal gates, second polysilicon gate and the surface of first interlayer dielectric layer.
As an example, adopt cmp (CMP) method that metal gate structure is carried out planarization.
Under preferred situation, just metal gate structure is planarized to the top surface of groove.
As an example, metal gates can be the N type metal gates utmost point, also can be the P type metal gates utmost point.Wherein, the N type metal gates extremely can be positioned at N type trap core space or N type trap I/O area; The P type metal gates extremely can be positioned at P type trap core space or P type trap I/O area.Further, the metal of the N type metal gates utmost point is the metal that work function is applicable to nmos device, and the metal of the P type metal gates utmost point is the metal that work function is applicable to the PMOS device.
In step 207, form the self-aligned silicide layer on the surface of second polysilicon gate.
As an example, at the surface deposition of second polysilicon gate material of metallic nickel or platinum nickel for example, with final formation self-aligned silicide layer.
In step 208, form etching stop layer on the surface of metal gates, the surface of first interlayer dielectric layer and the surface of self-aligned silicide layer, form second interlayer dielectric layer on the surface of etching stop layer.
As shown in Figure 3, be the sketch map of the semiconductor device structure produced according to one embodiment of the present invention.As shown in the figure, semiconductor device structure comprises substrate 301, at least one first device 303 and at least one second device 304.More specifically, said substrate 301 have at least above that first device 303 that forms and isolated by shallow trench 302 and with said first device, 303 opposite polarity second devices 304.Wherein, first device 303 can be nmos device, also can be the PMOS device.
Further, first device 303 has:
First grid oxide layer 305a, first grid oxide layer 305a is formed on the surface of first device 303 of substrate 301;
The first interlayer dielectric layer 310a, the first interlayer dielectric layer 310a is formed on the surface of silicide layer 309 a;
Second interlayer dielectric layer, 313, the second interlayer dielectric layers 313 are formed on the surface of etching stop layer 312.
Further, second device 304 has:
The second gate oxide 305b, the second gate oxide 305b is formed on the surface of second device 304 of substrate 301;
The first interlayer dielectric layer 310b, the first interlayer dielectric layer 310b is formed on the surface of silicide layer 309 b;
Self-aligned silicide layer 311, self-aligned silicide layer 311 is formed on the surface of polysilicon gate 306b;
Second interlayer dielectric layer, 313, the second interlayer dielectric layers 313 are formed on the surface of etching stop layer 312.
Further, according to the demand of different process, metal gates 306a can be the N type metal gates utmost point, also can be the P type metal gates utmost point; Wherein, N type metal gates utmost point 306a can be positioned at N type trap core space or N type trap I/O area, and P type metal gates utmost point 306a can be positioned at P type trap core space or P type trap I/O area; Polysilicon gate 306b can be formed on N type trap core space or N type trap I/O area.
Further, according to the difference of metal gates polarity, the N type metal gates has the work function of the metal that is applicable to nmos device and sets metal level; The P type metal gates has the work function of the metal that is applicable to the PMOS device and sets metal level.
As an example, for N type metal gates electrode structure, the material that its work function is set metal level can comprise titanium, tantalum, aluminium, zirconium, hafnium and alloy thereof, for example comprises the metal carbides, nitride of these elements etc.
Under preferred situation, the work function of N type metal gates electrode structure is set metal level and is followed successively by tantalum, titanium nitride layer and calorize titanium layer from bottom to top; Perhaps be tantalum nitride layer, titanium nitride layer and calorize titanium layer.
As an example, for P type metal gates electrode structure, its work function is set metal level can comprise ruthenium, palladium, platinum and metal nitride, for example the nitride of titanium, tungsten, tantalum, ruthenium and titanium aluminium.
Under preferred situation, the work function of P type metal gates electrode structure is set metal level and is followed successively by titanium nitride layer, tantalum and calorize titanium layer from bottom to top; Perhaps be titanium nitride layer, tantalum nitride layer and calorize titanium layer.
Semiconductor device according to aforesaid embodiment manufacturing can be applicable in the multiple integrated circuit (IC).According to integrated circuit of the present invention for example is memory circuitry, like random-access memory (ram), dynamic ram (DRAM), synchronous dram (SDRAM), static RAM (SRAM) (SRAM) or read-only memory (ROM) or the like.According to IC of the present invention can also be logical device, like programmable logic array (PLA), application-specific integrated circuit (ASIC) (ASIC), combination type DRAM logical integrated circuit (buried type DRAM) or other circuit devcies arbitrarily.IC chip according to the present invention can be used for for example consumer electronic products; In various electronic products such as personal computer, portable computer, game machine, cellular phone, personal digital assistant, video camera, digital camera, mobile phone, especially in the radio frequency products.
The present invention is illustrated through the foregoing description, but should be understood that, the foregoing description just is used for for example and illustrative purposes, but not is intended to the present invention is limited in the described scope of embodiments.It will be appreciated by persons skilled in the art that in addition the present invention is not limited to the foregoing description, can also make more kinds of variants and modifications according to instruction of the present invention, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by appended claims book and equivalent scope thereof.
Claims (14)
1. a method of making semiconductor device structure is characterized in that, comprises the following steps:
A) front end device layer structure is provided; Said front end device layer structure comprises substrate; Said substrate have at least above that first device that forms and left by shallow trench isolation and with opposite polarity second device of said first device, wherein, the surface of said first device is formed with the first grid oxide layer and first polysilicon gate successively; The surface of said second device is formed with second gate oxide and second polysilicon gate successively; The both sides of the both sides of said first polysilicon gate and said second polysilicon gate by side wall around, the zone in the outside that is arranged in said side wall of said substrate is formed with the source region, on said active area, forms silicide layer;
B) form first interlayer dielectric layer on the surface of said front end device layer structure;
C) surface of said first interlayer dielectric layer of planarization to surface that exposes said first polysilicon gate and said second polysilicon gate;
D) above said second device, form the cover layer that covers said second polysilicon gate;
E) remove the said first polysilicon gate best through etching and expose said first grid oxide layer, to be formed for holding the groove of metal gates;
F) remove said cover layer;
G) in said groove, fill metal, to form metal gate structure;
H) surface of the said metal gate structure of planarization to the surface that exposes metal gates, said second polysilicon gate and the surface of said first interlayer dielectric layer;
I) form the self-aligned silicide layer on the surface of said second polysilicon gate;
J) at surface and the surface of said first interlayer dielectric layer and the surface formation etching stop layer of said self-aligned silicide layer of said metal gates, form second interlayer dielectric layer on the surface of said etching stop layer.
2. method according to claim 1 is characterized in that, said first device and second device are selected from nmos device and PMOS device.
3. method according to claim 1 is characterized in that, said metal gates is the N type metal gates utmost point or the P type metal gates utmost point.
4. method according to claim 3 is characterized in that, the said N type metal gates utmost point is positioned at N type trap core space or N type trap I/O area.
5. method according to claim 3 is characterized in that, the said P type metal gates utmost point is positioned at P type trap core space or P type trap I/O area.
6. method according to claim 1 is characterized in that, said metal gate structure is formed with gate dielectric layer, the work function of high-k from bottom to top successively and sets metal level and grid electrode layer.
7. the semiconductor device structure processed of a utilization such as each described method of claim 1 ~ 6 is characterized in that, comprising:
Substrate, said substrate have at least above that first device that forms and left by shallow trench isolation and with opposite polarity second device of said first device;
The first grid oxide layer and second gate oxide, said first grid oxide layer is positioned at the surface of said first device, and said second gate oxide is formed on the surface of said second device;
Metal gates, said metal gates is formed on the surface of said first grid oxide layer;
Polysilicon gate, said polysilicon gate is positioned at the surface of said second gate oxide;
Side wall, said side wall is around said polysilicon gate and said metal gates;
Active area, said active area are formed on the zone in the outside that is arranged in said side wall of said substrate;
Silicide layer, said silicide layer is formed on the surface of said active area;
First interlayer dielectric layer, said first interlayer dielectric layer is formed on the surface of said silicide layer;
The self-aligned silicide layer, said self-aligned silicide layer is formed on the surface of said polysilicon gate;
Etching stop layer, said etching stop layer are formed on the surface of the surface of said metal gates, said first interlayer dielectric layer and the surface of said self-aligned silicide layer;
Second interlayer dielectric layer, said second interlayer dielectric layer is formed on the surface of said etching stop layer.
8. method according to claim 7 is characterized in that, said first device and second device are selected from nmos device and PMOS device.
9. method according to claim 7 is characterized in that, said metal gates is the N type metal gates utmost point or the P type metal gates utmost point.
10. method according to claim 9 is characterized in that, the said N type metal gates utmost point is positioned at N type trap core space or N type trap I/O area.
11. method according to claim 9 is characterized in that, the said P type metal gates utmost point is positioned at P type trap core space or P type trap I/O area.
12. method according to claim 7 is characterized in that, said metal gate structure is formed with gate dielectric layer, the work function of high-k from bottom to top successively and sets metal level and grid electrode layer.
13. an integrated circuit that comprises through the semiconductor device of making like claim 1 or 7 described methods, wherein said integrated circuit is selected from random access memory, dynamic random access memory, Synchronous Dynamic Random Access Memory, static RAM, read-only memory, programmable logic array, application-specific integrated circuit (ASIC), buried type dynamic random access memory and radio circuit.
14. an electronic equipment that comprises through the semiconductor device of making like claim 1 or 7 described methods, wherein said electronic equipment is selected from personal computer, portable computer, game machine, cellular phone, personal digital assistant, video camera, digital camera and mobile phone.
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