CN102447455A - Reset signal discharge circuit - Google Patents
Reset signal discharge circuit Download PDFInfo
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- CN102447455A CN102447455A CN2010102990455A CN201010299045A CN102447455A CN 102447455 A CN102447455 A CN 102447455A CN 2010102990455 A CN2010102990455 A CN 2010102990455A CN 201010299045 A CN201010299045 A CN 201010299045A CN 102447455 A CN102447455 A CN 102447455A
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- voltage signal
- reset signal
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- resistance
- switch
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Abstract
The invention provides a reset signal discharge circuit, which is used for discharging a reset signal during the pull-down process of the reset signal. The reset signal discharge circuit comprises a voltage division circuit, a discharge circuit, a delay circuit and a switching circuit, wherein, the voltage division circuit receives a first voltage signal and then outputs a second voltage signal after voltage reduction on the first voltage signal; the delay circuit is charged by virtue of the second voltage signal, and then the second voltage signal is output to the switching circuit after the delay circuit is fully charged; the switching circuit receives the second voltage signal and outputs the reset signal according to the second voltage signal; and the discharge circuit accelerates the speed of discharging the delay circuit during the process that the first voltage signal is changed from a high potential to a low potential so that the reset signal is pulled down before the first voltage signal is pulled down.
Description
Technical field
The present invention relates to a kind of discharge circuit, be meant a kind of normal reset signal discharge circuit of computer system sequential that guarantees especially.
Background technology
Signal sequence standard according to the computer operation; RSMRST (restart normally and reset) signal owing to receive+control of 3.3V_AUX (+3.3V boost voltage) signal; Should compare the fall time of RSMRST signal+fall time of 3.3V_AUX signal is short, and promptly the RSMRST signal should be pulled low to electronegative potential prior to+3.3V_AUX signal.Usually adopt resistance and electric capacity to constitute the RC filter circuit in traditional RSMRST circuit with the noise jamming in the filtered signal.Yet, therefore cause the RSMRST signal in discharge process, also to have time-delay because electric capacity belongs to the effect that energy-storage travelling wave tube has the charging time-delay.Finally possibly cause the sequential of RSMRST signal to lag behind+the 3.3V_AUX signal, promptly+the 3.3V_AUX signal is pulled low to electronegative potential prior to the RSMRST signal, do not meet the signal sequence standard.Consequent sequential disorder causes computer system unstable unusual with start easily.
Summary of the invention
In view of above content, be necessary to provide a kind of normal reset signal discharge circuit of computer system sequential that guarantees.
A kind of reset signal discharge circuit; In order to drag down in the process this reset signal is discharged in reset signal; Comprise a bleeder circuit, a discharge circuit, a delay circuit and a switching circuit, said bleeder circuit receives one first voltage signal, and with output one second voltage signal after this first voltage signal step-down; Said second voltage signal charges to delay circuit; And after said delay circuit is full of electricity, second voltage signal is exported to said switching circuit, said switching circuit receives second voltage signal, and according to this second voltage signal output reset signal; Said discharge circuit is become the discharge process of accelerating in the process of electronegative potential said delay circuit at first voltage signal by high potential, make said reset signal before first voltage signal, dragged down.
Compared to prior art; Reset signal discharge circuit of the present invention carries out discharge process through delay circuit to the switching circuit that is full of behind the electricity; Make reset signal before first voltage signal, dragged down when changeing low, guaranteed that the sequential of the reset signal and first voltage signal is normal by height.
Description of drawings
Fig. 1 is the block diagram of reset signal discharge circuit of the present invention.
Fig. 2 is the circuit diagram of reset signal discharge circuit of the present invention.
The main element symbol description
Switching circuit 400
The first switch T1
Second switch T2
Diode D
Capacitor C
First resistance R 1
Second resistance R 2
The 3rd resistance R 3
The 4th resistance R 4
Embodiment
See also Fig. 1, reset signal discharge circuit of the present invention discharges to this reset signal in order to drag down in the process in reset signal, comprises a bleeder circuit 100, a discharge circuit 200, a delay circuit 300 and a switching circuit 400.Said bleeder circuit 100 receives one first voltage signal, and with output one second voltage signal after this first voltage signal step-down.Said second voltage signal charges to delay circuit 300, and after said delay circuit 300 is full of electricity, second voltage signal is exported to said switching circuit 400.Said switching circuit 400 receives second voltage signal, and according to this second voltage signal output reset signal.Said discharge circuit 200 is become the discharge process of accelerating in the process of electronegative potential said delay circuit 300 at first voltage signal by high potential, make said reset signal before first voltage signal, dragged down.
See also Fig. 2, said bleeder circuit 100 comprises one first resistance R 1 and one second resistance R 2.Said first resistance R, 1 one terminations are received first voltage signal, and said first resistance R, 1 other end is via second resistance R, 2 ground connection, and the connected node between said first resistance R 1 and second resistance R 2 is exported said second voltage signal.Said discharge circuit 200 comprises a diode D.The anode of said diode D electrically connects the connected node between said first resistance R 1 and second resistance R 2, and the negative electrode of said diode D receives said first voltage signal.Said delay circuit 300 comprises a capacitor C, and the connected node between said first resistance R 1 and second resistance R 2 is via said capacitor C ground connection.
Said switching circuit 400 comprises one first switch T1, a second switch T2, one the 3rd resistance R 3 and one the 4th resistance R 4.Each switch T1, T2 comprise one first end, one second end and one the 3rd end.First termination of the said first switch T1 is received said second voltage signal.The second end ground connection of the said first switch T1.The 3rd end of the said first switch T1 electrically connects first end of said second switch T2.The 3rd end of the said first switch T1 also receives a tertiary voltage signal via said the 3rd resistance R 3.The second end ground connection of said second switch T2.The 3rd end of said second switch T2 is exported said reset signal.The 3rd end of said second switch T2 also receives first voltage signal via said the 4th resistance R 4.Wherein, said first switch and second switch T1, T2 are NPN type triode, and said first end, second end and the 3rd end are respectively base stage, emitter and collector.Wherein, said first voltage signal is+3.3V boost voltage signal that said second voltage signal is+5V boost voltage signal.
When said bleeder circuit 100 received first voltage signal of high potential, this first voltage signal converted one second voltage signal into after said bleeder circuit 100 step-downs.This second voltage signal gives the capacitor C charging of said delay circuit 300 until the said first switch T1 conducting, and this moment, said second switch T2 ended, the reset signal of the 3rd end output high potential of said second switch T2.
When said bleeder circuit 100 received first voltage signal of electronegative potential, the capacitor C of storage Full Charge Capacity was reduced to electronegative potential through said diode D repid discharge by high potential.This moment, the said first switch T1 ended, second switch T2 conducting, the reset signal of the 3rd end output electronegative potential of said second switch T2.In this first voltage signal process low by the height commentaries on classics, said capacitor C makes said reset signal before first voltage signal, to be dragged down through diode D repid discharge.
Respectively said first voltage signal and reset signal are measured through an oscilloscope, when not using reset signal discharge circuit of the present invention, time ratio first voltage signal that said reset signal is pulled low to 0.8V is pulled low to time-lag 560 microseconds of 2.1V.And after using reset signal discharge circuit of the present invention, the time that time ratio first voltage signal that said reset signal is pulled low to 0.8V is pulled low to 2.1V is 480 microseconds in advance, meet the timing sequence specification of Intel for first voltage signal and reset signal.
Reset signal discharge circuit of the present invention carries out discharge process through the switching circuit 400 that 300 pairs of delay circuits are full of behind the electricity; Make reset signal before first voltage signal, dragged down when changeing low, guaranteed that the sequential of the reset signal and first voltage signal is normal by height.
Claims (8)
1. reset signal discharge circuit; In order to drag down in the process this reset signal is discharged in reset signal; It is characterized in that: said reset signal discharge circuit comprises a bleeder circuit, a discharge circuit, a delay circuit and a switching circuit; Said bleeder circuit receives one first voltage signal; And with output one second voltage signal after this first voltage signal step-down, said second voltage signal charges to delay circuit, and after said delay circuit is full of electricity, second voltage signal is exported to said switching circuit; Said switching circuit receives second voltage signal; And according to this second voltage signal output reset signal, said discharge circuit is accelerated the discharge process to said delay circuit in first voltage signal is become the process of electronegative potential by high potential, make said reset signal before first voltage signal, dragged down.
2. reset signal discharge circuit as claimed in claim 1; It is characterized in that: said bleeder circuit comprises one first resistance and one second resistance; Said first resistance, one termination is received first voltage signal; The said first resistance other end is via second grounding through resistance, and the connected node between said first resistance and second resistance is exported said second voltage signal.
3. reset signal discharge circuit as claimed in claim 2 is characterized in that: said delay circuit comprises an electric capacity, and the connected node between said first resistance and second resistance is via said capacity earth.
4. reset signal discharge circuit as claimed in claim 3; It is characterized in that: said switching circuit comprises one first switch, a second switch, one the 3rd resistance and one the 4th resistance; Each switch comprises one first end, one second end and one the 3rd end; First termination of said first switch is received said second voltage signal, the second end ground connection of said first switch, and the 3rd end of said first switch electrically connects first end of said second switch; The 3rd end of said first switch also receives a tertiary voltage signal via said the 3rd resistance; The second end ground connection of said second switch, the 3rd end of said second switch is exported said reset signal, and the 3rd end of said second switch also receives first voltage signal via said the 4th resistance.
5. reset signal discharge circuit as claimed in claim 4 is characterized in that: said first switch and second switch are NPN type triode, and said first end, second end and the 3rd end are respectively base stage, emitter and collector.
6. reset signal discharge circuit as claimed in claim 4; It is characterized in that: said discharge circuit comprises a diode; The anode of said diode electrically connects the connected node between said first resistance and second resistance, and the negative electrode of said diode receives said first voltage signal.
7. reset signal discharge circuit as claimed in claim 6 is characterized in that: when said bleeder circuit receives first voltage signal of high potential, and the reset signal of the 3rd end of said second switch output high potential.
8. reset signal discharge circuit as claimed in claim 6 is characterized in that: when said bleeder circuit receives first voltage signal of electronegative potential, and the reset signal of the 3rd end of said second switch output electronegative potential.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010102990455A CN102447455A (en) | 2010-10-07 | 2010-10-07 | Reset signal discharge circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010102990455A CN102447455A (en) | 2010-10-07 | 2010-10-07 | Reset signal discharge circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102447455A true CN102447455A (en) | 2012-05-09 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010102990455A Pending CN102447455A (en) | 2010-10-07 | 2010-10-07 | Reset signal discharge circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102447455A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104199752A (en) * | 2014-08-29 | 2014-12-10 | 迈普通信技术股份有限公司 | Failure recovery circuit and device |
| CN104539274A (en) * | 2014-12-31 | 2015-04-22 | 广东志高空调有限公司 | Reset circuit and WiFi communication system |
| CN110350898A (en) * | 2019-07-16 | 2019-10-18 | 常州欣盛半导体技术股份有限公司 | A kind of carrier band chip start and close reset circuit and its working method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5357222A (en) * | 1991-10-09 | 1994-10-18 | Nokia Mobile Phones Ltd. | Voltage controlled component including a capacitive diode biased to operate in the linear region |
| US20060044028A1 (en) * | 2004-08-25 | 2006-03-02 | Dipankar Bhattacharya | Programmable reset signal that is independent of supply voltage ramp rate |
| US20090174443A1 (en) * | 2008-01-03 | 2009-07-09 | Universal Scientific Industrial Co., Ltd. | Hard reset and manual reset circuit assembly |
| CN101751099A (en) * | 2008-12-18 | 2010-06-23 | 鸿富锦精密工业（深圳）有限公司 | Signal generation circuit |
-
2010
- 2010-10-07 CN CN2010102990455A patent/CN102447455A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5357222A (en) * | 1991-10-09 | 1994-10-18 | Nokia Mobile Phones Ltd. | Voltage controlled component including a capacitive diode biased to operate in the linear region |
| US20060044028A1 (en) * | 2004-08-25 | 2006-03-02 | Dipankar Bhattacharya | Programmable reset signal that is independent of supply voltage ramp rate |
| US20090174443A1 (en) * | 2008-01-03 | 2009-07-09 | Universal Scientific Industrial Co., Ltd. | Hard reset and manual reset circuit assembly |
| CN101751099A (en) * | 2008-12-18 | 2010-06-23 | 鸿富锦精密工业（深圳）有限公司 | Signal generation circuit |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104199752A (en) * | 2014-08-29 | 2014-12-10 | 迈普通信技术股份有限公司 | Failure recovery circuit and device |
| CN104199752B (en) * | 2014-08-29 | 2017-04-26 | 迈普通信技术股份有限公司 | Failure recovery circuit and device |
| CN104539274A (en) * | 2014-12-31 | 2015-04-22 | 广东志高空调有限公司 | Reset circuit and WiFi communication system |
| CN104539274B (en) * | 2014-12-31 | 2017-12-05 | 广东志高空调有限公司 | A kind of reset circuit and WiFi communication system |
| CN110350898A (en) * | 2019-07-16 | 2019-10-18 | 常州欣盛半导体技术股份有限公司 | A kind of carrier band chip start and close reset circuit and its working method |
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| PB01 | Publication | ||
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| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20120509 |