CN102447062A - Transistor structure - Google Patents
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- CN102447062A CN102447062A CN2010105181113A CN201010518111A CN102447062A CN 102447062 A CN102447062 A CN 102447062A CN 2010105181113 A CN2010105181113 A CN 2010105181113A CN 201010518111 A CN201010518111 A CN 201010518111A CN 102447062 A CN102447062 A CN 102447062A
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Abstract
The invention relates to a transistor structure which comprises a patterning N-type transparent oxide semiconductor layer and a patterning P-type organic high molecular semiconductor layer. The patterning N-type transparent oxide semiconductor layer is formed on a baseplate to serve as a base electrode. The patterning P-type organic high molecular semiconductor layer is formed on the patterning N-type transparent oxide semiconductor layer and comprises a first part and a second part so that the patterning N-type transparent oxide semiconductor layer respectively forms heterojunction interfaces with the first part and the second part of the patterning P-type organic high molecular semiconductor layer, wherein the first part of the patterning P-type organic high molecular semiconductor layer serves as an emitting electrode, and the second part of the patterning P-type organic high molecular semiconductor layer serves as a collecting electrode.
Description
Technical field
The invention relates to a kind of transistor arrangement, and particularly about a kind of employing transparent oxide semiconductor and the semi-conductive transistor arrangement of organic polymer.
Background technology
Along with the progress of science and technology and the consumer requirement to display quality, Display Technique is also increasingly mature thereupon.Develop more gradually in recent years and time Display Technique from generation to generation, that is Display Technique and element slim, transparent, deflection, wherein the quality of element and its characteristic are main goals in research as far as display.
Aspect element material; The technology of hydrogenation non crystal silicon film transistor (a-Si:H TFT) is quite ripe; Therefore yet its technological temperature is high, light tight and carrier transport factor is low, is difficult to some characteristic elements, along with the manufacturing process of thin-film transistor together is made on the panel.In addition, the low temperature compound crystal silicon (low temperature poly-Silicon, LTPS) thin-film transistor technologies has higher carrier transport factor, however its technological temperature is higher than hydrogenation non crystal silicon film transistor, and manufacturing cost is higher.
Therefore, how to use the element material of other kind, its characteristic is able to solve the problem that the said elements material is had, and demands industry urgently and finds out solution.
Summary of the invention
The purpose of this invention is to provide a kind of transistor arrangement; It adopts transparent oxide semiconductor and organic polymer semiconductor, uses solve to adopt the hydrogenation non crystal silicon film transistor and low temperature compound crystal silicon have is low such as carrier transport factor, manufacturing cost is high and problem such as technological temperature height.
For reaching above-mentioned purpose, a technology kind attitude of the present invention is about a kind of transistor arrangement, and it comprises patterning N type transparent oxide semiconductor layer and patterning P type organic polymer semiconductor layer.Patterning N type transparent oxide semiconductor layer is formed at substrate top, with as base stage.Patterning P type organic polymer semiconductor layer is formed on the patterning N type transparent oxide semiconductor layer; And comprise first and second portion; Make the first and the second portion of patterning N type transparent oxide semiconductor layer and patterning P type organic polymer semiconductor layer form heterojunction respectively; Wherein the first of patterning P type organic polymer semiconductor layer is as emitter, and the second portion of patterning P type organic polymer semiconductor layer is as collector electrode.
According to one embodiment of the invention, patterning N type transparent oxide semiconductor layer comprises indium gallium zinc oxide and patterning P type organic polymer semiconductor layer comprises the five rings element.
According to another embodiment of the present invention, transistor arrangement also comprises insulating barrier, and insulating barrier is formed between substrate and the patterning N type transparent oxide semiconductor layer.
Another technology appearance attitude of the present invention is about a kind of transistor arrangement, and it comprises patterning P type organic polymer semiconductor layer, patterning N type transparent oxide semiconductor layer.Patterning P type organic polymer semiconductor layer is formed at substrate top, with as base stage.Patterning N type transparent oxide semiconductor layer is formed on the patterning P type organic polymer semiconductor layer; And comprise first and second portion; Make the first and the second portion of patterning P type organic polymer semiconductor layer and patterning N type transparent oxide semiconductor layer form heterojunction respectively; Wherein the first of patterning N type transparent oxide semiconductor layer is as emitter, and the second portion of patterning N type transparent oxide semiconductor layer is as collector electrode.
According to one embodiment of the invention, patterning N type transparent oxide semiconductor layer comprises indium gallium zinc oxide and patterning P type organic polymer semiconductor layer comprises the five rings element.
According to another embodiment of the present invention, transistor arrangement also comprises insulating barrier, and insulating barrier is formed between substrate and the patterning P type organic polymer semiconductor layer.
Another technology appearance attitude of the present invention is about a kind of transistor arrangement, and it comprises first patterned conductive layer, patterning N type transparent oxide semiconductor layer, patterning P type organic polymer semiconductor layer, patterned grid insulating layer, active layer and second patterned conductive layer.First patterned conductive layer is formed at the substrate top, and comprises first and second portion, and wherein the first of first patterned conductive layer is as the base stage conductive layer, and the second portion of first patterned conductive layer is as grid.Patterning N type transparent oxide semiconductor layer is formed in the first of first patterned conductive layer.Patterning P type organic polymer semiconductor layer is formed on the patterning N type transparent oxide semiconductor layer; And comprise first and second portion; Make the first and the second portion of patterning N type transparent oxide semiconductor layer and patterning P type organic polymer semiconductor layer form heterojunction respectively; Wherein the first of patterning P type organic polymer semiconductor layer is as emitter, and the second portion of patterning P type organic polymer semiconductor layer is as collector electrode.Patterned grid insulating layer is formed on the second portion of first patterned conductive layer.Active layer is formed on the patterned grid insulating layer, makes active layer be positioned at the second portion top of first patterned conductive layer.Second patterned conductive layer is formed on the active layer, and comprises first and second portion, and wherein the first of second patterned conductive layer is as source electrode, and the second portion of second patterned conductive layer is as drain electrode.
According to one embodiment of the invention, patterning N type transparent oxide semiconductor layer comprises indium gallium zinc oxide and patterning P type organic polymer semiconductor layer comprises the five rings element.
According to another embodiment of the present invention, active layer is patterning N type transparent oxide semiconductor layer or patterning P type organic polymer semiconductor layer.
According to further embodiment of this invention, transistor arrangement also comprises insulating barrier, and insulating barrier is formed between the first and patterning N type transparent oxide semiconductor layer of first patterned conductive layer.
A technology kind attitude more of the present invention is about a kind of transistor arrangement, and it comprises first patterned conductive layer, patterning P type organic polymer semiconductor layer, patterning N type transparent oxide semiconductor layer, patterned grid insulating layer, active layer and second patterned conductive layer.First patterned conductive layer is formed at the substrate top, and comprises first and second portion, and wherein the first of first patterned conductive layer is as the base stage conductive layer, and the second portion of first patterned conductive layer is as grid.Patterning P type organic polymer semiconductor layer is formed in the first of first patterned conductive layer.Patterning N type transparent oxide semiconductor layer is formed on the patterning P type organic polymer semiconductor layer; And comprise first and second portion; Make the first and the second portion of patterning P type organic polymer semiconductor layer and patterning N type transparent oxide semiconductor layer form heterojunction respectively; Wherein the first of patterning N type transparent oxide semiconductor layer is as emitter, and the second portion of patterning N type transparent oxide semiconductor layer is as collector electrode.Patterned grid insulating layer is formed on the second portion of first patterned conductive layer.Active layer is formed on the patterned grid insulating layer, makes active layer be positioned at the second portion top of first patterned conductive layer.Second patterned conductive layer is formed on the active layer, and comprises first and second portion, and wherein the first of second patterned conductive layer is as source electrode, and the second portion of second patterned conductive layer is as drain electrode.
According to one embodiment of the invention, patterning N type transparent oxide semiconductor layer comprises indium gallium zinc oxide and patterning P type organic polymer semiconductor layer comprises the five rings element.
According to another embodiment of the present invention, active layer is patterning N type transparent oxide semiconductor layer or patterning P type organic polymer semiconductor layer.
According to further embodiment of this invention, transistor arrangement also comprises insulating barrier, and insulating barrier is formed between the first and patterning P type organic polymer semiconductor layer of first patterned conductive layer.
Useful technique effect of the present invention is: the present invention is through adopting transparent oxide semiconductor and organic polymer semiconductor in transistor arrangement, and then solves and adopt the hydrogenation non crystal silicon film transistor and low temperature compound crystal silicon have is low such as carrier transport factor, manufacturing cost is high and problem such as technological temperature height.
Description of drawings
For let above and other objects of the present invention, characteristic, advantage can be more obviously understandable, below will combine accompanying drawing that preferred embodiment of the present invention is elaborated, wherein:
Figure 1A to Figure 1B is a kind of transistor arrangement sketch map that illustrates according to first embodiment of the invention.
Fig. 2 A to Fig. 2 B is a kind of transistor arrangement sketch map that illustrates according to second embodiment of the invention.
Fig. 3 A to Fig. 3 B is a kind of transistor arrangement sketch map that illustrates according to third embodiment of the invention.
Fig. 4 A to Fig. 4 B is a kind of transistor arrangement sketch map that illustrates according to fourth embodiment of the invention.
Fig. 5 A to Fig. 5 B is a kind of transistor arrangement sketch map that illustrates according to fifth embodiment of the invention.
Embodiment
Hereinafter is to lift the embodiment conjunction with figs. to elaborate; But the embodiment that is provided not is the scope that contains in order to restriction the present invention; And the description of structure running is non-in order to limit the order of its execution; Any structure that is reconfigured by element, the device with impartial effect that produces is all the scope that the present invention is contained.Wherein accompanying drawing is not mapped according to life size only for the purpose of description.
Figure 1A to Figure 1B is a kind of transistor arrangement sketch map that illustrates according to first embodiment of the invention.Shown in Figure 1A, transistor arrangement 100 comprises first patterned conductive layer, second patterned conductive layer, the 3rd patterned conductive layer, patterning N type transparent oxide semiconductor layer (n-type transparent oxide semiconductor) 106, patterning P type organic polymer semiconductor layer (p-type organic polymer semiconductor), patterned grid insulating layer 122, active layer 124 and outer insulating layer coating 132.
First patterned conductive layer is formed at substrate 102 tops; And comprise first 104 and second portion 118; Wherein the first 104 of first patterned conductive layer is as base stage conductive layer (base electrode), and the second portion 118 of first patterned conductive layer is as grid.Patterning N type transparent oxide semiconductor layer 106 is formed in the first 104 of first patterned conductive layer.Patterning P type organic polymer semiconductor layer is formed on the patterning N type transparent oxide semiconductor layer 106; And comprise first 108 and second portion 112; Make the patterning N type transparent oxide semiconductor layer 106 and the first 108 of patterning P type organic polymer semiconductor layer form heterojunction respectively with second portion 112; Wherein the first 108 of patterning P type organic polymer semiconductor layer is as emitter, and the second portion 112 of patterning P type organic polymer semiconductor layer is as collector electrode.
In addition; The 3rd patterned conductive layer is formed on the patterning P type organic polymer semiconductor layer; And comprise first 114 and second portion 116; Make the first 114 of the 3rd patterned conductive layer lay respectively in the first 108 and second portion 112 of patterning P type organic polymer semiconductor layer with second portion 116; Wherein the first 114 of the 3rd patterned conductive layer is as emitter conductive layer (emitter electrode), and the second portion 116 of the 3rd patterned conductive layer is as collector electrode conductive layer (collector electrode).
Secondly, patterned grid insulating layer 122 is formed on the second portion 118 of first patterned conductive layer.Active layer 124 is formed on the patterned grid insulating layer 122, makes active layer 124 be positioned at second portion 118 tops of first patterned conductive layer, and wherein active layer 124 can be patterning P type organic polymer semiconductor layer.Second patterned conductive layer is formed on the active layer 124, and comprises first 126 and second portion 128, and wherein the first 126 of second patterned conductive layer is as source electrode, and the second portion 128 of second patterned conductive layer is as drain electrode.Outer insulating layer coating 132 is formed on second patterned conductive layer and the 3rd patterned conductive layer, and part is formed on substrate 102 and the patterned grid insulating layer 122.
Thus, just can accomplish left side PNP bipolarity junction transistor (Bipolar Junction transistor, BJT) with the right side thin-film transistor (Thin Film Transistor, TFT).In addition, from the above, the bipolarity junction transistor has the identical operation of part with thin-film transistor, so its making can be made on panel separately or together.
Shown in Figure 1B, transistor arrangement 150 can be patterning N type transparent oxide semiconductor layer except its active layer 174 and is different from the transistor arrangement 100 among Figure 1A, and transistor arrangement 150 is identical with transistor arrangement 100 in fact.
In the present embodiment, patterning N type transparent oxide semiconductor layer comprises indium gallium zinc oxide (InGaZnO, IGZO), and patterning P type organic polymer semiconductor layer comprises five rings element (Pentacene).In addition, first, second and the 3rd patterned conductive layer can be metal (for example: titanium (Ti), gold (Au), aluminium (Al), molybdenum (Mo) or tin indium oxide (ITO)) or conducting polymer (for example: the mixture of doped polyaniline (Doped Polyaniline (PANI)) or polystyrolsulfon acid (PEDOT:PSS (Baytron P))).Moreover aforesaid substrate can be glass or plastic base.
Fig. 2 A to Fig. 2 B is a kind of transistor arrangement sketch map that illustrates according to second embodiment of the invention.Shown in Fig. 2 A, transistor arrangement 200 comprises first patterned conductive layer, second patterned conductive layer, the 3rd patterned conductive layer, patterning P type organic polymer semiconductor layer 206, patterning N type transparent oxide semiconductor layer, patterned grid insulating layer 222, active layer 224 and outer insulating layer coating 232.
First patterned conductive layer is formed at substrate 202 tops; And comprise first 204 and second portion 218; Wherein the first 204 of first patterned conductive layer is as base stage conductive layer (base electrode), and the second portion 218 of first patterned conductive layer is as grid.Patterning P type organic polymer semiconductor layer 206 is formed in the first 204 of first patterned conductive layer.Patterning N type transparent oxide semiconductor layer is formed on the patterning P type organic polymer semiconductor layer 206; And comprise first 208 and second portion 212; Make the first 208 of patterning P type organic polymer semiconductor layer and patterning N type transparent oxide semiconductor layer form heterojunction respectively with second portion 212; Wherein the first 208 of patterning N type transparent oxide semiconductor layer is as emitter, and the second portion 212 of patterning N type transparent oxide semiconductor layer is as collector electrode.
In addition; The 3rd patterned conductive layer is formed on the patterning N type transparent oxide semiconductor layer; And comprise first 214 and second portion 216; Make the first 214 of the 3rd patterned conductive layer lay respectively in the first 208 and second portion 212 of patterning N type transparent oxide semiconductor layer with second portion 216; Wherein the first 214 of the 3rd patterned conductive layer is as emitter conductive layer (emitter electrode), and the second portion 216 of the 3rd patterned conductive layer is as collector electrode conductive layer (collector electrode).
Secondly, patterned grid insulating layer 222 is formed on the second portion 218 of first patterned conductive layer.Active layer 224 is formed on the patterned grid insulating layer 222, makes active layer 224 be positioned at second portion 218 tops of first patterned conductive layer, and wherein active layer 224 can be patterning N type transparent oxide semiconductor layer.Second patterned conductive layer is formed on the active layer 224, and comprises first 226 and second portion 228, and wherein the first 226 of second patterned conductive layer is as source electrode, and the second portion 228 of second patterned conductive layer is as drain electrode.Outer insulating layer coating 232 is formed on second patterned conductive layer and the 3rd patterned conductive layer, and part is formed on substrate 202 and the patterned grid insulating layer 222.
Thus, just can accomplish left side NPN bipolarity junction transistor and right side thin-film transistor.In addition, from the above, the bipolarity junction transistor has the identical operation of part with thin-film transistor, so its making can be made on big panel separately or together.
Shown in Fig. 2 B, transistor arrangement 250 can be patterning P type organic polymer semiconductor layer except its active layer 274 and is different from the transistor arrangement 200 among Fig. 2 A, and transistor arrangement 250 is identical with transistor arrangement 200 in fact.
In the present embodiment, patterning N type transparent oxide semiconductor layer comprises indium gallium zinc oxide, and patterning P type organic polymer semiconductor layer comprises the five rings element.In addition, first, second and the 3rd patterned conductive layer can be metal (for example: titanium (Ti), gold (Au), aluminium (Al), molybdenum (Mo) or tin indium oxide (ITO)) or conducting polymer (for example: the mixture of doped polyaniline (Doped Polyaniline (PANI)) or polystyrolsulfon acid (PEDOT:PSS (Baytron P))).Moreover aforesaid substrate can be glass or plastic base.
Fig. 3 A to Fig. 3 B is a kind of transistor arrangement sketch map that illustrates according to third embodiment of the invention.Shown in Fig. 3 A; Transistor arrangement 100 in Figure 1A; Transistor arrangement 300 also comprises insulating barrier; Insulating barrier is formed between the first 304 and patterning N type transparent oxide semiconductor layer 306 of first patterned conductive layer; And comprise first 342 and second portion 344; Wherein the first 342 of insulating barrier is formed at the first 304 of first patterned conductive layer and a side of patterning N type transparent oxide semiconductor layer 306, and the second portion 344 of insulating barrier is formed at the first 304 of first patterned conductive layer and the opposite side of patterning N type transparent oxide semiconductor layer 306, and insulating barrier can form in processing step with patterned grid insulating layer 322 together.In the present embodiment, transistor arrangement 300 is except also comprising the insulating barrier, and its structure is identical in fact with transistor arrangement 100 among Figure 1A.
In addition; Shown in Fig. 3 B; Transistor arrangement 150 in Figure 1B; Transistor arrangement 350 also comprises insulating barrier; Insulating barrier is formed between the first 354 and patterning N type transparent oxide semiconductor layer 356 of first patterned conductive layer, and comprises first 392 and second portion 394, and wherein the first 392 of insulating barrier is formed at the first 354 of first patterned conductive layer and a side of patterning N type transparent oxide semiconductor layer 356; And the second portion 394 of insulating barrier is formed at the first 354 of first patterned conductive layer and the opposite side of patterning N type transparent oxide semiconductor layer 356, and insulating barrier can form in processing step with patterned grid insulating layer 372 together.In the present embodiment, transistor arrangement 350 is except also comprising the insulating barrier, and its structure is identical in fact with transistor arrangement 150 among Figure 1B.
Fig. 4 A to Fig. 4 B is a kind of transistor arrangement sketch map that illustrates according to fourth embodiment of the invention.Shown in Fig. 4 A; Transistor arrangement 200 in Fig. 2 A; Transistor arrangement 400 also comprises insulating barrier; Insulating barrier is formed between the first 404 and patterning P type organic polymer semiconductor layer 406 of first patterned conductive layer; And comprise first 442 and second portion 444; Wherein the first 442 of insulating barrier is formed at the first 404 of first patterned conductive layer and a side of patterning P type organic polymer semiconductor layer 406, and the second portion 444 of insulating barrier is formed at the first 404 of first patterned conductive layer and the opposite side of patterning P type organic polymer semiconductor layer 406, and insulating barrier can form in processing step with patterned grid insulating layer 422 together.In the present embodiment, transistor arrangement 400 is except also comprising the insulating barrier, and its structure is identical in fact with transistor arrangement 200 among Fig. 2 A.
In addition; Shown in Fig. 4 B; Transistor arrangement 250 in Fig. 2 B; Transistor arrangement 450 also comprises insulating barrier; Insulating barrier is formed between the first 454 and patterning P type organic polymer semiconductor layer 456 of first patterned conductive layer, and comprises first 492 and second portion 494, and wherein the first 492 of insulating barrier is formed at the first 454 of first patterned conductive layer and a side of patterning P type organic polymer semiconductor layer 456; And the second portion 494 of insulating barrier is formed at the first 454 of first patterned conductive layer and the opposite side of patterning P type organic polymer semiconductor layer 456, and insulating barrier can form in processing step with patterned grid insulating layer 472 together.In the present embodiment, transistor arrangement 450 is except also comprising the insulating barrier, and its structure is identical in fact with transistor arrangement 250 among Fig. 2 B.
Fig. 5 A to Fig. 5 B is a kind of transistor arrangement sketch map that illustrates according to fifth embodiment of the invention.Shown in Fig. 5 A, transistor arrangement 500 comprises first patterned conductive layer, second patterned conductive layer, the 3rd patterned conductive layer, the first patterning P type organic polymer semiconductor layer 506, the first patterning N type transparent oxide semiconductor layer, the second patterning N type transparent oxide semiconductor layer 522, second patterning P type organic polymer semiconductor layer and the outer insulating layer coating 534.
First patterned conductive layer is formed at substrate 502 tops; And comprise first 504 and second portion 518; Wherein the first 504 of first patterned conductive layer is as the first base stage conductive layer (first base electrode), and the second portion 518 of first patterned conductive layer is as the second base stage conductive layer (second base electrode).The first patterning P type organic polymer semiconductor layer 506 is formed in the first 504 of first patterned conductive layer, with as first base stage.The first patterning N type transparent oxide semiconductor layer is formed on the first patterning P type organic polymer semiconductor layer 506; And comprise first 508 and second portion 512; Make the first 508 of win the patterning P type organic polymer semiconductor layer 506 and the first patterning N type transparent oxide semiconductor layer form heterojunction respectively with second portion 512; Wherein the first 508 of the first patterning N type transparent oxide semiconductor layer is as emitter, and the second portion 512 of the first patterning N type transparent oxide semiconductor layer is as collector electrode.
In addition; Second patterned conductive layer is formed on the first patterning N type transparent oxide semiconductor layer; And comprise first 514 and second portion 516; Make the first 514 of second patterned conductive layer lay respectively in the first 508 and second portion 512 of patterning N type transparent oxide semiconductor layer with second portion 516; Wherein the first 514 of second patterned conductive layer is as the first emitter conductive layer (first emitter electrode), and the second portion 516 of second patterned conductive layer is as collector electrode conductive layer (first collector electrode).
Moreover the second patterning N type transparent oxide semiconductor layer 522 is formed on the second portion 518 of first patterned conductive layer, with as second base stage.The second patterning P type organic polymer semiconductor layer is formed on the second patterning N type transparent oxide semiconductor layer 522; And comprise first 524 and second portion 526; Make the first 524 of the second patterning N type transparent oxide semiconductor layer 522 and the second patterning P type organic polymer semiconductor layer form heterojunction respectively with second portion 526; Wherein the first 524 of the second patterning P type organic polymer semiconductor layer is as emitter, and the second portion 526 of the second patterning P type organic polymer semiconductor layer is as collector electrode.
The 3rd patterned conductive layer is formed on the second patterning P type organic polymer semiconductor layer; And comprise first 528 and second portion 532; Make the first 528 of the 3rd patterned conductive layer lay respectively in the first 524 and second portion 526 of the second patterning P type organic polymer semiconductor layer with second portion 532; Wherein the first 528 of the 3rd patterned conductive layer is as the second emitter conductive layer (second emitter electrode), and the second portion 532 of the 3rd patterned conductive layer is as the second collector electrode conductive layer (second collector electrode).
In the present embodiment, outer insulating layer coating 534 is formed on second patterned conductive layer and the 3rd patterned conductive layer, and part is formed on the substrate 502.In addition, first and second patterning N type transparent oxide semiconductor layer comprises indium gallium zinc oxide, and first and second patterning P type organic polymer semiconductor layer comprises the five rings element.In addition, first, second and the 3rd patterned conductive layer can be metal (for example: titanium (Ti), gold (Au), aluminium (Al), molybdenum (Mo) or tin indium oxide (ITO)) or conducting polymer (for example: the mixture of doped polyaniline (Doped Polyaniline (PANI)) or polystyrolsulfon acid (PEDOT:PSS (Baytron P))).Moreover aforesaid substrate can be glass or plastic base.
Thus, just can accomplish left side NPN bipolarity junction transistor and right side PNP bipolarity junction transistor.In addition, from the above, aforementioned two types bipolarity junction transistor has the identical operation of part, so its making can be made on big panel separately or together.For example, based on considering of circuit function, can above-mentioned two types of bipolarity junction transistors as switch be made on the drive circuit area of panel simultaneously.
Shown in Fig. 5 B; Transistor arrangement 500 in Fig. 5 A; Transistor arrangement 550 also comprises insulating barrier; Insulating barrier is formed between the first 554 and the first patterning P type organic polymer semiconductor layer 556 of first patterned conductive layer, and is formed between the second portion 568 and the second patterning N type transparent oxide semiconductor layer 572 of first patterned conductive layer, and comprises first 592, second portion 594 and third part 596.
Particularly; The second portion 594 of insulating barrier is formed between the second portion 568 of first 554 and first patterned conductive layer of first patterned conductive layer, and is formed between the first patterning P type organic polymer semiconductor layer 556 and the second patterning N type transparent oxide semiconductor layer 572.The first 592 of insulating barrier is formed at the first 554 of first patterned conductive layer and the opposite side of the first patterning P type organic polymer semiconductor layer 556.The third part 596 of insulating barrier is formed at the second portion 568 of first patterned conductive layer and the opposite side of the second patterning N type transparent oxide semiconductor layer 572.
In the present embodiment, transistor arrangement 550 is except also comprising the insulating barrier, and its structure is identical in fact with transistor arrangement 500 among Fig. 5 A.
Particularly; But the N type transparent oxide semiconductor described in the embodiment of the invention has characteristics such as low temperature depositing, deflection, the transparency and the uniformity be good; Wherein adopt indium gallium zinc oxide to be used as the thin-film transistor of active layer; Its carrier transport factor is higher than traditional hydrogenation non crystal silicon film transistor, uniformity is superior to low temperature compound crystal silicon thin-film transistor and but low temperature is made; Therefore adopt indium gallium zinc oxide film transistor to replace hydrogenation non crystal silicon film transistor AND gate low temperature compound crystal silicon thin-film transistor to make the active-matrix OLED; Can improve and adopt problem that hydrogenation non crystal silicon film transistor AND gate low temperature compound crystal silicon thin-film transistor had (for example: adopt the active layer of amorphous silicon hydride as thin-film transistor; Then it has the low and technological temperature height of carrier transport factor ... Etc. problem, and adopt the active layer of low temperature compound crystal silicon as thin-film transistor, then it has problems such as manufacturing cost height and technological temperature height).
Secondly, the P type organic polymer semiconductor described in the embodiment of the invention belongs to soft electronic, and it possesses gently, approaches, large tracts of land and characteristic such as can curl, and the application that is different from silicon and glass substrate can be provided.In addition, if will cooperate the characteristic of soft electronic microelectronic element is produced on the soft bendable plastic base, then all process steps all must be accomplished at low temperatures.Thereby; But N type transparent oxide semiconductor has the characteristic that low temperature is made; Make it be able to cooperate P type organic polymer semiconductor to reach widely and use, the transistor arrangement of processing such as cooperating two kinds of semi-conducting materials, it helps system's panel (System on Panel; SOP) realization also can be with all peripheral circuits (for example: key element, memory element and drive circuit ... Deng) all be integrated on glass or the plastic base.
Can know by the above-mentioned execution mode of the present invention, use the present invention and have advantage.The embodiment of the invention is through in transistor arrangement; Adopt transparent oxide semiconductor and organic polymer semiconductor, and then solve and adopt the hydrogenation non crystal silicon film transistor and low temperature compound crystal silicon have is low such as carrier transport factor, manufacturing cost is high and problem such as technological temperature height.
Though the present invention discloses as above with execution mode; Yet it is not in order to limit the present invention; Anyly be familiar with this operator; Do not breaking away from the spirit and scope of the present invention, when can making various changes that are equal to or replacement, so protection scope of the present invention is when looking accompanying being as the criterion that the application's claim scope defined.
Claims (14)
1. a transistor arrangement is characterized in that, comprises:
One patterning N type transparent oxide semiconductor layer is formed at substrate top, as a base stage; And
One patterning P type organic polymer semiconductor layer; Be formed on this patterning N type transparent oxide semiconductor layer; And comprise a first and a second portion; Make this first of this patterning N type transparent oxide semiconductor layer and this patterning P type organic polymer semiconductor layer form a heterojunction respectively with this second portion; Wherein this first of this patterning P type organic polymer semiconductor layer is as an emitter, and this second portion of this patterning P type organic polymer semiconductor layer is as a collector electrode.
2. transistor arrangement according to claim 1 is characterized in that, this patterning N type transparent oxide semiconductor layer comprises indium gallium zinc oxide and this patterning P type organic polymer semiconductor layer comprises the five rings element.
3. transistor arrangement according to claim 1 is characterized in that, also comprises:
One insulating barrier is formed between this substrate and this patterning N type transparent oxide semiconductor layer.
4. a transistor arrangement is characterized in that, comprises:
One patterning P type organic polymer semiconductor layer is formed at substrate top, as a base stage; And
One patterning N type transparent oxide semiconductor layer; Be formed on this patterning P type organic polymer semiconductor layer; And comprise a first and a second portion; Make this first of this patterning P type organic polymer semiconductor layer and this patterning N type transparent oxide semiconductor layer form a heterojunction respectively with this second portion; Wherein this first of this patterning N type transparent oxide semiconductor layer is as an emitter, and this second portion of this patterning N type transparent oxide semiconductor layer is as a collector electrode.
5. transistor arrangement according to claim 4 is characterized in that, this patterning N type transparent oxide semiconductor layer comprises indium gallium zinc oxide and this patterning P type organic polymer semiconductor layer comprises the five rings element.
6. transistor arrangement according to claim 4 is characterized in that, also comprises:
One insulating barrier is formed between this substrate and this patterning P type organic polymer semiconductor layer.
7. a transistor arrangement is characterized in that, comprises:
One first patterned conductive layer; Be formed at substrate top; And comprise a first and a second portion, and wherein this first of this first patterned conductive layer is as a base stage conductive layer, this second portion of this first patterned conductive layer is as a grid;
One patterning N type transparent oxide semiconductor layer is formed in this first of this first patterned conductive layer;
One patterning P type organic polymer semiconductor layer; Be formed on this patterning N type transparent oxide semiconductor layer; And comprise a first and a second portion; Make this first of this patterning N type transparent oxide semiconductor layer and this patterning P type organic polymer semiconductor layer form a heterojunction respectively with this second portion; Wherein this first of this patterning P type organic polymer semiconductor layer is as an emitter, and this second portion of this patterning P type organic polymer semiconductor layer is as a collector electrode;
One patterned grid insulating layer is formed on this second portion of this first patterned conductive layer;
One active layer is formed on this patterned grid insulating layer, makes this active layer be positioned at this second portion top of this first patterned conductive layer; And
One second patterned conductive layer is formed on this active layer, and comprises a first and a second portion, and wherein this first of this second patterned conductive layer is as one source pole, and this second portion of this second patterned conductive layer is as a drain electrode.
8. transistor arrangement according to claim 7 is characterized in that, this patterning N type transparent oxide semiconductor layer comprises indium gallium zinc oxide and this patterning P type organic polymer semiconductor layer comprises the five rings element.
9. transistor arrangement according to claim 7 is characterized in that, this active layer is to be this patterning N type transparent oxide semiconductor layer or this patterning P type organic polymer semiconductor layer.
10. transistor arrangement according to claim 7 is characterized in that, also comprises:
One insulating barrier is formed between this first and this patterning N type transparent oxide semiconductor layer of this first patterned conductive layer.
11. a transistor arrangement is characterized in that, comprises:
One first patterned conductive layer; Be formed at substrate top, and comprise a first and a second portion, it is characterized in that; This first of this first patterned conductive layer is as a base stage conductive layer, and this second portion of this first patterned conductive layer is as a grid;
One patterning P type organic polymer semiconductor layer is formed in this first of this first patterned conductive layer;
One patterning N type transparent oxide semiconductor layer; Be formed on this patterning P type organic polymer semiconductor layer; And comprise a first and a second portion; Make this first of this patterning P type organic polymer semiconductor layer and this patterning N type transparent oxide semiconductor layer form a heterojunction respectively with this second portion; Wherein this first of this patterning N type transparent oxide semiconductor layer is as an emitter, and this second portion of this patterning N type transparent oxide semiconductor layer is as a collector electrode;
One patterned grid insulating layer is formed on this second portion of this first patterned conductive layer;
One active layer is formed on this patterned grid insulating layer, makes this active layer be positioned at this second portion top of this first patterned conductive layer; And
One second patterned conductive layer is formed on this active layer, and comprises a first and a second portion, and wherein this first of this second patterned conductive layer is as one source pole, and this second portion of this second patterned conductive layer is as a drain electrode.
12. transistor arrangement according to claim 11 is characterized in that, this patterning N type transparent oxide semiconductor layer comprises indium gallium zinc oxide and this patterning P type organic polymer semiconductor layer comprises the five rings element.
13. transistor arrangement according to claim 11 is characterized in that, this active layer is this patterning N type transparent oxide semiconductor layer or this patterning P type organic polymer semiconductor layer.
14. transistor arrangement according to claim 11 is characterized in that, also comprises:
One insulating barrier is formed between this first and this patterning P type organic polymer semiconductor layer of this first patterned conductive layer.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111063703A (en) * | 2019-12-10 | 2020-04-24 | Tcl华星光电技术有限公司 | Array substrate and display device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5315129A (en) * | 1990-08-20 | 1994-05-24 | University Of Southern California | Organic optoelectronic devices and methods |
| US20090256140A1 (en) * | 2008-04-10 | 2009-10-15 | National Chiao Tung University | Light-detecting device structure |
| CN101752426A (en) * | 2008-12-03 | 2010-06-23 | 索尼株式会社 | Thin film transistor, display unit, and method of manufacturing thin film transistor |
-
2010
- 2010-10-13 CN CN201010518111.3A patent/CN102447062B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5315129A (en) * | 1990-08-20 | 1994-05-24 | University Of Southern California | Organic optoelectronic devices and methods |
| US20090256140A1 (en) * | 2008-04-10 | 2009-10-15 | National Chiao Tung University | Light-detecting device structure |
| CN101752426A (en) * | 2008-12-03 | 2010-06-23 | 索尼株式会社 | Thin film transistor, display unit, and method of manufacturing thin film transistor |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111063703A (en) * | 2019-12-10 | 2020-04-24 | Tcl华星光电技术有限公司 | Array substrate and display device |
| WO2021114327A1 (en) * | 2019-12-10 | 2021-06-17 | Tcl华星光电技术有限公司 | Array substrate and display apparatus |
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| CN102447062B (en) | 2014-02-05 |
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