CN102446952B - Semiconductor structure and formation method thereof - Google Patents
Semiconductor structure and formation method thereof Download PDFInfo
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- CN102446952B CN102446952B CN201010501694.9A CN201010501694A CN102446952B CN 102446952 B CN102446952 B CN 102446952B CN 201010501694 A CN201010501694 A CN 201010501694A CN 102446952 B CN102446952 B CN 102446952B
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Abstract
The invention relates to a semiconductor structure, and the semiconductor structure is formed on a first semiconductor layer; the semiconductor structure comprises a main nanometer line, a nanometer line group and two semiconductor substrates; each semiconductor substrate comprises at least two second semiconductor layers, each second semiconductor layer is formed on an insulating layer, and each second semiconductor layer is in one-to-one correspondence with each insulating layer in each semiconductor substrate; the nanometer line group comprises at least two nanometer lines, the main nanometer line and each nanometer line are independent and comprise third semiconductor layers, and the second semiconductor layers as well as the first semiconductor layer and/or the third semiconductor layers are made of different materials; the main nanometer line is connected with the corresponding second semiconductor layer adjacent to the first semiconductor layer; and each nanometer line is connected with each second semiconductor layer in one-to-one correspondence, and the projections, positioned on the first semiconductor layer, of nanometer lines are coincided. In addition, the invention also provides a formation method of the semiconductor structure. The formation method is favorable for increasing integrated level.
Description
Technical field
The present invention relates to technical field of semiconductors, specifically, relate to a kind of semiconductor structure and forming method thereof.
Background technology
Along with the critical dimension of semiconductor structure is more and more less, due to the particularity in structure and performance, the application prospect of nano wire aspect semiconductor structure manifested, and becomes the study hotspot in current international forward position.Especially, in VLSI (very lagre scale integrated circuit (VLSIC)) field, because nano wire has characteristic and the short channel control characteristic that height ratio is dwindled, and paid much attention to.
But, at present, described in each making, nano wire is to be all directly formed on semiconductor base, make utilizing of described semiconductor base relatively limited, for applying nano line is better beneficial to scaled down characteristic, if except being formed at the nano wire on semiconductor base, also has a kind of nano wire that is formed at semiconductor base top, can reduce to carry the area of the required semiconductor base of similar number nano wire, be beneficial to and on the semiconductor base of same area, manufacture more semiconductor structure having, increase integrated level.
Summary of the invention
In order to address the above problem, the invention provides a kind of semiconductor structure and forming method thereof, be beneficial to increase integrated level.
A kind of semiconductor structure provided by the invention, described semiconductor structure is formed on the first semiconductor layer, and described semiconductor structure comprises main nano wire, set of nanowires and two semiconductor substrates; Described in each, semiconductor substrate comprises at least two the second semiconductor layers, and described in each, the second semiconductor layer is formed on insulating barrier, described in each between semiconductor substrate, described in each the second semiconductor layer and described in each insulating barrier corresponding one by one; Described set of nanowires comprises at least two nano wires, and described main nano wire, described in each, nano wire is discrete and all comprise the 3rd semiconductor layer, and described the second semiconductor layer is different from described the first semiconductor layer and/or described the 3rd semiconductor layer material; Described main nano wire joins with corresponding described the second semiconductor layer near described the first semiconductor layer; Described the second semiconductor layer that described in each, nano wire is corresponding with each joins one by one; Described in each, the projection of nano wire on described the first semiconductor layer overlaps.
The formation method of a kind of semiconductor structure provided by the invention, comprising:
On the first semiconductor layer, determine nanowire region and form semiconductor substrate and the 3rd semiconductor layer, described the 3rd semiconductor layer covers described nanowire region and embeds in described semiconductor substrate; Described semiconductor substrate comprises at least three the second semiconductor layers, and described in each, the second semiconductor layer is sandwiched between insulating barrier; Described the second semiconductor layer is different from described the first semiconductor layer and/or described the 3rd semiconductor layer material, is formed with the first hard mask in being connected to described nanowire region on the described semiconductor substrate of one group of opposite flank;
Form the second hard mask, the described second hard mask is attached to and in the described first hard mask, is connected to the 3rd semiconductor layer described in the sidewall of described opposite flank and expose portion;
Remove described the 3rd semiconductor layer of part exposing, to form groove;
Form the 3rd hard mask, the described the 3rd hard mask covers the sidewall of described groove, and the described first hard mask, the described second hard mask are different from described insulating layer material with the described the 3rd hard mask;
Removal is away from the described semiconductor substrate of part of described nanowire region, so that be connected to the width of described opposite sides in described semiconductor substrate, be less than the width that is connected to place, other sides, insulating barrier and the second semiconductor layer described in each exposing described the first semiconductor layer, described in each;
Remove the described insulating barrier that is connected to described opposite sides in described semiconductor substrate, and the surface of described the 3rd semiconductor layer of part of exposure carrying the described first hard mask, after removing the described first hard mask, the described second hard mask and the described the 3rd hard mask, in described normal to a surface direction, described the second semiconductor layer of take is mask, remove described the 3rd semiconductor layer, then remove described the second semiconductor layer as mask;
Except close described second semiconductor layer of described the first semiconductor layer, remove the subregion of the second semiconductor layer described in each, described subregion comprise along in described groove, be connected to described the second semiconductor layer really deckle extend into the region on described the second semiconductor layer one border.
Compared with prior art, adopt technical scheme tool provided by the invention to have the following advantages:
By making described set of nanowires comprise at least two nano wires, described in each, nano wire is discrete, and described in each, the projection of nano wire on described the first semiconductor layer overlaps, and can above described semiconductor base, form nano wire, in addition, because the second semiconductor layer described in each has formed stacked structure by insulating barrier described in each, by nano wire described second semiconductor layer corresponding with each described in each joined one by one, then, the nano wire described in each of take is the channel region that basis forms device, described second semiconductor layer of each correspondence of take is that basis forms the source-drain area of device, be beneficial to and form the stacking of device, , be beneficial to the area that reduces to carry the required described semiconductor base of nano wire described in similar number, and on the described semiconductor base of same area, manufacture more device having, increase integrated level, in addition, by making described semiconductor structure also comprise main nano wire, described main nano wire joins with corresponding described the second semiconductor layer near described the first semiconductor layer, again because nano wire described in each is discrete, can make stacking source region or the drain region that comprises respectively the device of nano wire described in each be connected, utilize described main nano wire and described in each device can form amplifier, be beneficial to when formation has the described amplifier of identical amplifying power, reduce the described semiconductor base that described amplifier takies area and.
By making described grid be connected to described main nano wire and nano wire described in each, that is, make each device share a described grid, be beneficial to further increase integrated level.
By making described side wall be positioned at described main nano wire and described set of nanowires top, be beneficial to after forming described side wall, can expose described main nano wire and nano wire described in each, then, in subsequent step, take described side wall as mask, can carry out metalized to described main nano wire and nano wire described in each, be beneficial to the resistance that reduces device.
By make described contact hole and described in each the second semiconductor layer join, can control respectively the second semiconductor layer described in each, then control respectively the different components that comprises the second semiconductor layer described in each, be beneficial to technological design.
By making described nano wire there is smooth surface, be beneficial in described nanowire surface and form uniform passivation layer (as hafnium base oxide layer or Al
2o
3, La
2o
3, ZrO
2, a kind of or its combination in LaAlO), can provide uniform described gate dielectric layer utilizing described nano wire to form device and usining described passivation layer during as gate dielectric layer, be beneficial to optimized device performance.
Accompanying drawing explanation
Fig. 1 to Fig. 7 is respectively the vertical view of semiconductor structure embodiment of the present invention and respectively along the cutaway view of AA ', BB ', CC ', DD ', EE ' and FF ' direction;
Fig. 8 forms the cutaway view after semiconductor substrate in the formation embodiment of the method for semiconductor structure of the present invention;
Fig. 9 to Figure 11 is respectively the vertical view that forms in the formation embodiment of the method for semiconductor structure of the present invention after the first hard mask and along the cutaway view of AA ', BB ' direction;
Figure 12 to Figure 14 is respectively the vertical view that forms in the formation embodiment of the method for semiconductor structure of the present invention after the 3rd semiconductor layer and along the cutaway view of AA ', BB ' direction;
Figure 15 to Figure 17 is respectively the vertical view that forms in the formation embodiment of the method for semiconductor structure of the present invention after the second hard mask and along the cutaway view of AA ', BB ' direction;
Figure 18 to Figure 20 is respectively the vertical view that forms in the formation embodiment of the method for semiconductor structure of the present invention after groove and along the cutaway view of AA ', BB ' direction;
Figure 21 to Figure 23 is respectively the vertical view that forms in the formation embodiment of the method for semiconductor structure of the present invention after the 3rd hard mask and along the cutaway view of AA ', BB ' direction;
Figure 24 to Figure 26 is respectively and in the formation embodiment of the method for semiconductor structure of the present invention, removes in described semiconductor substrate away from the vertical view after the part of described nanowire region with along the cutaway view of AA ', BB ' direction;
Figure 27 to Figure 28 is respectively the cutaway view forming in the formation embodiment of the method for semiconductor structure of the present invention behind heterogeneous district along AA ', BB ' direction;
Figure 29 to Figure 31 is respectively the vertical view of the device architecture forming in the formation embodiment of the method for semiconductor structure of the present invention and along the cutaway view of AA ', BB ' direction;
Figure 32 is the cutaway view of carrying out in the formation embodiment of the method for semiconductor structure of the present invention after annealing operation along AA ' direction;
Figure 33 to Figure 36 is respectively vertical view after the part upper surface that exposes each second semiconductor layer in the formation embodiment of the method for semiconductor structure of the present invention and along the cutaway view of BB ', CC ', FF ' direction;
Figure 37 to Figure 38 is respectively and in the formation embodiment of the method for semiconductor structure of the present invention, cuts off near the vertical view after the second semiconductor layer of the first semiconductor layer with along the cutaway view of FF ' direction;
Figure 39 to Figure 42 is respectively the cutaway view forming in the formation embodiment of the method for semiconductor structure of the present invention after first grid along BB ', CC ', DD ', EE ' direction;
Figure 43 to Figure 46 is respectively the cutaway view forming in the formation embodiment of the method for semiconductor structure of the present invention after the first interlayer dielectric layer along BB ', CC ', DD ', EE ' direction;
Figure 47 to Figure 50 is respectively the cutaway view forming in the formation embodiment of the method for semiconductor structure of the present invention after side wall along BB ', CC ', DD ', EE ' direction;
Figure 51 to Figure 53 is respectively the cutaway view forming in the formation embodiment of the method for semiconductor structure of the present invention after contact hole along BB ', CC ', FF ' direction.
Embodiment
Disclosing below provides many different embodiment or example to be used for realizing technical scheme provided by the invention.Although hereinafter the parts of specific examples and setting are described,, they are only example, and object does not lie in restriction the present invention.
In addition, the present invention can be in different embodiment repeat reference numerals and/or letter.This repetition is in order to simplify and object clearly, itself do not indicate discussed various embodiment and/or arrange between relation.
The invention provides the example of various special processes and/or material, still, other techniques that those of ordinary skills can recognize and/or the alternate application of other materials, obviously do not depart from the scope of protection of present invention.Need emphasize, in presents, the border in described various regions comprises the necessary extension of doing due to the needs of technique or processing procedure.
The invention provides a kind of semiconductor structure, as shown in Figures 1 to 7, described semiconductor structure is formed on the first semiconductor layer 100, and described semiconductor structure comprises main nano wire 144, set of nanowires 140 (as empty frame in Fig. 2 indicates) and two semiconductor substrates 120 (as empty frame in Fig. 3 indicates); Described in each, semiconductor substrate 120 comprises at least two the second semiconductor layers 122, and described in each, the second semiconductor layer 122 is formed on insulating barrier 124; Described in each between semiconductor substrate 120, described in each the second semiconductor layer 122 and described in each insulating barrier 124 corresponding one by one; Described set of nanowires 140 comprises at least two nano wires 142, described main nano wire 144, described in each, nano wire 142 is discrete and all comprise the 3rd semiconductor layer, and described the second semiconductor layer 122 is different from described the first semiconductor layer 100 and/or described the 3rd semiconductor layer material; Described main nano wire 144 joins with corresponding described the second semiconductor layer 122 near described the first semiconductor layer 100; Described the second semiconductor layer 122 that described in each, nano wire 142 is corresponding with each joins one by one, and described in each, the projection of nano wire 142 on described the first semiconductor layer 100 overlaps.
Wherein, described the first semiconductor layer 100 can be silicon substrate, and preferably, described the first semiconductor layer 100 is silicon epitaxy layer, and described the first semiconductor layer 100 also can be silicon-on-insulator (SOI); Now, described the 3rd semi-conducting material can be silicon or doped silicon, described doped silicon comprises that the silicon materials that completed ion doping through ion implantation technology (can be the silicon materials of N-type or P type, as, the silicon materials of doping B, P or As) and through epitaxial growth technology (mixing the reactant that comprises the ion component that adulterate as generated in the reactant of silicon), directly form the silicon materials that adulterate (as for PMOS device, described silicon materials can be Si
1-Xge
x, wherein, the span of X can be 0.1～0.7, as 0.2,0.3,0.4,0.5 or 0.6; For nmos device, described silicon materials can be Si:C, and wherein, the span of the atomicity percentage of C can be 0.2%～2%, as 0.5%, 1% or 1.5%).It should be noted that, described the first semiconductor layer 100 materials also can be doped silicon, and described doped silicon is identical with above-mentioned doped silicon, repeats no more.
When described the first semiconductor layer 100 materials or described the 3rd semiconductor layer material are silicon or doped silicon, described the second semiconductor layer 122 materials are doping or unadulterated polysilicon or amorphous silicon.Be preferably the polysilicon (doped chemical can be B, P or As etc.) of doping, be both beneficial to when graphical described the second semiconductor layer 122 and obtained high-quality figure, be also beneficial to and take described the second semiconductor layer 122 optimized device performance when basis provides source-drain area.Described insulating barrier 124 can be silicon oxide layer.
In presents, " described in each between semiconductor substrate 120, described in each the second semiconductor layer 122 and described in each insulating barrier 124 corresponding one by one " mean: while comprising two described semiconductor substrates 120 (being designated as respectively the first semiconductor substrate and the second semiconductor substrate) in described device, described the first semiconductor substrate comprises that (direction along away from described the first semiconductor layer 100, is denoted as 1241 and 1243 to three described insulating barriers 124, it should be noted that, for taking into account the simple and clear and clear of attached number in the figure, the second semiconductor layer described in each, described in each insulating barrier and follow-up described in each differentiation of nano wire only in Fig. 7, give exemplary concrete label, in other accompanying drawings, do not distinguish), and described in each, between insulating barrier 124, accompany altogether two described the second semiconductor layers 122 (along the direction away from described the first semiconductor layer 100, be denoted as 1221 and 1223) time, described the second semiconductor substrate also comprises that three described insulating barriers 124 are (along the direction away from described the first semiconductor layer 100, be denoted as 1242 and 1244) and described in each, between insulating barrier 124, also accompany altogether two described the second semiconductor layers 122 (along the direction away from described the first semiconductor layer 100, be denoted as 1222 and 1224).The material of the described insulating barrier 124 in described the first semiconductor substrate and described insulating barrier 124 in described the second semiconductor substrate is identical with thickness, as 1241 and 1242,1243 and 1244; The material of the second semiconductor layer 122 in described the first semiconductor substrate and the second semiconductor layer 122 in described the second semiconductor substrate is identical with thickness, as 1221 and 1222,1223 and 1224.
" described second semiconductor layer 122 of each correspondence " means a combination that described the second semiconductor layer 122 forms in arbitrary described the second semiconductor layer 122 and described the second semiconductor substrate in described the first semiconductor substrate, the material of the two identical with thickness (as 1221 and 1222 and 1223 and 1224), described in each, the second semiconductor layer 122 can only belong to a certain definite combination.
" described the second semiconductor layer 122 that described in each, nano wire 142 is corresponding with each joins one by one " means nano wire 142 described in each and is connected to arbitrary described combination; For arbitrary described combination, only join with unique described nano wire 142, as, when described set of nanowires comprises 2 described nano wires, (edge is away from the direction of described the first semiconductor layer 100, be denoted as 1421 and 1423), nano wire 1421 is connected to 1221 and 1222, and nano wire 1423 is connected to 1223 and 1224.
Described semiconductor structure also comprises grid 160, and described grid 160 can adopt first grid (gate first) or rear grid (gate last) technique to form; While adopting first grid technique, described grid 160 can be polysilicon gate or metal gates, and (described metal gate material can be a kind of or its combination in Ti, Co, Ni, Al, W, described metal gates is formed in workfunction layers, and described workfunction layers can be a kind of or its combination in TiN, TiAlN, TaN, TaAlN, TaC); While adopting rear grid technique, described grid 160 comprises workfunction layers and metal level, described metal level is formed at (all not shown in described workfunction layers and described metal level figure) in described workfunction layers, wherein, described workfunction layers can be a kind of or its combination in TiN, TiAlN, TaN, TaAlN, TaC; Described metal level can be a kind of or its combination in Ti, Co, Ni, Al, W.
In the present embodiment, described grid 160 is connected to described main nano wire 144 and nano wire 142 described in each through gate dielectric layer 164.Described gate dielectric layer 164 can be high dielectric constant material HfO
2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al
2o
3, La
20
3, ZrO
2, a kind of or its combination in LaAlO, described gate dielectric layer 164 also can be traditional insulating material such as silica.Take described main nano wire 144 and described in each, nano wire 142 is the channel region that forms device, basis, described second semiconductor layer 122 of take each correspondence source-drain area that forms device as basis forms the heap poststack of device, make again described grid 160 be connected to described main nano wire 144 and nano wire 142 described in each,, can make each device share a described grid 160, be beneficial to further increase integrated level.
Described semiconductor structure also comprises side wall 162, and described side wall 162 is connected to relative both sides in described grid 160.Described side wall 162 can comprise a kind of or its combination in silicon nitride, silica, silicon oxynitride or carborundum.Described side wall 162 can have sandwich construction.In the present embodiment, described side wall 162 is positioned at described main nano wire 144 and described set of nanowires 140 tops; Be beneficial to after forming described side wall 162, expose described main nano wire 144 and nano wire 142 described in each, then, in subsequent technique, the described side wall 162 of take is mask, can carry out metalized with nano wire 142 described in each to described main nano wire 144, is beneficial to the resistance that reduces device.Especially, described main nano wire 144 also comprises metallized semi conductor layer with nano wire 142 described in each, described metallized semi conductor layer is below folded region between described side wall 162 and described the second semiconductor layer 122 and be connected to described the second semiconductor layer 122, is beneficial to the resistance that reduces device.
Described semiconductor structure also comprises that contact hole is (in illustrated embodiment, described in each, on semiconductor substrate, be formed with 2 contact holes, be designated as respectively 182 and 184), described contact hole and described in each the second semiconductor layer 122 (through metal silicide layer 180) join; Be beneficial to and control respectively the second semiconductor layer 122 described in each, then control respectively the different components that comprises the second semiconductor layer 122 described in each, be beneficial to technological design.In other embodiments, described in each in same described semiconductor substrate, the second semiconductor layer 122 can be connected to same described contact hole, now, described in each, the second semiconductor layer 122 can Synchronization Control, can make source region or the drain region of each stacking device be connected, utilize described main nano wire and described in each device can form amplifier, be beneficial to when formation has the described amplifier of identical amplifying power, reduce the described semiconductor base that described amplifier takies area and.。
Described nano wire 142 can have smooth surface.In presents, described smooth surface means the cross section perpendicular to its length direction in described nano wire 142 does not have the wedge angle protruding.That is, described cross section can be the circle shown in Fig. 2, also can be ellipse, also can be rectangle or squarely carries out the figure that corners obtains.Described nano wire 142 has smooth surface, is beneficial on described nano wire 142 surfaces and forms uniform passivation layer (as hafnium base oxide layer or Al
2o
3, La
2o
3, ZrO
2, a kind of or its combination in LaAlO), can, utilizing described nano wire 142 to form semiconductor structures and usining described passivation layer during as gate dielectric layer 164, provide uniform described gate dielectric layer 164, to optimize the performance of described semiconductor structure.
Wherein, in presents, nano wire 142 described in each, described in each, semiconductor substrate, described grid 160, described side wall 162 and described contact hole are all embedded in interlayer dielectric layer 190.In above-described embodiment, only exemplarily provided the example that comprises two described nano wires 142 in described set of nanowires 140, according to the instruction of above-described embodiment, those skilled in the art can know described in each and comprise other execution modes more than two described nano wires 142 in set of nanowires 140, repeat no more.
The present invention also provides a kind of formation method of semiconductor structure, comprising:
First, as shown in Figure 8, on the first semiconductor layer 200, interval forms insulating barrier 202 and the second semiconductor layer 204 (to form semiconductor substrate), the number of described the second semiconductor layer 204 is at least three and (in the present embodiment, is three, in other embodiments, can be more than three), described in each, the second semiconductor layer 204 is sandwiched between insulating barrier 202, subsequently, on described semiconductor substrate, (on the described insulating barrier 202 away from described the first semiconductor layer 200) forms the first hard mask layer 206.
Described the first semiconductor layer 200 can be silicon substrate, and preferably, described the first semiconductor layer 200 is silicon epitaxy layer, and described the first semiconductor layer 200 also can be silicon-on-insulator (SOI).Described the second semiconductor layer 204 can be doping or unadulterated polysilicon or amorphous silicon.Be preferably the polysilicon (doped chemical can be B, P or As etc.) of doping, be both beneficial to when graphical described the second semiconductor layer 204 and obtained high-quality figure, be also beneficial to and take described the second semiconductor layer 204 optimized device performance when basis provides source-drain area.Described insulating barrier 202 can be silicon oxide layer.Described the first hard mask layer 206 can be silicon nitride layer.
Can form described semiconductor substrate and described the first hard mask layer 206 by depositing operation.Can adopt chemical vapor deposition (CVD), physical vapor deposition (PVD), pulsed laser deposition (PLD), atomic layer deposition (ALD), plasma enhanced atomic layer deposit (PEALD) or other applicable technique to carry out described electroless copper deposition operation.
Then, shown in Figs. 9 to 11, remove described first hard mask layer 206 (to form the first hard mask 208) of subregion, bar-shaped zone as shown, to expose the described insulating barrier 202 in described region; Predetermined, in order to form in the region (being nanowire region) of nano wire, remove described semiconductor substrate again, to expose described the first semiconductor layer 200.Can utilize anisotropic etch process (as RIE) carry out as described in removal operation.Now, only in being connected to described nanowire region, on the described semiconductor substrate of one group of opposite flank, be formed with the described first hard mask 208; And the described semiconductor substrate that is connected to another group opposite flank in described nanowire region only exposes described insulating barrier 202.
Again, as shown in Figure 12 to 14, on described the first semiconductor layer 200 exposing, form the 3rd semiconductor layer 220, can epitaxial growth technology form described the 3rd semiconductor layer 220, described the 3rd semiconductor layer 220 materials can be silicon or doped silicon; Subsequently, then remove described the 3rd semiconductor layer 220 of Partial Height, make the upper surface of described the 3rd semiconductor layer 220 lower than the upper surface of the described first hard mask 208, to expose the sidewall that is connected to described opposite flank in the described first hard mask 208; Can cmp (CMP) technique carry out described removal operation.
In the present embodiment, the upper surface of the described insulating barrier 202 that the upper surface of described the 3rd semiconductor layer 220 can expose with above-mentioned bar-shaped zone is concordant; In presents, term " upper surface " means to be parallel in the described semiconductor substrate of described the 3rd semiconductor layer 220 materials or exposure the side of described the first semiconductor layer 200; Term " concordant " means the difference in height of the two in the scope of fabrication error permission.
Again, as shown in Figure 15 to 17, form the second hard mask 218, the described second hard mask 218 is attached to and in the described first hard mask 208, is connected to the 3rd semiconductor layer 220 described in the sidewall of described opposite flank and expose portion.Can depositing-etching technique form the described second hard mask 218; The described second hard mask 218 materials can be silicon nitride.
Subsequently, as shown in Figure 18 to 20, remove described the 3rd semiconductor layer 220 of part exposing, to form groove 240, described groove 240 exposes described the first semiconductor layer 200.Can RIE technique carry out described removal operation.
Then, as shown in Figure 21 to 23, form the 3rd hard mask 228, the described the 3rd hard mask 228 covers the sidewall of described groove 240.Can depositing-etching technique form the described the 3rd hard mask 228; The described the 3rd hard mask 228 materials can be silicon nitride.
Subsequently, as shown in Figure 24 to 26, remove in described semiconductor substrate the part away from described nanowire region, so that carry the width at the described first hard mask 208 places in described semiconductor substrate, be less than the width that is connected to its elsewhere, described nanowire region, insulating barrier 202 and the second semiconductor layer 204 described in each exposing described the first semiconductor layer 200, described in each.In presents, described width means shared wire space in the direction perpendicular to side, described nanowire region, arbitrary region.Can RIE technique carry out described removal operation.
Again, as shown in Figure 27 to 28, (described in this part, insulating barrier 202 is connected to one opposite flank, described nanowire region to the described insulating barrier 202 in the described semiconductor substrate of removal carrying the described first hard mask 208; Now, in described semiconductor substrate, being connected to insulating barrier 202 described in each of another opposite sides is also partly removed; For the described semiconductor substrate not covered by the described first hard mask 208, the described insulating barrier 202 of its exposure is also removed, and then, make the described semiconductor substrate not covered by the described first hard mask 208 expose described the second semiconductor layer 204), and the surface of described the 3rd semiconductor layer 220 of part of exposure carrying the described first hard mask 208; Then, carry out oxidation operation, to form heterogeneous district 222 (now on described the 3rd semiconductor layer 220 exposing, described the second semiconductor layer 204 can prevent that described the 3rd semiconductor layer 220 of its covering is oxidized, that is, described the second semiconductor layer 204 can play the effect of mask), described heterogeneous district 222 materials are different with described the 3rd semiconductor layer 220 materials from described the second semiconductor layer 204 materials, in the present embodiment, described heterogeneous district 222 materials are silica; Now, described the second semiconductor layer 204 as mask is also oxidized to silica by part (top layer 2044 is oxidized); In addition described the second semiconductor layer 204 exposing in described semiconductor substrate, is also oxidized to heterogeneous district 222 (being silica).
Then, remove the described first hard mask 208, the described second hard mask 218 and the described the 3rd hard mask 228, described the second semiconductor layer 204 of take is again mask, remove described heterogeneous district 222, upper in described normal to a surface direction (as shown by arrows), described the 3rd semiconductor layer 220 is run through in described heterogeneous district 222; And then, remove described the second semiconductor layer 204 as mask, obtain the device architecture as shown in Figure 29 to 31.First make described the 3rd semiconductor layer 220 of part to be removed form described heterogeneous district 222, remove again described heterogeneous district 222 to remove described the 3rd semiconductor layer 220 of part and then graphical described the 3rd semiconductor layer 220, can make described heterogeneous district 222 mainly be formed at the region that described mask exposes, and the region that described mask is covered only produces less impact, be beneficial to after removing described heterogeneous district 222, the region that described mask is covered only produces less lateral erosion, is beneficial to more accurately and shifts mask pattern on described the 3rd semiconductor layer 220.
It should be noted that, in other embodiments, after the surface of described the 3rd semiconductor layer 220 of part that exposes carrying the described first hard mask 208, described the second semiconductor layer 204 of take is mask, in described normal to a surface direction (as shown by arrows), adopt isotropic etching (as wet etching) technique remove as described in the 3rd semiconductor layer 220, also (described the second semiconductor layer 204 of just now exposing in described semiconductor substrate is not oxidized is heterogeneous district 222 can to obtain the device architecture shown in similar Figure 29 to 31, in the device architecture forming, comprise three described the 3rd semiconductor layers 220), those skilled in the art can choose concrete technology according to actual needs flexibly.
Subsequently, shown in figure 32, can carry out annealing operation to described device architecture.Particularly, can be at H
2or under He atmosphere, carry out described annealing operation.Be beneficial to the part that makes to expose in described device architecture (as, in order to form the 3rd semiconductor layer 220 of nano wire) there is smooth surface, be beneficial in described nanowire surface and form uniform passivation layer (as hafnium base oxide layer or Al
2o
3, La
2o
3, ZrO
2, a kind of or its combination in LaAlO), can provide uniform described gate dielectric layer utilizing described nano wire to form device and usining described passivation layer during as gate dielectric layer, be beneficial to optimized device performance.
Again, as shown in Figure 33 to Figure 36, except close described second semiconductor layer 204 of described the first semiconductor layer 200, remove the subregion of the second semiconductor layer 204 described in each, described subregion comprise along in described groove 240, be connected to described the second semiconductor layer 204 really deckle extend into the region on described the second semiconductor layer 204 1 borders.
Wherein, the step of removing the subregion of the second semiconductor layer 204 described in each comprises: first remove described in the ground floor exposing subregion on the second semiconductor layer 204, to expose the subregion of the second semiconductor layer 204 described in the second layer; Until remove subregion on described the second semiconductor layer 204 of N layer exposing, to expose the subregion of described the second semiconductor layer 204 of N+1 layer, N is more than or equal to 1 natural number.In the present embodiment, N equals 1.Particularly, in one embodiment of the invention, except close described second semiconductor layer 204 of described the first semiconductor layer 200, described in each, in the second semiconductor layer 204, removed subregion can be identical.
In the present embodiment, for removing the subregion in described the second semiconductor layer 204, each complete described second semiconductor layer 204 can be divided into 2 regions (being designated as respectively 2041 and 2043), make subregion (remaining area 2041 or region 2043 at the second semiconductor layer 204 described in removal ground floor, in the present embodiment, remaining area 2041) time, region 2043 is removed, and expose the region 2043 (insulating barrier between each layer of described the second semiconductor layer can be removed by corresponding technique, repeats no more) of the second semiconductor layer 204 described in the second layer.Can be by form resist layer on described the second semiconductor layer 204, and adopt the mode of photoetching and the graphical described resist layer of etching technics, carry out described removal operation.
Because described the 3rd semiconductor layer 220 is connected to described the second semiconductor layer 204, when removing corresponding described the second semiconductor layer 204, described the 3rd semiconductor layer 220 being sandwiched between corresponding described the second semiconductor layer 204 also will be removed, and described the 3rd semiconductor layer 220 will provide the channel region existing with nano wire form in the semiconductor structure of follow-up formation, , being connected to described in ground floor described the 3rd semiconductor layer in region 2043 in the second semiconductor layer is removed, described the 3rd semiconductor layer in the second semiconductor layer region 2043 described in the second layer that is connected to that is arranged in its below is retained, and in the semiconductor structure forming as main nano wire, be connected to described in ground floor and the second layer described in each of region 2041 in the second semiconductor layer the 3rd semiconductor layer in the semiconductor structure forming as each nano wire.In the second semiconductor layer as described in cutting off as shown in Figure 37 and Figure 38 behind region 2043, do not carry the region 2043 in region 2041 in described the second semiconductor layer by the device that comprises main nano wire in order to formation, other regions 2043 and 2041 will be in order to form the device that comprises respectively each nano wire.
Then, also can on described device architecture, form grid structure and contact hole.Wherein, the order that forms described grid structure and described contact hole can be selected according to flexible process design.
Particularly, the step that forms described grid structure comprises:
First, as shown in Figure 39 to Figure 42, form first grid 260, described first grid 260 is connected to described the 3rd semiconductor layer 220 through gate dielectric layer 262.When adopting first grid technique to form described first grid 260, described first grid 260 materials can be the polysilicon of doping; When after employing, grid technique forms described first grid 260, described first grid 260 materials can be doping or unadulterated polysilicon or amorphous silicon.Described gate dielectric layer 262 materials can be hafnium base oxide layer or Al
2o
3, La
2o
3, ZrO
2, a kind of or its combination in LaAlO, described gate dielectric layer 262 also can be traditional insulating material such as silica.
Again, as shown in Figure 43 to Figure 46, form the first interlayer dielectric layer 264 of planarization, so that the first interlayer dielectric layer 264 of described planarization covers described the 3rd semiconductor layers 220 and exposes upper surface and the partial sidewall of described first grid 260, described partial sidewall is formed to downward-extension by described upper surface.
The step that forms the first interlayer dielectric layer 264 of described planarization can comprise: form the first interlayer dielectric layer, described the first interlayer dielectric layer covers described first grid; The first interlayer dielectric layer described in planarization, to expose described first grid 260; The first interlayer dielectric layer described in etching, to expose upper surface and the partial sidewall of described first grid 260.Can CMP technique carry out described planarization operation, with RIE technique, carry out described etching operation.Now, the first interlayer dielectric layer 264 of described planarization covers described in each the second semiconductor layer 204 and the 3rd semiconductor layer 220 described in each.
Then, as shown in Figure 47 to Figure 50, form side wall 266, described side wall 266 is formed on the first interlayer dielectric layer 264 of described planarization and is attached in described partial sidewall.Can adopt depositing-etching technique to form described side wall 266.Described side wall 266 can comprise a kind of or its combination in silicon nitride, silica, silicon oxynitride or carborundum.Described side wall 266 can have sandwich construction.In the present embodiment, described side wall 266 is positioned at the 3rd semiconductor layer 220 (that is, set of nanowires) top described in each; Be beneficial to after forming described side wall 266, can expose nano wire described in each, then, in subsequent technique, the described side wall 266 of take is mask, can carry out metalized to nano wire described in each, is beneficial to the resistance that reduces device.
Further, the described side wall 266 of take is mask, removes the first interlayer dielectric layer 264 of the described planarization of part, to expose described the 3rd semiconductor layer 220; Described the 3rd semiconductor layer 220 metallizes.Be beneficial to the resistance that reduces device.Wherein, the step of described the 3rd semiconductor layer 220 that metallizes can comprise: first form the first metal layer (as a kind of or its combination in Ti, Co, Cu, Ni), to cover described device architecture; Carry out again heat treatment operation, described the 3rd semiconductor layer that makes to be covered by described the first metal layer in described device architecture form metal silicide layer (now, described first grid and described in each top layer of the second semiconductor layer be also all formed with metal silicide layer); Remove unreacted described the first metal layer.
As shown in Figure 51 to Figure 53, after forming described grid structure, can continue to form contact hole 280, specifically comprise: first, form the second interlayer dielectric layer 268, (described the second interlayer dielectric layer 268 covers described the first interlayer dielectric layer, cover described in each the second semiconductor layer 204 and the 3rd semiconductor layer 220 described in each), what need emphasize is, while adopting rear grid technique, after forming described second medium layer 268, also comprise: with second grid, substitute described first grid, described second grid material is metal material.Described second grid comprises workfunction layers and the second metal level, described the second metal level is formed at (all not shown in described workfunction layers and described the second metal level figure) in described workfunction layers, wherein, described workfunction layers can be a kind of or its combination in TiN, TiAlN, TaN, TaAlN, TaC; Described the second metal level can be a kind of or its combination in Ti, Co, Ni, Al, W; Subsequently, at the interior formation contact hole of described the second interlayer dielectric layer 268, described contact hole (through metal silicide 282) is connected to the subregion of the second semiconductor layer 204 upper surfaces described in each.Wherein, the step that forms described contact hole 280 comprises: at the interior formation groove of described the second interlayer dielectric layer 268, described groove exposes the subregion of the second semiconductor layer 204 upper surfaces described in each; With the 3rd metal level, fill described groove.Described the 3rd metal level comprises bed course (a kind of or its combination in Ta, TaN, Ti, TiN) and filling metal level (a kind of or its combination in W, Al, Cu, TiAl), and described filling metal level is formed on described bed course.It should be noted that, in the description of the various embodiments described above, the second semiconductor layer 204 is contained the second semiconductor layer 2041, the second semiconductor layer 2042 and/or the second semiconductor layer 2043.
In addition, in other embodiments, the step that forms described contact hole on described device architecture comprises: first, form the second interlayer dielectric layer, described the second interlayer dielectric layer covers the second semiconductor layer described in each; Again, in described the second interlayer dielectric layer, form contact hole, described contact hole is connected to the subregion (identical with step in previous embodiment, to repeat no more) of upper surface described in each of exposure.Now, can any traditional technique form described grid structure.
In presents, can adopt and form each interlayer dielectric layer (as the first interlayer dielectric layer and the second interlayer dielectric layer) as CVD and/or other suitable technique, described in each, inter-level dielectric layer material can comprise a kind of or its combination in silica glass, fluorine silex glass, Pyrex, phosphorosilicate glass, boron-phosphorosilicate glass, carbon silex glass, low K dielectrics material (as black diamond, coral etc.).Described in each, interlayer dielectric layer can have sandwich construction.
Need emphasize, range of application of the present invention is not limited to technique, structure, manufacture, material composition, means, method and the step of the specific embodiment of describing in specification.According to disclosure of the present invention; those skilled in the art will easily understand; for the technique, mechanism, manufacture, material composition, means, method or the step that have existed or be about to develop at present later; they are when carrying out the function identical with the corresponding embodiment cardinal principle of the present invention's description or obtaining substantially identical result; according to instruction of the present invention; can apply them, and not depart from the present invention's scope required for protection.
Claims (11)
1. a formation method for semiconductor structure, is characterized in that, comprising:
On the first semiconductor layer, determine nanowire region and form semiconductor substrate and the 3rd semiconductor layer, described the 3rd semiconductor layer covers described nanowire region and embeds in described semiconductor substrate; Described semiconductor substrate comprises at least three the second semiconductor layers, and described in each, the second semiconductor layer is sandwiched between insulating barrier; Described the second semiconductor layer is different from described the first semiconductor layer and/or described the 3rd semiconductor layer material, is formed with the first hard mask in being connected to described nanowire region on the described semiconductor substrate of one group of opposite flank;
Form the second hard mask, the described second hard mask is attached to and in the described first hard mask, is connected to the 3rd semiconductor layer described in the sidewall of described opposite flank and expose portion;
Remove described the 3rd semiconductor layer of part exposing, to form groove;
Form the 3rd hard mask, the described the 3rd hard mask covers the sidewall of described groove, and the described first hard mask, the described second hard mask are different from described insulating layer material with the described the 3rd hard mask;
Removal is away from the described semiconductor substrate of part of described nanowire region; so that be connected to the width of described opposite sides in described semiconductor substrate, be less than the width that is connected to place, other sides, insulating barrier and the second semiconductor layer described in each exposing described the first semiconductor layer, described in each;
Remove the described insulating barrier that is connected to described opposite sides in described semiconductor substrate; and the surface of described the 3rd semiconductor layer of part of exposure carrying the described first hard mask; after removing the described first hard mask, the described second hard mask and the described the 3rd hard mask; in described normal to a surface direction; described the second semiconductor layer of take is mask; remove described the 3rd semiconductor layer, then remove described the second semiconductor layer as mask;
Except close described second semiconductor layer of described the first semiconductor layer, remove the subregion of the second semiconductor layer described in each, described subregion comprise along in described groove, be connected to described the second semiconductor layer really deckle extend into the region on described the second semiconductor layer one border.
2. method according to claim 1, is characterized in that, also comprises:
Form first grid, described first grid is connected to described the 3rd semiconductor layer through gate dielectric layer, and described first grid material is semi-conducting material and different from described the 3rd semiconductor layer material;
Form the first interlayer dielectric layer of planarization, so that the first interlayer dielectric layer of described planarization covers described the 3rd semiconductor layer and exposes upper surface and the partial sidewall of described first grid, described partial sidewall is formed to downward-extension by described upper surface;
Form side wall, described side wall is formed on the first interlayer dielectric layer of described planarization and is attached in described partial sidewall.
3. method according to claim 2, is characterized in that, also comprises:
Take described side wall as mask, remove the first interlayer dielectric layer of described planarization, to expose described the 3rd semiconductor layer;
Described the 3rd semiconductor layer metallizes.
4. according to the method described in claim 1 or 3, it is characterized in that, also comprise:
Form the second interlayer dielectric layer, described the second interlayer dielectric layer covers described in each the second semiconductor layer and the 3rd semiconductor layer described in each;
In described the second interlayer dielectric layer, form contact hole, described contact hole is connected to subregion described in each.
5. method according to claim 3, is characterized in that, is forming described side wall to exposing between described the 3rd semiconductor layer, also comprises: with second grid, substitute described first grid, described second grid material is metal material.
6. method according to claim 1, is characterized in that, determines nanowire region and form semiconductor substrate and the step of described the 3rd semiconductor layer comprises on the first semiconductor layer:
On the first semiconductor layer, order forms semiconductor substrate and the first hard mask layer; described semiconductor substrate comprises at least three the second semiconductor layers; described in each, the second semiconductor layer is sandwiched between insulating barrier, and described the first hard mask layer is formed on described semiconductor substrate;
Determine nanowire region; and remove the described semiconductor substrate in described the first hard mask layer of part and described nanowire region; on described semiconductor substrate with one group of opposite flank in being connected to described nanowire region, form the first hard mask, and expose described the first semiconductor layer;
On described the first semiconductor layer exposing, form the 3rd semiconductor layer, the upper surface of described the 3rd semiconductor layer is lower than the upper surface of the described first hard mask, to expose the sidewall that is connected to described opposite flank in the described first hard mask, described the second semiconductor layer is different from described the first semiconductor layer and/or described the 3rd semiconductor layer material.
7. method according to claim 1, is characterized in that, the step of removing described the 3rd semiconductor layer of part comprises:
On described the 3rd semiconductor layer exposing, form heterogeneous district, described heterogeneous district material is different with described the 3rd semiconductor layer material from described the second semiconductor layer material;
Described the second semiconductor layer of take is mask, removes described heterogeneous district, and in described normal to a surface direction, described the second semiconductor layer is run through in described heterogeneous district.
8. method according to claim 7, is characterized in that: with oxidation technology, form described heterogeneous district.
9. method according to claim 1, is characterized in that, also comprises: carry out annealing operation.
10. method according to claim 9, is characterized in that: at H
2or under He atmosphere, carry out described annealing operation.
11. methods according to claim 1, is characterized in that: when described the first semiconductor layer material is silicon or doped silicon, described the second semiconductor layer is doping or unadulterated polysilicon or amorphous silicon, and described the 3rd semiconductor layer is silicon or doped silicon.
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| CN1805152A (en) * | 2004-09-07 | 2006-07-19 | 三星电子株式会社 | Field effect transistor (FET) having wire channels and method of fabricating the same |
| CN1855390A (en) * | 2005-03-24 | 2006-11-01 | 三星电子株式会社 | Semiconductor device having a round-shaped nano-wire transistor channel and method of manufacturing same |
| CN1893079A (en) * | 2005-06-28 | 2007-01-10 | 三星电子株式会社 | CMOS device, method of manufacturing the same, and memory including cmos device |
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| CN1805152A (en) * | 2004-09-07 | 2006-07-19 | 三星电子株式会社 | Field effect transistor (FET) having wire channels and method of fabricating the same |
| CN1855390A (en) * | 2005-03-24 | 2006-11-01 | 三星电子株式会社 | Semiconductor device having a round-shaped nano-wire transistor channel and method of manufacturing same |
| CN1893079A (en) * | 2005-06-28 | 2007-01-10 | 三星电子株式会社 | CMOS device, method of manufacturing the same, and memory including cmos device |
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