CN102442636B - Semiconductor structure with lamella defined by singulation trench - Google Patents
Semiconductor structure with lamella defined by singulation trench Download PDFInfo
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- CN102442636B CN102442636B CN201110372606.4A CN201110372606A CN102442636B CN 102442636 B CN102442636 B CN 102442636B CN 201110372606 A CN201110372606 A CN 201110372606A CN 102442636 B CN102442636 B CN 102442636B
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Abstract
A method for fabricating a semiconductor structure includes etching a first opening into a substrate; etching a chip singulation trench into the substrate to define a lamella between the first opening and the chip singulation trench; fabricating a sense element for sensing a deflection of the lamella; and singulating the semiconductor structure at the chip singulation trench.
Description
Technical field
The present invention relates to semiconductor technology, particularly semiconductor fabrication.
Background technology
the cross reference of related application
The application is the part continuation application that on September 11st, 2008 submits to, serial number is the application of 12/208,897.The content of this earlier application is bonded to this with for referencial use.
It is mutual that many application in microelectronics domain not only need to carry out with environment electricity, and need and environment carries out the machinery of a certain kind, thermodynamic (al), fluid dynamic, chemical, radiation or other mutual.Examples of these application can in the field of sensor device, find in field of MEMS (MEMS) etc.Mechanical force, pressure, temperature, chemical substance, physical quantity etc. and the private part of semiconductor structure carry out mutual to produce the effect expected, such as specific voltage or electric capacity, and it is the function of applied physical quantity.
The example of pressure sensor will illustrate the technological accumulation and inheritance carrying out the type of similar application alternately for needs and environment in representational mode.Pressure sensor is usually used to the pressure measuring liquid or gas (such as air).Pressure sensor usually provide based on by pressure sensor senses to pressure and the output signal changed.The pressure sensor of one type comprises coupling or is bonded to the individual pressure sensors of sensor surface, such as special IC (ASIC).The pressure sensor of another kind of type is pressure diaphragm capsule (capsule) (such as polysilicon films) integrated with the sensor circuit of such as ASIC and so on during production line back segment (BEOL) technique.Pressure usually be parallel to semiconductor structure substrate first type surface direction on the thin slice (lamella) of semiconductor structure that extends carry out alternately.Near one of thin slice first type surface being usually located at substrate.Therefore, the first type surface needs comprising thin slice are located, and make this first type surface towards its pressure by measured volume.
In interchangeable design, thin slice has been moved into the inside of substrate.Pressure is conducted to thin slice by pressure channel (channel) usually, and this pressure channel can have more or less complicated shape, and this depends on the entrance of pressure channel relative to thin slice by the position of locating.
Summary of the invention
One embodiment of the present of invention propose a kind of method for the manufacture of semiconductor structure, and the method comprises: etch the first opening in the substrate; Etch chip scribe line (singulation trench) in the substrate to limit the thin slice between the first opening and chip scribe line; Manufacture the sensing element of the deflection for sensing thin slice; And at chip scribe line place, scribing is carried out to semiconductor structure.
Accompanying drawing explanation
Accompanying drawing is included to provide the further understanding to embodiment, and accompanying drawing is incorporated in the present specification and forms the part of this description.Accompanying drawing illustrates embodiment, and is used for together with the description explaining the principle of embodiment.Many expection advantages of other embodiments and embodiment will easily be realized, because by reference to following detailed description, they become better understood.The element of accompanying drawing relative to each other not necessarily in proportion.Similar Reference numeral represents corresponding similar portions.
Fig. 1 illustrates the diagrammatic vertical cross section of the semiconductor structure according to instruction disclosed herein.
Fig. 2 illustrates the diagrammatic horizontal cross section of the semiconductor structure according to instruction disclosed herein.
Fig. 3 illustrates the partial view of the schematic cross-section of semiconductor structure.
Fig. 4 A and Fig. 4 B illustrates chamber and has the level cross-sectionn of two modification of internal structure in this chamber.
Fig. 5 illustrates the perspective view of the modification of internal structure.
Fig. 6 A to 6D illustrate depositing operation each stage and subsequently to the etching of Semiconductor substrate.
Fig. 7 A to 7F illustrates the process sequence for carrying out electric insulation to presser sensor structure.
Fig. 8 illustrates the sensor construction using semiconductor structure to implement.
Fig. 9 illustrates the cross section of the substrate with conical cross-section chamber.
Figure 10 illustrates the cross section of the semiconductor structure of the cone-shaped slice had between chamber and chamber.
Figure 11 A to 11D illustrates each stage of an embodiment of the manufacturing process of semiconductor structure.
Figure 12 A to 12D illustrates each stage of another embodiment of the manufacturing process of semiconductor structure.
Figure 13 A illustrates the first scanning electron microscope image of the section of the semiconductor structure obtained at the intermediate steps place of the manufacturing process of Figure 11 A-11D or Figure 12 A-12D.
Figure 13 B illustrates the second scanning electron microscope image of the section of the semiconductor structure obtained at the intermediate steps place of the manufacture method of Figure 11 A-11D or Figure 12 A-12D.
Figure 14 illustrates the cross section of the Semiconductor substrate of another combination wherein implementing feature disclosed in some.
Figure 15 illustrates the part comprising the semiconductor wafer of several semiconductor structure before the scribing process for obtaining single semiconductor structure.
Detailed description of the invention
In the following detailed description, done reference to accompanying drawing, described accompanying drawing forms a part for this detailed description, and is wherein shown can be put into practice specific embodiments of the invention by explanation.In this respect, such as the directional terminology of " top " and " bottom ", " front " and " afterwards ", " leading ", " hangover " etc. and so on is used with reference to the orientation of the figure be just described.Because the parts of embodiment can be located with many different orientations, therefore directional terminology be used to illustrate object and restrictive anything but.Should be appreciated that can utilize other embodiments and can carry out structure or logic change and do not depart from the scope of the present invention.Therefore, below describe in detail and should not be regarded as limited significance, and scope of the present invention is limited by claims.
Should be appreciated that the feature of various exemplary embodiment described herein can combine mutually, unless specifically stated otherwise.
In the comparatively early stage of technology development process causing instruction disclosed herein, have developed the pressure sensor with vertical design, namely thin slice extends on the direction of the first type surface perpendicular with substrate.Different from compact design, this design also provides to be selected to provide the differential pressure transducer with one or more pressure channels that can very freely configure.For the application in the environment seriously polluted by liquid and analog, may there is the risk that the pressure channel of pressure sensor and other structures become permanent blockage, this depends on the use to pressure sensor.As the result of blocking, the change by the change of the dielectric situation between the presser sensor plate that is read out and capacitance signal therefore may be there is.It is envisaged that, compared with in the environment of of low pollution, lower and lessly require that the application of specification (specification) can utilize the pressure sensor with vertical design to serve for chemically inert requirement.But, especially at automotive field, require normally strict (comprising, the robustness about them is tested for different chemical material by pressure sensor).It is possible that by the skilled use to the auxiliary layer of the mode work to repel liquid, it may be attainable for meeting these high requests.But the application for these high requests provides interchangeable, the solution of robust also exists great interest.
Instructions more disclosed herein propose to produce the sensor element being parallel to chip edge, and pressure channel can be exempted together.Fig. 1 to 3 illustrates corresponding sensor element.
Fig. 1 illustrates the diagrammatic vertical cross section of semiconductor structure.Substrate 102 has the first first type surface 103 and the second first type surface 104.In addition, substrate 102 has the chamber 152 be formed in wherein.Chamber 152 is delimited by the wall of substrate 102 on the left of it, and is delimited by thin slice 151 on the right side of it, and thin slice 151 is actually the part of substrate 102 and normally its part.Thin slice 151 is thin that to be enough to when such as, being brought out by the pressure P (or the physical quantity of another kind of type, power) putting on thin slice 151 from outside be deflectable.At top, chamber 152 is capped material 155 and closes, and therefore provides reference pressure volume.The opposite wall of thin slice 151 and substrate 102 forms capacitor by two condenser armatures or plate region 170, and it is represented as dash line by way of illustration.Due to the deflection of thin slice 151, the distance between condenser armature 170 as pressure P function and change.The change of the distance between condenser armature 170 causes the change of the electric capacity of capacitor.Thin slice 151 is close to be realized the border of the chip of semiconductor structure thereon and locates, and is actually a part for the chip edge 159 of semiconductor structure.
In the enforcement shown in Fig. 1, substrate 102 comprises several layer 182 and 183.These layers 182,183 serve as electric insulation layer.Such as, layer 182 and 183 can be the layer with opposite dopant type, and such as layer 182 is p+ type doped layer and layer 183 is n+ type doped layers.The structure formed by layer 182 and 183 produces pn knot in the substrate.In interchangeable enforcement, the other types of at least one electric insulation made in layer 182,183 can be used, such as layer 182,183 (one of) in inject oxygen atom and with after annealing to produce silica.Note, one independent in layer 182,183 may be just much of that.Chamber 152 is crossing with at least one in layer 182,183.Therefore, in the position that the remainder of thin slice and substrate 102 merges, thin slice 151 is relative to the remainder electric insulation of substrate 102.Usually, chamber 152 be also positioned at the wall of narrow side close, i.e. (not shown in figure 1) above and below figure plane.These walls also need electric insulation usually, to make thin slice 151 completely and the remainder electric insulation of substrate 102.Cladding material 155 is also electric insulation usually.
Above the first first type surface 103 of substrate 102, articulamentum 180 is provided, and via articulamentum 180, the electrode of the capacitor that thin slice 151 and opposite wall are formed can be connected to evaluation circuits.Element indicated by Reference numeral 181 belongs to one or more metal level.
This semiconductor structure comprises circuit layer 190,191 further, such as, be used to implement cmos circuit.Circuit layer 190,191 is positioned at the distance I from chip edge 159
dISTANCEplace.Such as, distance I
dISTANCEfrom in the scope of approximate 1 μm to 5 μm, such as 2 μm, 3 μm or 4 μm.Distance I
dISTANCEalso 5 μm can be greater than, such as 7 μm, 10 μm or 12 μm.This distance I
dISTANCEthere is provided surplus to avoid the damage to potential fragile circuit layer caused in chip edge place process chip (particularly performing chip scribing at chip edge place).Element 181 for being electrically connected condenser armature 170 and circuit layer 190,191 (in particular for being connected that of thin slice 151) can be designed to enough robusts, to tolerate the Several Typical Load observed when processing semiconductor structure.
The design without pressure channel is very suitable for being used in adverse circumstances, because do not have chamber to be directly exposed to environment.In addition, apply the position of external pressure and be provided at chip edge place, thus cause being parallel to encapsulation compacter compared with the pressure sensor of the thin slice that the direction of the first type surface of substrate 102 extends with having.And, comprise with the pressure sensor of the upright thin slice (namely perpendicular to first type surface) of the coincident of semiconductor chip compared with the above-mentioned device with horizontal sheet or pressure sensing element, originally can manufacture with lower one-tenth.
For total capacitance and the simple method of estimation display of the sensitivity that is associated, the enforcement described is in the scope of current scale (current dimensioning).Depend on the width in the chamber 152 be closed, capacitance can reach the every micro flakes length (length of the chip edge 159 namely related to) of about 1 to 10 flying method (fF), and wherein chip edge 159 belongs to such as asic chip.The total length of chip edge 159 is such as 2mm, and total capacitance can reach 2 pico farads.The absolute change of electric capacity largely depends on the size of thin slice 151.Lamella height 10 μm and sheet thickness is between 200nm and 300nm time, the change of electric capacity can reach up to 10% every 1 bar pressure change, namely a few flying method.Total capacitance and sensitivity adjust by selecting etch depth and sheet thickness.The size in the size of thin slice (thickness, length, highly, etc.) and chamber (width, length, etc.) also can adjust according to such as desired measurement category and sensitivity.
Another theme is chip scribing.Likely be used for the groove in chamber in etching while, many grooves are firmly got in etching.This firmly gets many grooves in an orbiting manner as the border of whole active area chip area, and specifies crack edge or chip edge.Several vicinity, adjacent chip carrys out scribing by the technology of such as " stealthy stripping and slicing " and so on or other suitable technology.Depend on the design around etching bath, likely just can get along without the need to auxiliary process during chip scribing.
According to instruction disclosed herein, presser sensor (or power is responsive, it is responsive to accelerate, etc.) structure is positioned at chip edge 159 place.Presser sensor thin slice 151 delimit chip boundary.Crack edge or chip scribing edge can via around darker groove limit.
Fig. 2 illustrates schematic partial top view or the plan view of the level cross-sectionn of the semiconductor structure according to instructions more disclosed herein.Several first chamber 252 is formed in substrate 102.Chamber 252 is configured to the circumferential groove around internal structure 253.In the embodiment shown in Figure 2, internal structure 253 is formed to have the inner flat pipe strengthening wall and inner chamber 254.In other embodiments, this internal structure can have different configuration.Demarcated by thin slice 251 in side in first chamber 252.First chamber 252 is separated with chip scribe line 270 by thin slice 251.Chip scribe line 270 usually has larger width and the larger degree of depth compared with the first chamber 252.
Internal structure 253 and substrate 102, particularly thin slice 251, form capacitor.Thin slice serves as the first electrode of capacitor, and internal structure 253 serves as the second electrode.In one embodiment, internal structure 253 is not positioned at the center in the first chamber 252 of its correspondence.Between internal structure 253 and thin slice 251, define capacitor gap around the first chamber 252, and there is the width less than other three parts in the first chamber in an embodiment.The electric capacity C of plate condenser can be similar to by relational expression C=ε A/d, and wherein ε is the dielectric constant of the material between plate, and A is the area of plate, and d is two plates distances each other.Due to the distance d inverse correlation of electric capacity and two plates, so the narrow gap portion of capacitor, the part of namely being delimited by thin slice 251, the contribution for electric capacity is maximum.As mentioned above, thin slice 251 deflects when being subject to the external impact of such as pressure or power.This causes its width of space change between thin slice 251 and internal structure 253, and this causes again the electric capacity of capacitor to change.Internal structure 253 keeps relatively fixing during pressure change, and this part is due to its shape and strengthens wall.The part of the substrate 102 that this is applicable to equally substantially below the first chamber 252 (" in ... below " refers to the direction relative to figure).Therefore, during pressure change, only thin slice 251 stands significant deflection or distortion.
Fig. 2 indicates multiple size, and it is adjustable to the working range and the sensitivity that obtain expectation.The symbol of specific dimensions used in following table indicator diagram 2, its implication, exemplary range and example values.
Fig. 3 illustrates the details of Fig. 2.Electric contacts or device 360,361 are provided such as, to be electrically connected thin slice 251 and internal structure 253 and evaluation circuits, capacitance measurement circuit (not shown).Such as, electrical connecting element or device 360,361 may extend to articulamentum 180 and the metal level 181 of Fig. 1.
Electric contacts or device 360,361 be positioned at distance chip scribe line 270 a certain distance, the part place of internal structure 253 and substrate 102.Especially, thin slice 251 does not directly contact with electric contacts or device 361, but via the inwall of substrate 102, this internal wall separates opens two the first chambeies 252.In one embodiment, the part place relative with thin slice 251 of internal structure 253 is positioned at for the contact element of internal structure or device 360.
Be enhanced by some in following aspect for the manufacture of the method for semiconductor structure and semiconductor structure self.
The etching of the first opening (chamber) and the etching of chip scribe line can perform simultaneously.Usually, identical lithography step is used to restriction first opening and chip scribe line.Chip scribe line has the width larger than the first opening usually.Depend on used etching technique, the width also influence depth (large width causes the larger degree of depth, and vice versa) of groove to be etched.
The form of the first opening can be the circumferential groove around internal structure.In order to make internal structure electric insulation, the bottom of internal structure or " footing " are insulated just much of that.This realizes by the insulating barrier be present in substrate with the degree of depth expected.In one embodiment, without the need to providing insulating barrier and/or material between the sidewall of the internal structure relative to substrate, because circumferential groove serves as insulator.
The method can comprise internally structure further provides electrical contact for electrical connection internal structure and sensing element.
Electrical contact can be positioned at the part place relative with chip scribe line of internal structure.This means electrical contact relatively away from scribe line, this has been shifted out the region may standing mechanical stress, especially, during scribing process and at the duration of work of semiconductor structure, now such as pressure collision is on the side of the semiconductor chip at the region place that used to be in and scribe line close with thin slice.
Before etching the first opening in the substrate, the method can comprise further: on the first type surface of substrate, produce electric insulation layer; And on electric insulation layer the skin of deposition substrate material.Outer field deposition causes substrate to become thicker usually.Then the etching of the first opening and chip scribe line can be carried out from outer field surface, and at least extends downwardly into electric insulation layer.These method steps can with other features disclosed herein (such as by circumferential groove around internal structure) there is cooperative effect.
The method can comprise further: the wall applying lining (1iner) material to the first opening; The first opening is filled with polysilicon; And be etched to small part lining material, thus between polysilicon and at least part of wall of the first opening leaving gap.These actions define for the replaceable option of one of electrode making capacitor relative to insulated substrate.Lining material is generally insulating materials, such as, in oxide liner.Also can imagine the wall applying several layer to the first opening be made up of different lining materials, each layer has certain desired effects.When polysilicon be formed such as substantially elongated or flat structure (such as thin slice or laminated structure) time, can at two of a flat structure first type surface (it is different from the first type surface of substrate usually) place equal (at least in part) remove lining material.Replace, be retained in the lining material of narrow side or edge.Therefore, substantially flat structure is only connected to substrate in end, also may in some selection section offices at first type surface place, and usually in bottom.In one embodiment, the parasitic capacitance between polysilicon and the surrounding wall of substrate is this reduced.
At least one had conical cross-section in first opening and thin slice.Contrary with rectangle or uniform crosssection, conical cross-section realizes the wide-measuring range of such as pressure sensor, maintains high sensitivity in the measurement category (scope of normally little value) of part simultaneously.Therefore, be that sensor construction provides progressive characteristic according to the conical cross-section of an embodiment.
According to some instructions disclosed herein, a kind of semiconductor structure comprises: the first chamber in Semiconductor substrate; With the chip scribing edge partially overlapped of the circumference (circumference) of Semiconductor substrate, chip scribing edge and the first chamber define the thin slice between them; And sensing element, it is arranged to the deflection of sensing thin slice.
First chamber can comprise the circumferential groove around the internal structure being positioned at the first chamber.
Semiconductor structure can comprise electrical contact to internal structure further for electrical connection internal structure and sensing element.
Electrical contact can be positioned at the part place relative with scribe line of internal structure.
Internal structure can comprise the electric insulation layer for making internal structure insulate relative to the remainder of substrate.
Semiconductor structure can comprise further: be arranged in the polysilicon structure in the first chamber; Lining material layer between the wall in polysilicon structure and the first chamber; And the gap between the wall in polysilicon structure and the first chamber, between the wall not being in polysilicon structure and the first chamber at gap location lining material.
At least one had conical cross-section in first chamber and thin slice.
When concern has the semiconductor structure of circumferential groove, a kind of method of this semiconductor structure that provides comprises the circumferential groove formed in the substrate around internal structure.At least one wall limited by circumferential groove comprises thin slice.The method also comprises the part place of the internal structure being substrate place support internal structure, makes internal structure relative to insulated substrate.The circumferential groove around internal structure is provided to reduce the region needing to provide electric insulation between internal structure and substrate.Internal structure can be used as the electrode of such as capacitor subsequently.The method causes semiconductor structure to comprise the first chamber in Semiconductor substrate and Semiconductor substrate usually, and the first chamber comprises the circumferential groove around the internal structure in the first chamber, and internal structure is relative to the sidewall electric insulation in the first chamber.The method can comprise manufacture further for sensing the sensing element of the deflection on thin slice and provide connection between internal structure and sensing element.Sensing element such as can assess the temporary charge reservoir value between internal structure and substrate.The sensing element of another kind of type can based on assessment piezo-electric effect.
According to instructions more disclosed herein, a kind of method for the manufacture of semiconductor structure comprises: etch the first opening in the substrate; Etch the second opening in the substrate to limit the thin slice between the first opening and the second opening; Manufacture the sensing element for sensing the deflection on thin slice; And at least one closing in the first opening and the second opening.At least one in first chamber and thin slice has conical cross-section.Therefore, the semiconductor obtained comprises: the first chamber in Semiconductor substrate; The second chamber in Semiconductor substrate, the second chamber is to atmosphere opening and limit the first thin slice between the first chamber and the second chamber; And sensing element, it is arranged to the deflection on sensing first thin slice.In addition, at least one in the first chamber and thin slice has conical cross-section.
According to instructions more disclosed herein, a kind of method for the manufacture of semiconductor structure comprises: etch the first opening in the substrate; Apply the wall of lining material to the first opening; The first opening is filled with polysilicon; Be etched to small part lining material, thus between polysilicon and at least part of wall of the first opening leaving gap.The optional aspect of the method comprises:
The method can comprise further: etch the second opening in the substrate; The first opening and the second opening is sealed with encapsulant after applying lining material; And remove at least part of encapsulant of the first opening so that or make it possible to etching lining material at least partially.
The method removes at least part of encapsulant of the second opening after can being included in etching lining material further.
It is recessed that the method performs polysilicon after can being included in further and filling the first opening with polysilicon.
Enable obtained semiconductor structure measure (capacitance-voltage) by such as C (V) based on the method for filling one or more groove with polysilicon and carry out online (inline) test.In addition, polysilicon structure formed two or more electrode for capacitors in the lump by lining material relative to structural insulation, as long as lining material is insulating materials.
The semiconductor structure obtained comprises: the first chamber in Semiconductor substrate; Be arranged in the polysilicon structure in the first chamber; Wall in polysilicon structure and the first chamber at least part of between lining material layer; And the gap between polysilicon structure and the wall in the first chamber, between the wall not being in polysilicon structure and the first chamber at gap location lining material.Optional aspect comprises:
Second chamber; Deflected thin slice between first chamber and the second chamber; And for the sensing element of the deflection that senses thin slice.
For sealing the encapsulant in the first chamber.
Between the part that lining material can be present in the wall in the first chamber and polysilicon, for supporting polysilicon and making polysilicon and substrate electric insulation.
The part that there is the wall of lining material can be relative with gap.
The disclosure also teach that a kind of method manufacturing semiconductor structure, and the method comprises: produce electric insulation layer at the first first type surface place of Semiconductor substrate; Electric insulation layer provides semi-conducting material; First opening is provided in provided semi-conducting material and Semiconductor substrate; And in provided semi-conducting material and Semiconductor substrate, etch the second opening to limit the thin slice between the first opening and the second opening.The method can comprise further: manufacture the sensing element for sensing the deflection on thin slice.These two etching actions can perform during the single step of technique.Semiconductor substrate can utilize the first doping type to adulterate.Then the generation of electric insulation layer can comprise the doping of the first first type surface utilizing the second doping type to Semiconductor substrate.Another option is, implants or otherwise inject such as oxygen atom and perform annealing steps to produce oxide layer with the first first type surface place in Semiconductor substrate at the first first type surface place of Semiconductor substrate.Supplement providing of semi-conducting material to realize by epitaxy technique or Venezia technique.
Corresponding semiconductor structure comprises: Semiconductor substrate, and it comprises base substrate, deposition or supplements (top) layer and the electric insulation layer between base substrate and deposition (or supplementing) layer.First chamber is disposed in deposition (or supplementing) layer, electric insulation layer and base substrate; And second chamber be disposed in deposition (or supplement) layer, wherein the second chamber is to atmosphere opening and the first thin slice limited between the first chamber and the second chamber, and the first thin slice is crossing with electric insulation layer.Semiconductor also can comprise the sensing element of the deflection being configured for sensing first thin slice.Base substrate and deposition (supplementing) layer can be the first doping type, and electric insulation layer can be the second doping type, and the second doping type is contrary with the first doping type in polarity.As in the context of this method, electric insulation layer may be obtained by annealing process.
Fig. 4 A and 4B illustrates top view or the plan view of the cross section in chamber, and its midship section is arranged essentially parallel to the first type surface 103,104,203,204 of substrate 102,202.With reference to Fig. 4 A, substrate 202 comprises three similar chambeies or groove 412.The form in chamber 412 be around internal structure 413 around chamber.Internal structure 413 can above plan and/or the place at below place be connected with substrate 202.The sidewall of internal structure 413 is represented by its cross section in figures 4 a and 4b, and described sidewall does not contact with the sidewall in chamber 412 usually, as can seeing in Fig. 4 A and 4B.Therefore, internal structure 413 can be considered in chamber 412 is independently substantially.For the purpose of this disclosure, expressing " independently " can comprise internal structure 413 and be connected with substrate 202 at its two end (normally in top and bottom end).Expressing " independently " also can comprise internal structure 413 and be connected with substrate 202 at single end, no matter and the spatial relationship of connection between internal structure 413 and substrate 202 (at top, bottom or sidepiece).
Fig. 4 category-B is similar to Fig. 4 A, but chamber 442 is greater than chamber 412.Internal structure 443 is also greater than internal structure 413, and has different configurations.
In both Fig. 4 A and 4B, internal structure 413,443 is all configured to have the pipe of reinforcement to improve the stability of internal structure 413,443.Especially, when internal structure 413,443 is connected to substrate 202 at its single end, the enough stability of internal structure 413,443 is favourable.Configuration as the pipe with reinforcement or enhancing wall can provide the stability of required rank.
Internal structure 413,443 can be used as one of electrode of such as capacitor.With reference to Fig. 4 A, the lower chamber 412 in three shown chambeies can adjacent sidewall or thin slice 411.Thin slice 411 can be used as the function of the pressure differential between the volume on the opposite side of chamber 412 and thin slice 411 and deflects.Therefore, its width of the space change between thin slice 411 and internal structure 413, thus the capacitance variations causing the capacitor formed by thin slice 411 and internal structure 413.Because internal structure 413 is relatively stable and/or rigidity, so the deflection of pressure differential or thin slice 411 does not all cause internal structure 413 to move in a substantial way.When internal structure 413,443 is used as electrode or the analog of capacitor, usually need internal structure 413,443 with electrical connecting element or device 460 (being schematically illustrated as the position residing for being electrically connected) are provided between certain evaluation circuits.Thin slice 411,441 is usual close to large chamber 220, or even close to the edge of semiconductor chip.Substrate 202 large chamber or chip edge vicinity relatively fragile; Namely substrate may reduce rigidity in this region.Therefore, electrical connecting element or device 460 are placed on from a certain distance of thin slice 411,441 may be favourable.Especially for the internal structure 434 shown in Fig. 4 B, it is enough far away that electrical connecting element or device 460 can be provided as distance thin slice 441, this is because internal structure 443 is relatively large.Such as, arrangements of electric connection can be provided the position in figure 4b indicated by circle.
Fig. 5 illustrates the perspective view of the embodiment of the internal structure 543 similar with the internal structure 443 shown in Fig. 4 B.Be used as the replacement of relative rigid structure as to above-mentioned, the internal structure 543 shown in Fig. 5 also can be configured to provide deflector in the side-walls of internal structure 543.In order to this point is described, Fig. 5 illustrates the degree that each several part of internal structure deflects when the pressure (or pressure differential) by 1 bar brings out.Fig. 5 illustrates the result that FEM model (FEM) emulates.The minimum deflection gone out by FEM simulation calculation is 0.1nm (being indicated by wide hacures in figure), and maximum deflection is 4.6nm (being indicated by cross-hauling).Other deflection of intergrade usually in an alternating fashion, is indicated by the shadow region of non-hatched area or different narrow degree.In that region, tilt value can be depending on itself and the distance between minimum deflection region and maximum deflection region and is observed.Internal structure shown in Fig. 4 A, 4B and 5 is configured such that, they provide enough technological abilities via enough rigidity.At the duration of work of time after a while, there is enough large deflection in the part of the length of thin slice, as can see with the part place shown in cross-hauling, wherein emulated the deflection predicting 4.6nm by FEM.Enough large deflection ensure that the sensitivity expecting rank.Note, internal structure 543 does not need distal opening at an upper portion thereof, as shown in Figure 5.It is also possible that internal structure 543 endcapped at an upper portion thereof, thus form four enclosed cavities (or enclosed cavity of any other quantity).When applying pressure to be measured from the circumferential groove around internal structure 543, enclosed cavity can bear the role of pressure reference volume subsequently.Also possible, circumferential groove represents reference volume, and is therefore closed by cladding material.Pressure to be measured is applied to a four or more chamber of serving as pressure channel subsequently.
Fig. 6 A to 6D illustrates the four-stage of the technique that can provide electric insulation layer in Semiconductor substrate 602.Substrate 602 normally has the semi-conducting material of the basic doping of the first polarity (such as n-or p-).In a first step, substrate 602 utilizes opposite polarity to be doped to produce contra-doping layer 632 in surface.Subsequently, execution extension or Venezia technique to set up layer 634 on contra-doping layer 632.Fig. 6 D illustrates how multiple groove 612,670 has been etched in layer 634, contra-doping layer 632 and (original) substrate 602.At contra-doping layer 632 place by formation two pn knots, when applying voltage between the upper and lower first type surface at such as substrate 602, one of these two pn knots are in reversing mode usually.Because one of these two pn knots are in reversing mode, so contra-doping layer 632 serves as insulator.On the other hand, substrate 602 is made up of homogeneous material.Contra-doping layer 632 can have the electrical characteristics different from the remainder of substrate 602, but its chemical characteristic is identical substantially.Therefore, multiple groove 612 can be etched through whole three layers 634,632 and 602 by substantially the same mode, such as, by DT etch process.
Technique shown in Fig. 6 A to 6D can be performed before the method shown in Fig. 1,2A and 2B.Technique shown in Fig. 6 A to 6D also can combine with the layout around chamber and internal structure shown in Fig. 4 A, 4B and 5.With reference to figure 6D, can see, thin-walled comprises the part of the bottom electric insulation by contra-doping layer 632 with substrate 602.Especially, when groove is formed circumferential groove as shown in Figure 4 A, internal structure is electric insulation complete in the bottom of substrate 602 only by contra-doping layer 632.Therefore, without the need to taking addition thereto to realize the electric insulation of internal structure 413 (Fig. 4 A).
Inventor have developed in the past the pressure sensor (as depicted in figure 8 and following explained such) with formation arranged perpendicular in the semiconductor substrate.For some in these pressure sensors, in the groove with very big depth-to-width ratio, apply doping becomes a challenge, and this doping is used for providing electric insulation for presser sensor thin slice.In addition, the transverse direction doping of opposite polarity needs the end being provided at groove.If possible, for this process sequence adopted should be maskless and robust.
A kind of proposal comprises carries out thin slice doping by arsenic glass coating, and injects by two angled boron the electric insulation providing thin slice in bottom and side subsequently.For making the process sequence of presser sensor structure electric insulation shown in Fig. 7 A to 7F, and comprise the following steps:
Deposition is used for hard mask heap (Fig. 7 A) of trench etch
Etching bath and remove hard mask heap (nitration case is retained in surface and stops that in affected position following arsenic glass coating and boron inject) (Fig. 7 B)
Apply arsenic glass and drive in arsenic (Fig. 7 C)
Inject boron and activated boron (Fig. 7 D)
Depositing silicon oxynitride thing (thin pad oxide under), recessed nitrogen oxide (nitride on surface is removed simultaneously) (Fig. 7 E)
Metallization (Fig. 7 F)
In fig. 7d, inject boron relative to plan with miter angle, and revolve turnback second time and inject boron, to guarantee the doping of opposite polarity of bottom (layer at the At The Height indicated by " p+ ") and groove end simultaneously.In injection device, typical Adjustment precision is about 1 degree.Depend on the depth-to-width ratio of groove, require higher precision, thus such as perform injection several times to succeed.This can cause the relatively large change of implantation dosage.Repeatedly inject although perform, realize the doping of sufficiently high opposite polarity and be still challenging to isolate thin slice.
According to instruction disclosed herein, the combination of structural modification and integrated modification is proposed, or for making the new doping sequence of structure electric insulation.First, carry out adaptive presser sensor structure in the mode can saving the insulation at leaf ends place, its result is such as found in Fig. 4 A, 4B and 5.Angled injection is no longer needed to adulterate to leaf ends.In the bottom of groove, internal structure is adulterated and be just enough to fully make pressure thin slice and insulated substrate.Which introduce new integrated option.Simple modification is, epitaxial substrate in the following manner: the doping that even just can manufacture opposite polarity before etching bath on wafer.This sequence is such as sketched out in Fig. 6 A to 6D.
The dosage injected can relatively accurately control, and realizes sufficiently high doping by several times or even bolus injection.
Instruction disclosed herein can combine with silicon-on-insulator (SOI) technology or be realized by it.This technology refers to and uses stacked silicon-on-insulator-silicon substrate to be substituted in silicon substrate conventional in semiconductor manufacturing (especially microelectronics), to reduce parasitic device capacitance and thus to improve performance.Insulator normally silica or be sapphire sometimes.The insulator layer of soi structure applies by technique known in SOI technology field or produces, instead of the doping such as performed before Fig. 6 B.
Also imaginabale right and wrong are angularly injected in the bottom of groove in one embodiment.This causes simpler technique compared with angled injection usually.Depend on the degree of depth of structure, the injection of superenergy is also possible, utilizes high-temperature annealing step, and this has sufficiently disperseed doped chemical and has activated their (such as 3MeV phosphorus inject and lower 240 minutes at 1200 degrees Celsius).A rear combination is by more cheap a little than the sequence with epitaxial step as set forth above.
Fig. 8 illustrates the cross section of the semiconductor structure as pressure sensor.Chamber 706 is pressure channel, and chamber 707 is the balancing gate pits being used as tonometric reference.Thin slice 711 is provided between pressure channel 706 and balancing gate pit 707.Two thin slices 711 of confining pressure room 707 can deflect under the impact of pressure differential between pressure channel 706 and balancing gate pit 707.Left thin slice forms the first electrode of capacitor, and right thin slice 711 forms the second electrode of capacitor, and balancing gate pit 707 forms the gap of capacitor.In order to conduct electricity, each of serving as two thin slices 711 of electrode for capacitors is at least n in the surface of thin slice
+doping.These two electrodes are electrically connected to the evaluation circuits be provided in one or more layer 730.Structure shown in Fig. 8 also has the second first type surface 704, and pressure channel 706 is open towards the second first type surface 704.In fig. 8, the width in the gap of capacitor is indicated by alphabetical s, and the width of thin slice 711 is indicated by alphabetical w.In order to make thin slice 711 electrically insulated from one another in its bottom, provide p
+doped portion, this p
+doped portion is to serve as insulating barrier with the mode similar about the mode described in Fig. 6 A to 6D.
Being configured in current available model of (independently or be integrated in AISC) pressure sensor is normally very similar: chamber by thin slice unilaterally or many sides limit.Thin slice is exposed to external agency and deflects when outside pressure change to make it.This mechanical information is converted into the signal of telecommunication by piezo-resistive, capacitor or other suitable methods and further technique subsequently.
When capacitive character information is changed, thin slice forms the capacitor with the sidewall in the chamber relative with thin slice.In order to realize the high sensitivity of this layout, thin slice needs to be needed to be narrow by thinning and chamber.By this way, the large change of electrode distance relative to initial distance is achieved.Meanwhile, therefore the measurement category of this layout is limited, because once these two electrodes contact with each other, then the further increase of pressure no longer causes the change of capacitance signal.
This problem can be avoided by the producer of the pressure sensor based on electric capacity providing a series of different size (relative to sheet thickness and/or chamber width).User can be the sensor that the application choice of expection is suitable subsequently.Possible, need by adopting several sensor to detect in the pressure change of going up very on a large scale, each optimised for subrange in described sensor.Alternatively, single-sensor can cover gamut, but due to the use in more thickness sheet and/or wider chamber, its cost is lower sensitivity.
The limited problem of measurement category by thin slice is arranged as relative to offside the tapered relation of chamber sidewall instead of become parallel relation to solve.Alternatively, but thin slice self is shaped as taper.Replace as another, the combination of these modification can be used.There is provided conical cavity, thin slice or the two cause this layout, wherein the high sensitivity conversion of pressure signal can be observed in the first subrange, and in other subranges, keeps enough distances between thin slice and the wall of offside can detect much bigger force value.In other words, conical cavity, gap and/or thin slice can give the progressive sensitivity of sensor (little-> is highly sensitive for measured value, and vice versa).
For deep trouth etch process, the size and dimension of chamber (or etching bath) and thin slice (silicon mesa) limits by photoetching and technological parameter.Such as, the etching bath for having the thin slice of wedge-shaped cross-section obtains by photoetching.By controlling etch process, the wedge-shaped cross-section in vertical direction can be produced.In addition, etch depth changes along with the width of channel opening and technological parameter.Changing technological parameter at etching and allow more or less significantly effect, making to obtain the further free degree when being shaped to chamber and/or thin slice.
According to instruction disclosed herein, chamber and/or the thin slice of pressure sensor are arranged such that, the surface limiting the plate of capacitor is not parallel to each other mutually, but demonstrates the geometry of taper or wedge-like.Express " taper " and mean chamber or the vicissitudinous thickness of thin slice tool or width.The change of thickness or width is not limited to linear change, but also can adopt other forms of change, such as curve or stepping.
Fig. 9 illustrates the first modification, and wherein mask (not shown) defines the trapezoidal cross-section in chamber.Fig. 9 is the level cross-sectionn of the substrate be similar in Fig. 8 in the position indicated by VIII-VIII.
Figure 10 illustrates another modification, and wherein mask defines the trapezoidal cross-section of thin slice.Which chamber arrow in Fig. 9 and 10 indicates are open (comparing with Fig. 8) towards the dorsal part of the second first type surface 704.
Much further enforcement is possible.What such as do not describe in the drawings is that etch depth changes with chamber, and this is by combining the photoetching of Fig. 9 and the etch process strongly affected by well width (shallow region corresponds to narrow well width, and dark etching corresponds to larger well width) and obtain.In addition, without the need to increasing width linearly.
Figure 11 A to 11D illustrates and utilizes polysilicon to fill the four-stage of the method for the semiconductor structure of filling according to the some of them chamber that provides of instruction disclosed herein.As above relative to as described in Fig. 8, the pressure sensor with arranged perpendicular develop by some inventors.Except the configuration shown in Fig. 8, alternative embodiment also can utilize and change for tonometric capacitance signal.But in these alternative embodiments, one of plate of capacitor is polysilicon films, and by oxide and substrate electric isolution.This tool has the following advantages: the function of micro mechanical structure can be verified in the capacitance measurement as soon as possible by depending on voltage during manufacturing process.The testing scheme used make use of polysilicon films and bends this fact due to applied voltage.Therefore, measure (namely electric capacity is as the function of voltage) by C (V) and guarantee production control.
Above-mentioned testing scheme easily can not be applied to the pressure sensor such as shown in Fig. 8.Maximumly allow that blocking voltage depends on the one hand the doping content (diode breakdown) of its lower edge at thin slice, and the geometry being also subject to groove (defines passage length; Perforation) impact.In addition, the electric capacity of space charge region (SCR) changes along with the voltage applied.For typical physical dimension, the capacitance variations of about a few pico farad as the voltage change of ten volts result and occur.The change that the deflection of thin slice causes is similar to a little order of magnitude.Therefore, above-mentioned testing scheme is only applicable to limitation or is not even applicable to the embodiment with the similar shown in Fig. 8.But, expectation is measured by C (V) and carries out on-line testing.
According to instruction disclosed herein, in trench etch and after applying auxiliary layer (liner oxide), in limited groove, perform polysilicon fill.Polycrystalline silicon material is used as one of electrode for capacitors subsequently, normally to electrode, and another electrode namely except formed the electrode of (or support) by thin slice except.After polysilicon is recessed, from groove, etch away oxide in one-sided mode by lithography step, to form chamber between polysilicon electrode and thin slice.Therefore, the testing scheme provided above can be kept and be suitable for online C (V) to measure.
According to instruction disclosed herein, polycrystalline (silicon) electrode structure in deep trouth is proposed.Chamber is between polysilicon electrode and contiguous thin slice, and this chamber defines the distance of condenser armature.
The integrated multi-form of proposed design can be imagined.Figure 11 A to 11D illustrates and performs sequence for the manufacture of having insulation to first of the capacitive pressure sensor of electrode according to an embodiment.In Figure 11 A, deep trouth etch process has been used to etched groove 1112 in substrate 1102.Subsequently as visible in Figure 11 B, by 1116 inside being applied to groove 1112 in oxide liner.In oxide liner, 1116 form relatively uniform layer on the inwall of groove 1112, and are used as encapsulant with seal groove.Figure 11 B also illustrates, the capped material 1115 of groove 1112 is closed.One of action performed after the stage shown in Figure 11 B is some grooves 1112 of selective reopening.Figure 11 C illustrates, first and the 3rd groove be such as unlocked by the etch process based on photoetching.Once the groove limited is reopened, then perform polysilicon deposition, this causes producing polysilicon structure 1119 in the groove limited of multiple groove 1112.Perform polysilicon subsequently recessed to remove the polysilicon be deposited on cladding material 1115, and remove the upper part of the polysilicon in groove 1112.In addition, 1116 etched down to a certain degree of depth from groove 1112 in oxide liner.This makes polysilicon structure 1119 be independently substantially, is supported because it only (comprises the little low portion of the sidewall of polysilicon structure 1119) bottom it, not to locate in oxide liner 1116 etched bottom this.Therefore, polysilicon structure 1119 by circumferential groove institute around and with substrate 1102 electric isolution because 1116 normally electrically insulating materials in oxide liner.By using the circumferential groove around polysilicon structure, relatively low parasitic capacitance can be obtained between polysilicon structure and the wall of substrate.In the alternative of complete circumferential groove, likely retain lining material at the narrow side place of polysilicon structure to provide a certain structural stability.Figure 11 C illustrates the semiconductor structure of the state of mediating, wherein 1116 etched in oxide liner.In Figure 11 D, illustrate how limited groove 1112 is heavily closed, it uses the material identical with cladding material 1115 or another suitable material.Cladding material 1115 is selected as electric insulation usually, to avoid the formation of the electrical connection between the polysilicon structure 1119 of electrode and substrate 1102.After heavily closing the groove 1112 limited, perform chemically mechanical polishing (CMP) step (Figure 11 D).After the state shown in Figure 11 D, second and the 4th groove can be reopened to limit pressure channel, external pressure is conducted to thin slice 1121 by this pressure channel.Therefore, the groove not being filled polysilicon forms pressure entrance.Measuring-signal is picked using as the change capacitance between polysilicon films and substrate silicon plate.Can via in oxide liner 1116 thickness carry out the basic electric capacity of accurate adjustment.
Described structure can produce in interchangeable mode, makes pressure only detected in the side of polysilicon structure.Figure 12 A to 12D illustrates for the manufacture of having the possible embodiment of insulation to the corresponding process sequence of the one-sided capacitive pressure sensor of electrode.Figure 12 A corresponds essentially to Figure 11 B, and namely, groove 1112 is etched, 1116 inwalls being applied to groove in oxide liner, and cladding material 1115 has been deposited so that enclosed slot.Figure 12 B illustrates following state, and wherein cladding material 1115 has been partially removed to be exposed to some gaps being filled with in oxide liner 1116 between polysilicon structure 1119 and substrate 1102.Also polysilicon was performed recessed before the state that Figure 12 B describes.In fig. 12 c, in the oxide liner in the gap of exposure, 1116 is etched.By contrast, 1116 be retained in those gaps that still capped material 1115 covers, because cannot close to these gaps by stopping for the etchant removing in oxide liner 1116 in oxide liner.Select etchant with only dissolved oxygen compound lining 1116 and make cladding material and polysilicon structure 1119 substantially unaffected.Hydrofluoric acid can be used, such as buffered hydrofluoric acid, dilute hydrofluoric acid or concentrated hydrofluoric acid for this reason.By using hydrofluoric acid, realize between silicon and silicon nitride good selective.Silicon nitride can be used as etch stopper to protect around structure.
Figure 12 D corresponds to Figure 11 D substantially.Especially, in oxide liner, 1116 etched gaps are heavily closed again, and executed chemical-mechanical polishing step.Therefore, gap is defined between polysilicon structure 1119 and thin slice 1121.As described in the context of Figure 11 D, those grooves not being filled polysilicon between the stage shown in Figure 12 A and 12B can be reopened to be used as pressure channel.
Embodiment shown in Figure 12 A to 12D can use in conjunction with such as pressure sensor, and wherein thin slice is positioned close to the edge of chip as shown in Figures 1 to 3.Thin slice 1121 is configured to border thin slice or edge thin slice subsequently.The groove 1112 of the rightmost side can be dimensioned in this case as scribe line, namely has relatively large width and the degree of depth.
For the technique shown in Figure 12 A to 12D, by not being removed and 1116 stability guaranteeing polysilicon structure 1119 in the one-sided oxide liner therefore supporting polysilicon structure 1119.Therefore, even if polysilicon structure 1119 is very thin, also enough stability can be obtained.Except described lining material, other auxiliary layers (nitride liner in the chamber between polysilicon structure and thin slice, etc.) can be expected.
The process sequence described in order to key diagram 11A to 11D and 12A to 12D has been proved to be and has tested, and at least in part for some processing steps, Figure 13 A and 13B illustrates the structure results of SEM (SEM) photo form.Figure 13 A illustrates the groove being filled with polysilicon 1119.Figure 13 A illustrates the approximate state corresponding to the technique of the state that Figure 12 B describes.The top of silicon 1102 is performed recessed accurately.The 1116 thickness t with approximate 66nm in oxide liner
lINER, its scope is from about 64nm to 68nm.The value of 68nm is applicable to be deposited on the layer on substrate 1102.Figure 13 B illustrate groove 1312 close by groove closure 1340 after semiconductor structure.Therefore, Figure 13 B corresponds to Figure 11 B and Figure 12 A substantially.Thin slice 1321 also shows in Figure 13 B.The bright border of Figure 13 B middle slot 1312 to correspond in oxide liner 1316.
When by by C (V) measure perform in-circuit function test time or when electric capacity respond will be prevented from the dependence of different voltage time, the process sequence proposed in Figure 11 A to 11D and 12A to 12D is useful.The structure obtained is joint space-efficient equally, and only complicated a little than the comparatively Zao method being used for obtaining the structure shown in Fig. 8.
Figure 14 illustrates the combination of conical cavity 1312 and internal structure 1343.Conical cavity 1312 is separated with large chamber 1320 by thin slice 1311.As mentioned above, the measurement category of such as pressure sensor is expanded by using conical cavity.Internal structure 1343 is relative stiffness, and relatively easily realizes the electric insulation between internal structure 1343 and the remainder of substrate by the such as technique shown in Fig. 6 A to 6D.Electrical connection between internal structure 1343 and evaluation circuits (not shown) such as can be provided at the position indicated by circle 1360.By this way, electrical connection and thin slice 1311 are enough far away, deflect when this thin slice 1311 is arranged to the pressure change in large chamber 1320.The vicinity of high pressure potential in the deflection of thin slice 1311 and chamber 1320 can cause the mechanical stress on the substrate of the vicinity in thin slice 1311 and chamber 1320.The place that the end of the internal structure 1343 relative with thin slice 1311 is caused away from mechanical stress more or position.Therefore, electrical connection 1360 is more durable potentially.
Figure 15 illustrates how semiconductor structure 1400 can be disposed on wafer 1401.In a schematic way, semiconductor structure 1400 comprises chamber 1412, and this chamber 1412 can be enclosed cavity or open cavity.Chamber 1412 is positioned close to chip scribe line 1420, and chamber 1412 is separated with chip scribe line 1420 by only thin slice 1411.Towards the end of manufacturing process, semiconductor structure 1400 by chip scribe line 1420 place such as shown in dash line rectangle by scribing.As a result, chamber 1412 by the edge close to semiconductor structure 1400, such as, close to chip edge.Therefore, the role of such as pressure channel is born around the space of semiconductor structure 1400.When pressure sensor, fulfil the role of pressure channel without the need to extra chamber.Mountable semiconductor structure 1400, makes the chip edge near chamber 1412 be exposed to its pressure by measured medium.Chamber 1412 is used as reference volume.Chamber 1412 can to the opposite side of semiconductor structure 1400 or surface open, makes different pressure can be measured.
Embodiment provides low cost and is integrated in the sensor had on the one single chip of logical device.The embodiment of sensor uses CMOS manufacturing process to assemble.Limit sensor chamber and sensing element can be come for the sensitivity expected and working range.
Although illustrate at this and describe specific embodiment, but persons of ordinary skill in the art will recognize that multiple (ordinate) correctly and/or equivalent enforcement can be used for replacing shown and described specific embodiment and do not depart from the scope of the present invention.The application's intention covers any adaptation or the modification of these those specific embodiments discussed.
Claims (20)
1., for the manufacture of a method for semiconductor structure, described method comprises:
Etch the first opening in the substrate;
Chip scribe line is etched to be limited to the thin slice between described first opening and described chip scribe line in described substrate;
Manufacture the sensing element of the deflection for sensing described thin slice;
At described chip scribe line place, scribing is carried out to described semiconductor structure;
Apply the wall of lining material to described first opening;
Described first opening is filled with polysilicon; And
Be etched to lining material described in small part, thus between described polysilicon and at least part of described wall of described first opening leaving gap.
2. method according to claim 1, wherein, etches the first opening and performs with etching chip scribe line simultaneously.
3. method according to claim 1, wherein, described first opening comprises the circumferential groove around internal structure.
4. method according to claim 3, comprises further:
There is provided electrical contact for the described internal structure of electrical connection and described sensing element to described internal structure.
5. method according to claim 4, wherein, described electrical contact is positioned at the part place relative with described chip scribe line of described internal structure.
6. method according to claim 1, comprises further, before etching the first opening in the substrate:
The first type surface of described substrate produces electric insulation layer;
The skin of deposition substrate material on described electric insulation layer;
Wherein, the etching of described first opening and described chip scribe line is carried out and is at least extended to described electric insulation layer from described outer field surface.
7. method according to claim 1, wherein, at least one in described first opening and described thin slice has taper level cross-sectionn.
8. a semiconductor structure, comprising:
The first chamber in Semiconductor substrate;
With the chip scribing edge partially overlapped of the circumference of described Semiconductor substrate, described chip scribing edge and described first chamber define thin slice therebetween;
Sensing element, it is configured to the deflection sensing described thin slice;
Be arranged in the polysilicon structure in described first chamber;
Be arranged in the lining material layer between the wall in the part in described polysilicon structure and described first chamber; And
In the part of described lining material not between described polysilicon structure and the described wall in described first chamber, between described polysilicon structure and the described wall in described first chamber gap.
9. semiconductor structure according to claim 8, wherein, described first chamber comprises the circumferential groove around the internal structure being positioned at described first chamber.
10. semiconductor structure according to claim 9, comprises further:
To the electrical contact of described internal structure, for being electrically connected described internal structure and described sensing element.
11. semiconductor structures according to claim 10, wherein, described electrical contact is positioned at the part place relative with described scribing edge of described internal structure.
12. semiconductor structures according to claim 9, wherein, described internal structure comprises electric insulation layer and insulate for the remainder making described internal structure relative to described substrate.
13. semiconductor structures according to claim 8, wherein, at least one in described first chamber and described thin slice has taper level cross-sectionn.
14. 1 kinds of semiconductor structures, comprising:
The first chamber in Semiconductor substrate;
The second chamber in described Semiconductor substrate, described second chamber is to atmosphere opening and the first thin slice defined between described first chamber and described second chamber;
Sensing element, it is configured to sense the deflection on described first thin slice;
Wherein, at least one in described first chamber and described thin slice has taper level cross-sectionn;
Be arranged in the polysilicon structure in described first chamber;
Be arranged in the lining material layer between the wall in the part in described polysilicon structure and described first chamber; And
In the part of described lining material not between described polysilicon structure and the described wall in described first chamber, between described polysilicon structure and the described wall in described first chamber gap.
15. 1 kinds of semiconductor structures, comprising:
The first chamber in Semiconductor substrate;
Be arranged in the polysilicon structure in described first chamber;
Wall in described polysilicon structure and described first chamber at least part of between lining material layer; And
Gap between described polysilicon structure and the described wall in described first chamber, at lining material described in described gap location not between described polysilicon structure and the described wall in described first chamber.
16. semiconductor structures according to claim 15, comprise further:
Second chamber;
Can deflect thin slice, it is limited by the described substrate between described first chamber and described second chamber; And
Sensing element, it is configured to the deflection sensing described thin slice.
17. semiconductor structures according to claim 15, comprise further:
For sealing the encapsulant in described first chamber.
18. semiconductor structures according to claim 15, wherein, the described lining material between the part of the described wall in described first chamber and described polysilicon supports described polysilicon, and makes described polysilicon and described substrate electric insulation.
19. semiconductor structures according to claim 18, wherein, the described part that there is the described wall of described lining material is relative with described gap.
20. 1 kinds of semiconductor structures, comprising:
Semiconductor substrate, it comprises base substrate, sedimentary deposit and the electric insulation layer between described base substrate and described sedimentary deposit;
The first chamber in described sedimentary deposit, described electric insulation layer and described base substrate; And
The second chamber in described sedimentary deposit, limit the first thin slice in the described sedimentary deposit of described second chamber to atmosphere opening and between described first chamber and described second chamber, described first thin slice is crossing with described electric insulation layer;
Be arranged in the polysilicon structure in described first chamber;
Be arranged in the lining material layer between the wall in the part in described polysilicon structure and described first chamber; And
In the part of described lining material not between described polysilicon structure and the described wall in described first chamber, between described polysilicon structure and the described wall in described first chamber gap.
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| US11046575B2 (en) * | 2017-10-31 | 2021-06-29 | Encite Llc | Broad range micro pressure sensor |
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| US6387772B1 (en) * | 2000-04-25 | 2002-05-14 | Agere Systems Guardian Corp. | Method for forming trench capacitors in SOI substrates |
| TW200305008A (en) * | 2002-04-10 | 2003-10-16 | Hewlett Packard Co | A pressure sensor and method of making the same |
| EP1574833A2 (en) * | 2004-03-12 | 2005-09-14 | General Electric Company | Micromechanical system pressure sensor |
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| US6387772B1 (en) * | 2000-04-25 | 2002-05-14 | Agere Systems Guardian Corp. | Method for forming trench capacitors in SOI substrates |
| TW200305008A (en) * | 2002-04-10 | 2003-10-16 | Hewlett Packard Co | A pressure sensor and method of making the same |
| EP1574833A2 (en) * | 2004-03-12 | 2005-09-14 | General Electric Company | Micromechanical system pressure sensor |
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