CN102437200B - A kind of FRD device architectures and its manufacture method - Google Patents
A kind of FRD device architectures and its manufacture method Download PDFInfo
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Abstract
The present invention provide a kind of FRD device architectures and and preparation method thereof, insulating barrier is formed on the trenched side-wall of FRD device architectures, the surface recombination of the insulating barrier and p-type doped region is made as complex centre, so as to form the composite pathway from p-type doped region to insulating barrier, and then it is effectively improved the reverse recovery characteristic of device；And because of the presence of insulating barrier on trenched side-wall, make part script in p-type doped region after the compound carrier that composite pathway reaches p-type doped region upper surface is shielded by insulating barrier, it is combined in surface of insulating layer, so as to further increase emission effciency, is improved on-state voltage drop.In addition, by controlling the doping content of channel bottom in p-type doped region, so as to avoid carrier diffusion length from strongly reducing, avoid carrier scattering and auger recombination effect, improve the emission effciency of trench bottom regions in p-type doped region, groove be compensate for because reduction of adulterating causes on-state voltage drop to raise, improve forward voltage drop.
Description
Technical field
The present invention relates to the device architecture in IC manufacturing field and manufacture method, more particularly to a kind of FRD structures and
Its manufacture method.
Background technology
As oil coal reserve is ceaselessly reduced, and the energy resource consumption of the mankind is continuously increased, and energy-conservation becomes 21
Century the mankind common recognition.Estimate have 2/3rds electric power to be used in motor and drive according to USDOE.And use IGBT and
Matched FRD constant powers device can make motor drive energy-conservation 20%～30%.It is contemplated that power device can be in future
Rapid growth.
For FRD (Fast recovery diode, fast recovery diode) power device, its reverse recovery characteristic and just
All extremely important to conduction voltage drop, forward conduction voltage drop height means that energy conversion efficiency is low, and reverse recovery characteristic is bad to drop
Low usage frequency, it is also possible to damage IGBT device in module.For high pressure and the matching used FRD of IGBT, improve reversely extensive
Multiple characteristic has several ways：Reduce carrier lifetime to improve reverse recovery characteristic, reduce the injection efficiency in hole, inject high energy
The local complex centres such as hydrion, helium ion.However, reducing carrier lifetime to improve reverse recovery characteristic and reduce hole
The method of injection efficiency can increase the pressure drop of forward conduction, the method for injecting the local complex centres such as high energy hydrion, helium ion
The equipment for using is very expensive, is unfavorable for technique productions.
Content of the invention
The technical problem to be solved of the present invention is to provide one kind and can not use injection high energy hydrion, helium ion feelings
Increase complex centre under shape, to improve the device FRD structures of reverse recovery characteristic.
For solving the above problems, the present invention provides a kind of FRD device architectures, including N-type heavily doped layer；N-type doping layer, position
On the N-type heavily doped layer；And p-type doped region, in the n-type doping layer；At least one groove, positioned at the P
In type doped region, the depth of the groove is less than the thickness of the p-type doped region；Insulating barrier, is formed at the side wall of the groove
On.
Further, FRD device architectures also include protection ring, in the n-type doping layer, adulterate around the p-type
Area.
Further, the material of the insulating barrier is silicon dioxide or silicon oxynitride.
Further, the thickness of the insulating barrier is more than 20 nanometers.
Further, the depth of the groove is more than 3 microns, the width of the width of the groove and the p-type doped region
Than being less than 4/5 more than 2/3.
Further, the doping content of the p-type doped region is 5E15/cm3～1E17/cm3.
The present invention also provides a kind of manufacture method of FRD device architectures, including
Semiconductor substrate is provided, includes N-type heavily doped layer and n-type doping layer from bottom to top；
P-type doped region is formed in the n-type doping layer；
At least one groove is formed in the p-type doped region, and the depth of the groove is less than the thickness of the p-type doped region
Degree；
First time oxidation is carried out, so that oxide layer is formed on the bottom surface of the groove and side wall；
Dry etching removes the oxide layer for being located at trench bottom surfaces.
Further, after the step of dry etching removes the oxide layer for being located at trench bottom surfaces, also include：Carry out second
Secondary oxidation, to thicken the oxide layer positioned at trenched side-wall；Wet etching removes portion of oxide layer, exposes the channel bottom, with
Insulating barrier is formed in the side wall of the groove.
Further, the material of the insulating barrier is silicon dioxide or silicon oxynitride.
Further, the thickness of the insulating barrier is more than 20 nanometers.
Further, while the step of forming p-type doped region in the n-type doping layer, also include forming protection ring,
It is located in the n-type doping layer, around the p-type doped region.
Further, in the step of carrying out oxidation for the first time, the oxidation of formation on the bottom surface of the groove and side wall
The thickness of layer is more than 15 nanometers.
Further, the depth of the groove is more than 3 microns, the width of the width of the groove and the p-type doped region
Than being less than 4/5 more than 2/3.
Further, the doping content of the p-type doped region is 5E15/cm3～1E17/cm3.
Compared to prior art, FRD device architectures of the present invention form insulation on the trenched side-wall of FRD device architectures
Layer, makes the surface recombination of the insulating barrier and p-type doped region as complex centre, so as to be formed from p-type doped region to insulating barrier
Composite pathway, and then be effectively improved the reverse recovery characteristic of device；And the presence due to insulating barrier on trenched side-wall, makes portion
The compound carrier for reaching p-type doped region upper surface through composite pathway in p-type doped region originally is divided to be shielded by insulating barrier,
And be combined in surface of insulating layer, emission effciency is further increased, improves on-state voltage drop, such that it is able to not use injection
High energy hydrion, increases complex centre under helium ion situation, improves reverse recovery characteristic.
Meanwhile, by controlling the doping content of channel bottom in p-type doped region, it is to avoid carrier diffusion length drastically subtracts
Little, it is to avoid carrier scattering and auger recombination effect, the emission effciency of trench bottom regions in p-type doped region is improve, is compensated
Groove causes on-state voltage drop to raise because of reduction of adulterating, meanwhile, the carrier of part is when p-type doped region surface is reached in groove
Side wall is combined, and can equally improve on-state voltage drop, so as to further improve forward voltage drop.
Additionally, in the manufacture method of FRD device architectures, the doping injection and the doping of protection ring injection of p-type doped region are
Complete simultaneously, a step photoetching process is saved compared to the manufacturing process of FRD structures of the prior art, improve FRD devices
Make efficiency.
Description of the drawings
Fig. 1 is the structural representation of FRD device architectures in one embodiment of the invention.
Fig. 2 is the schematic flow sheet of FRD device architecture manufacture methods in one embodiment of the invention.
Fig. 3～Fig. 9 is the schematic flow sheet of FRD device architecture manufacture methods in one embodiment of the invention.
Specific embodiment
For making present disclosure more clear understandable, below in conjunction with Figure of description, present disclosure is made into one
Step explanation.The specific embodiment, the general replacement known to those skilled in the art the invention is not limited in certainly
Cover within the scope of the present invention.
Secondly, the present invention has carried out detailed statement using schematic diagram, when present example is described in detail, for the ease of saying
Bright, schematic diagram, should not be in this, as limitation of the invention not according to general ratio partial enlargement.
The present invention provides a kind of FRD device architectures, and Fig. 1 is FRD device architectures in an embodiment, as shown in figure 1, the FRD
Device architecture includes：N-type heavily doped layer 100；N-type doping layer 101, on the N-type heavily doped layer 100；P-type doped region
103, in the n-type doping layer 101；At least one groove 105, in the p-type doped region 103, the groove 105
Depth less than the p-type doped region 103 thickness；And insulating barrier 106, it is formed on the side wall of the groove 106.
In the present embodiment, the FRD device architectures also include protection ring 104 and dielectric layer 102, the protection ring 104
It is located in the n-type doping layer 101, around the p-type doped region 103, in Fig. 1, indicates the side of the protection ring 104
Structure, the region for omitting expression on the left of Fig. 1 also include another side structure of protection ring 104, so as to protection ring 104 is around described
P-type doped region 103.The dielectric layer 102 is formed in n-type doping layer 101, forms p-type doped region 103 and protection in doping
Play a part of mask blocks during ring 104, and as interlayer dielectric layer during subsequent technique.
In preferred embodiment, the material of the insulating barrier 106 is silicon dioxide or silicon oxynitride.Silicon dioxide and nitrogen
Silicon oxide has good repair, and trenched side-wall can be made to form the good contact in interface, so as to form good being combined
Region.The thickness of the insulating barrier can be further ensured that good recombination region more than 20 nanometers.
Further, the depth H of the groove 1051It is more than 3 microns, less than the thickness H of the p-type doped region 1032, and
The width W of the groove 1051Width W with the p-type doped region 1032Than being less than 4/5 more than 2/3, can effectively prevent P
Area in type doped region 103 beyond groove 105 is too small, causes the pressure of forward voltage generation excessive and damage device, while
Ensure the width W of the groove 1051Width W with the p-type doped region 1032Proportion is sufficiently large, to improve FRD devices
Performance during reverse operation.
Further, the doping content of the p-type doped region 103 is 5E15/cm3～1E17/cm3, concentration is more than 1E15/
cm3Being prevented from injection efficiency reduces making too much the pressure drop of opening of FRD device architectures to increase；Concentration is less than 1E17/cm3Can subtract
Little scattering and auger recombination between carrier and carrier occurs, and therefore avoids the reduction of carrier diffusion length, makes
The compound composite pathway A that 105 bottom of groove in p-type doped region 103 occurs, so that increased injection efficiency；Compensate for simultaneously
105 bottom of groove is because of forward conduction voltage drop rising caused by the low institute of the low-doped injection efficiency for causing.
Shown in Fig. 9, FRD device architectures of the present invention form insulation compared to prior art, on the side wall of its groove
Layer 106, makes the surface recombination of the insulating barrier 106 and p-type doped region 103 as complex centre, so as to such as be formed from p-type doping
Composite pathway B of the area 103 to insulating barrier 106, and then it is effectively improved the reverse recovery characteristic of device；And due to 105 side of groove
The presence of insulating barrier 106 on wall, makes part reach on p-type doped region 103 through composite pathway C in p-type doped region 103 originally
The compound carrier on surface is shielded by insulating barrier, but is combined in surface of insulating layer, is further increased emission effciency, is changed
Kind on-state voltage drop.Additionally, by the doping content for controlling 105 bottom of groove in p-type doped region 103, so as to avoid carrier from expanding
Scattered length is strongly reduced, it is to avoid carrier scattering and auger recombination effect, improves 105 bottom section of groove in p-type doped region 103
Emission effciency, compensate for groove 105 because adulterate reduction cause on-state voltage drop raise, improve forward voltage drop.Meanwhile, in the present invention
Structure in, have the carrier of part to be combined in groove side wall when p-type 103 surface of doped region is reached, can equally improve logical
State pressure drop.
Fig. 2 is the schematic flow sheet of FRD device architecture manufacture methods in one embodiment of the invention.As shown in Fig. 2 of the invention
In one embodiment of the manufacture method of the FRD device architectures for also providing, comprise the following steps：
Step S01：Semiconductor substrate is provided, includes N-type heavily doped layer and n-type doping layer from bottom to top；
Step S02：P-type doped region is formed in the n-type doping layer；
Step S03：At least one groove is formed in the p-type doped region, and the depth of the groove is mixed less than the p-type
The thickness in miscellaneous area；
Step S04：First time oxidation is carried out, so that oxide layer is formed on the bottom surface of the groove and side wall；
Step S05：Dry etching removes the oxide layer for being located at trench bottom surfaces；
Step S06：Second oxidation is carried out, to thicken the oxide layer positioned at trenched side-wall；
Step S07：Wet etching removes portion of oxide layer, exposes the channel bottom, with the side wall shape in the groove
Into insulating barrier.
Fig. 3～Fig. 9 is the schematic flow sheet of FRD device architecture manufacture methods in one embodiment of the invention.Below in conjunction with Fig. 1
And Fig. 3～Fig. 9 describes the manufacturing process of FRD device architectures of the present invention in detail.
As shown in figure 3, in step S01, there is provided semiconductor substrate, include N-type heavily doped layer 100 and N-type from bottom to top
Doped layer 101, forms N-type heavily doped layer and n-type doping layer on the substrate by controlling doping implantation concentration, wherein described N
The doping content of type heavily doped layer 100 is more than 5.0E19/cm3, the doping content of the n-type doping layer 101 be less than
6.6E13/cm3.
As shown in figure 4, in step S02, dielectric layer is formed on the surface in the n-type doping area 101 first, followed by
Photoetching and the dielectric layer 102 of etching technics patterning, are doped injection with the dielectric layer 102 for patterning as mask blocks, from
And form p-type doped region 103 and protection ring 104；Protection ring 104 is located in the n-type doping layer, is adulterated around the p-type
Area 103.The doping content of the p-type doped region 103 is 5E15/cm3～1E17/cm3, concentration is more than 1E15/cm3It is prevented from
Injection efficiency reduces making too much the pressure drop of opening of FRD device architectures to increase；Concentration is less than 1E17/cm3Carrier can be reduced
Scattering between carrier and auger recombination occur, and therefore avoid the reduction of carrier diffusion length, make compound generation exist
The composite pathway A of 105 bottom of groove in p-type doped region 103 shown in Fig. 9, so as to increased injection efficiency, therefore can be not
Using injection high energy hydrion, increase complex centre under helium ion situation, improve reverse recovery characteristic；Follow-up shape compensate for simultaneously
Into groove 105 bottom because the low-doped injection efficiency for causing low institute caused by forward conduction voltage drop raise.
As shown in figure 5, in step S03, the photoresist for continuing to form patterning in FRD device surfaces (is not marked in figure
Show), the photoresist with the patterning is performed etching as mask to the p-type doped region 103, so as to form at least one groove
105, the depth H of the groove 1051It is more than 3 microns, less than the thickness H of the p-type doped region 1032, and the groove 105
Width W1Width W with the p-type doped region 1032, effectively can prevent in p-type doped region 103 less than 4/5 than more than 2/3
Area beyond groove 105 is too small, the excessive damage device of the pressure for causing forward voltage to produce, while ensureing the groove 105
Width W1Width W with the p-type doped region 1032Proportion is sufficiently large, to improve property during FRD device reverse operations
Energy.
As shown in fig. 6, in step S04, first time oxidation is carried out, with shape on the bottom surface of the groove 105 and side wall
Into oxide layer 106a, oxide layer 106a can be formed using thermal oxidation method or chemical vapour deposition technique, now oxide layer 106a
Thickness is more than 15 nanometers；Then, as shown in fig. 7, the dry etching using anisotropic in step S05 is removed positioned at groove
Oxide layer 106a of 105 bottom surfaces, retains the oxide layer 106 for being located at 105 side wall of groove；Then, second is carried out in step S06
Oxidation, forms oxide layer 106b for thickening for being located at 105 side wall of groove, it is ensured that the thickness of oxide layer 106b and repair in step
Dry etching damage in S05, so as to form sull again in 105 bottom of groove, forms structure as shown in Figure 8；Cause
This, finally in step S07, removes portion of oxide layer 106b using wet etching, to expose the bottom of the groove 105, from
And the side wall in the groove 105 forms the insulating barrier 106 that thickness reaches requirement, structure as shown in Figure 9 is formed.
In sum, shown in Fig. 9 of the present invention, FRD device architectures of the present invention compared to prior art, in Qi Gou
Insulating barrier 106 is formed on the side wall of groove, makes the surface recombination of the insulating barrier 106 and p-type doped region 103 as complex centre,
So as to such as form the composite pathway B from p-type doped region 103 to insulating barrier 106, and then it is special to be effectively improved the Reverse recovery of device
Property；And the presence due to insulating barrier 106 on 105 side wall of groove, makes part pass through originally compound way in p-type doped region 103
Footpath C reaches the compound carrier of 103 upper surface of p-type doped region and is shielded by insulating barrier, but is combined in surface of insulating layer, enters
One step improves emission effciency, improves on-state voltage drop.Additionally, by the doping for controlling 105 bottom of groove in p-type doped region 103
Concentration, so as to avoid carrier diffusion length from strongly reducing, it is to avoid carrier scattering and auger recombination effect, improve p-type doping
The emission effciency of 105 bottom section of groove in area 103, compensate for groove 105 because reduction of adulterating causes on-state voltage drop to raise, improves
Forward voltage drop.Meanwhile, the carrier for having part in the present invention is answered in groove side wall when p-type 103 surface of doped region is reached
Close, can equally improve on-state voltage drop.
Additionally, the doping injection and the doping of protection ring injection of p-type doped region in the present invention is while complete, compared to
FRD structures of the prior art save a step photoetching process, improve element manufacturing efficiency.
Although the present invention is disclosed above with preferred embodiment, so which is not limited to the present invention, any affiliated technology
Has usually intellectual in field, without departing from the spirit and scope of the present invention, when a little change and retouching can be made, therefore
Protection scope of the present invention ought be defined depending on those as defined in claim.
Claims (14)
1. a kind of FRD device architectures, it is characterised in that include
N-type heavily doped layer；
N-type doping layer, on the N-type heavily doped layer；And
P-type doped region, in the n-type doping layer；P-type doped region constitutes PN junction with n-type doping layer；
At least one groove, in the p-type doped region, the depth of the groove is less than the thickness of the p-type doped region；Ditch
The p-type doped region of groove both sides and bottom is continuous；The bottom and both sides of groove is surrounded by p-type doped region, and channel bottom does not have
Penetrate the bottom of p-type doped region；And
Insulating barrier, is formed on the side wall of the groove；The bottom of the insulating barrier and the groove on the side wall of the groove
Portion contacts the p-type doped region, and the surface recombination of the insulating barrier and the p-type doped region is used as complex centre, so as to shape
Into the composite pathway from the p-type doped region to the insulating barrier.
2. FRD device architectures as claimed in claim 1, it is characterised in that also include protection ring, positioned at the n-type doping layer
In, around the p-type doped region.
3. FRD device architectures as claimed in claim 1, it is characterised in that the material of the insulating barrier is silicon dioxide or nitrogen
Silicon oxide.
4. FRD device architectures as claimed in claim 1, it is characterised in that the thickness of the insulating barrier is more than 20 nanometers.
5. FRD device architectures as claimed in claim 1, it is characterised in that the depth of the groove is more than 3 microns, the ditch
The width of groove is less than 4/5 with the width ratio of the p-type doped region more than 2/3.
6. FRD device architectures as claimed in claim 1, it is characterised in that the doping content of the p-type doped region is 5E15/
cm3～1E17/cm3.
7. a kind of manufacture method of FRD device architectures, including：
Semiconductor substrate is provided, includes N-type heavily doped layer and n-type doping layer from bottom to top；
P-type doped region is formed in the n-type doping layer；P-type doped region constitutes PN junction with n-type doping layer；
At least one groove is formed in the p-type doped region, and the depth of the groove is less than the thickness of the p-type doped region；
The bottom of the side wall and the groove of the groove contacts the p-type doped region；The p-type doped region of groove both sides and bottom is to connect
Continuous；The bottom and both sides of groove is surrounded by p-type doped region, and channel bottom does not penetrate the bottom of p-type doped region；
First time oxidation is carried out, so that oxide layer is formed on the bottom surface of the groove and side wall；
Dry etching removes the oxide layer for being located at trench bottom surfaces, so as to the side wall in the groove forms insulating barrier；The groove
Side wall on the insulating barrier and the bottom of the groove contact the p-type doped region, and the insulating barrier is mixed with the p-type
The surface recombination in miscellaneous area as complex centre, so as to form the composite pathway from the p-type doped region to the insulating barrier.
8. the manufacture method of FRD device architectures as claimed in claim 7, it is characterised in that remove in dry etching and be located at ditch
After the step of oxide layer of groove bottom, also include：
Second oxidation is carried out, to thicken the oxide layer positioned at trenched side-wall；
Wet etching removes portion of oxide layer, exposes the channel bottom, forms insulating barrier with the side wall in the groove.
9. the manufacture method of FRD device architectures as claimed in claim 8, it is characterised in that the material of the insulating barrier is two
Silicon oxide or silicon oxynitride.
10. the manufacture method of FRD device architectures as claimed in claim 8, it is characterised in that the thickness of the insulating barrier is more than
20 nanometers.
The manufacture method of 11. FRD device architectures as claimed in claim 7, it is characterised in that shape in the n-type doping layer
Into while the step of p-type doped region, also include forming protection ring, in the n-type doping layer, adulterate around the p-type
Area.
The manufacture method of the FRD device architectures in 12. such as claim 7 to 11 as described in any one, it is characterised in that carrying out
In the step of aoxidizing for the first time, the thickness of the oxide layer formed on the bottom surface of the groove and side wall is more than 15 nanometers.
The manufacture method of the FRD device architectures in 13. such as claim 7 to 11 as described in any one, it is characterised in that the ditch
The depth of groove is more than 3 microns, and the width of the groove is less than 4/5 with the width ratio of the p-type doped region more than 2/3.
The manufacture method of the FRD device architectures in 14. such as claim 7 to 11 as described in any one, it is characterised in that the P
The doping content of type doped region is 5E15/cm3～1E17/cm3.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4982260A (en) * | 1989-10-02 | 1991-01-01 | General Electric Company | Power rectifier with trenches |
| CN101866855A (en) * | 2010-06-07 | 2010-10-20 | 北京时代民芯科技有限公司 | Method for preparing chip of high-voltage planar fast-recovery diode |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6252288B1 (en) * | 1999-01-19 | 2001-06-26 | Rockwell Science Center, Llc | High power trench-based rectifier with improved reverse breakdown characteristic |
| US6710418B1 (en) * | 2002-10-11 | 2004-03-23 | Fairchild Semiconductor Corporation | Schottky rectifier with insulation-filled trenches and method of forming the same |
| US7696598B2 (en) * | 2005-12-27 | 2010-04-13 | Qspeed Semiconductor Inc. | Ultrafast recovery diode |
| US7944018B2 (en) * | 2006-08-14 | 2011-05-17 | Icemos Technology Ltd. | Semiconductor devices with sealed, unlined trenches and methods of forming same |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4982260A (en) * | 1989-10-02 | 1991-01-01 | General Electric Company | Power rectifier with trenches |
| CN101866855A (en) * | 2010-06-07 | 2010-10-20 | 北京时代民芯科技有限公司 | Method for preparing chip of high-voltage planar fast-recovery diode |
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