CN102437121B - The method that effective minimizing via etch stop-layer strain technique affects PMOS - Google Patents
The method that effective minimizing via etch stop-layer strain technique affects PMOS Download PDFInfo
- Publication number
- CN102437121B CN102437121B CN201110235242.5A CN201110235242A CN102437121B CN 102437121 B CN102437121 B CN 102437121B CN 201110235242 A CN201110235242 A CN 201110235242A CN 102437121 B CN102437121 B CN 102437121B
- Authority
- CN
- China
- Prior art keywords
- pmos
- barrier layer
- etching barrier
- transistor seconds
- etch stop
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The present invention effectively reduces via etch stop layer process and the method that PMOS affects is solved to the silicon nitride usually only having tensile stress in the via etch stop-layer technical matters of prior art, while nmos device performance is got a promotion, the characteristic of PMOS device is had to the problem of decay to a certain degree, (UV process is specifically comprised by certain technique processing method, heavy ion bombardment, such as Sn, Kr etc.) certain process is done to the tensile stress silicon nitride film of PMOS area, destroy the crystal structure that it is intrinsic, thus discharge the tensile stress of its intrinsic, thus reach the object reducing PMOS device characteristic attenuation.
Description
Technical field
The present invention relates to a kind of semiconductor technology, particularly relate to a kind of method that effective minimizing via etch stop-layer strain technique affects PMOS.
Background technology
In first generation CESL technique, usually only have the silicon nitride of tensile stress to be used, the stress types needed due to NMOS and PMOS is contrary, so, this kind of stress film, while improving nmos device characteristic, has decay to a certain degree to the device property of PMOS.
A.Shimizu in 2002, IEDM reports a kind of Ge of employing and injects the method regulating CESL technogenic influence, to eliminate the deterioration of CESL technique for PMOS.
IBM alliance, in its deep submicron process, uses Xe to inject to reduce CESL technique to propose protect a kind of method adopting ion injection method to inject PMOS area to discharge the stress of PMOS area for the Chinese patent 200510074788.1 in 2006 that affects of PMOS.But the injection particle used in this patent comprises Si, Ge, Ar and Xe tetra-kinds of elements.
Summary of the invention
The invention discloses a kind of method that effective minimizing via etch stop-layer strain technique affects PMOS, in order to solve prior art via etch stop-layer technical matters in usually only have the silicon nitride of tensile stress, while nmos device performance is got a promotion, the characteristic of PMOS device is had to the problem of decay to a certain degree.
Above-mentioned purpose of the present invention is achieved through the following technical solutions:
The method that effective minimizing via etch stop-layer strain technique affects PMOS, a silicon substrate is formed a first transistor and a transistor seconds, wherein, comprises the following steps:
Step a: grow an etching barrier layer on a silicon substrate, the first transistor, transistor seconds cover by etching barrier layer simultaneously, and etching barrier layer provides tensile stress to the first transistor, transistor seconds;
Step b: spin coating photoresist on substrate, covers completely by etching barrier layer;
Step c: the photoresist covered on transistor seconds is removed in photoetching;
Steps d: process the etching barrier layer that transistor seconds covers, destroys crystal structure intrinsic for this partial etching barrier layer, to reduce the tensile stress that this partial etching barrier layer provides transistor seconds;
Step e: photoresist is removed.
The method effectively reducing via etch stop-layer strain technique and affect PMOS as above, wherein, etching barrier layer is silicon nitride layer.
The method effectively reducing via etch stop-layer strain technique and affect PMOS as above, wherein, the first transistor is nmos device, and transistor seconds is PMOS device.
The method effectively reducing via etch stop-layer strain technique and affect PMOS as above, wherein, carries out ultraviolet process to the etching barrier layer that transistor seconds covers in steps d.
The method effectively reducing via etch stop-layer strain technique and affect PMOS as above, wherein, carries out heavy particle injection to the etching barrier layer that transistor seconds covers in steps d.
The method effectively reducing via etch stop-layer strain technique and affect PMOS as above, wherein, in steps d, heavy particle injection technology adopts Sn, Kr.
In sum, owing to have employed technique scheme, the present invention effectively reduces via etch stop-layer strain technique to be affected PMOS, solve the silicon nitride usually only having tensile stress in the via etch stop-layer technical matters of prior art, while nmos device performance is got a promotion, the characteristic of PMOS device is had to the problem of decay to a certain degree, (UV process is specifically comprised by certain technique processing method, heavy ion bombardment, such as Sn, Kr etc.) certain process is done to the tensile stress silicon nitride film of PMOS area, destroy the crystal structure that it is intrinsic, thus discharge the tensile stress of its intrinsic, thus reach the object reducing PMOS device characteristic attenuation.
Accompanying drawing explanation
By reading the detailed description done non-limiting example with reference to the following drawings, the present invention and feature, profile and advantage will become more obvious.Mark identical in whole accompanying drawing indicates identical part.Deliberately proportionally do not draw accompanying drawing, focus on purport of the present invention is shown.
Fig. 1 is that the present invention effectively reduces via etch stop-layer strain technique to the silicon substrate of the method that PMOS affects being formed the schematic diagram after the first transistor and transistor seconds;
Fig. 2 is that the present invention effectively reduces via etch stop-layer strain technique to the schematic diagram after the formation etching barrier layer of the method that PMOS affects;
Fig. 3 is that the present invention effectively reduces the via etch stop-layer strain etching removal unit of technique on the method that PMOS affects and divides the schematic diagram after photoresist;
Fig. 4 is that the present invention effectively reduces via etch stop-layer strain technique to the schematic diagram after the processing etching barrier layer of the method that PMOS affects.
Embodiment
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is further described:
Fig. 1 is that the present invention effectively reduces via etch stop-layer strain technique to the silicon substrate of the method that PMOS affects being formed the schematic diagram after the first transistor and transistor seconds, refer to Fig. 1, a kind of method that effective minimizing via etch stop-layer strain technique affects PMOS, a silicon substrate is formed the first transistor 101 and a transistor seconds 201, wherein, comprise the following steps:
Fig. 2 is that the present invention effectively reduces via etch stop-layer strain technique to the schematic diagram after the formation etching barrier layer of the method that PMOS affects, refer to Fig. 2, step a: grow an etching barrier layer 301 on a silicon substrate, the first transistor 101, transistor seconds 201 cover by etching barrier layer 301 simultaneously, and etching barrier layer 301 provides tensile stress to the first transistor 101, transistor seconds 201;
Wherein, the etching barrier layer 301 adopted in the present invention can be silicon nitride layer, can provide tensile stress after silicon nitride layer is formed for the first transistor 101 and transistor seconds 201.
The first transistor 101 in the present invention is nmos device, transistor seconds 201 is PMOS device, nmos device is different from the stress types of the many needs of PMOS device, be applied to tensile stress on nmos device and effectively can improve the performance of nmos device, but tensile stress is applied to the hydraulic performance decline that PMOS device can make PMOS device, therefore after covering silicon nitride layer in this step on nmos device and PMOS device, because silicon nitride layer produces tensile stress, therefore while making nmos device performance boost, the performance of PMOS device is affected and declines.
Step b: spin coating photoresist on substrate, covers completely by etching barrier layer 301;
Fig. 3 is that the present invention effectively reduces the via etch stop-layer strain etching removal unit of technique on the method that PMOS affects and divides the schematic diagram after photoresist, refer to Fig. 3, step c: the photoresist covered on transistor seconds 201 is removed in photoetching, the photoresist covered on the first transistor 101 is retained, for changing the crystal structure headspace on silicon nitride etch barrier layer 301 in subsequent technique;
Fig. 4 is that the present invention effectively reduces via etch stop-layer strain technique to the schematic diagram after the processing etching barrier layer of the method that PMOS affects, refer to Fig. 4, steps d: the etching barrier layer 301 that transistor seconds 201 covers is processed, crystal structure intrinsic for this partial etching barrier layer 301 is destroyed, to reduce the tensile stress that 301 pairs, this partial etching barrier layer transistor seconds 201 provides, transistor seconds 201 is PMOS device, therefore the performance of tensile stress to PMOS device that silicon nitride etch barrier layer 301 provides causes adverse influence, after the technique of steps d, the tensile stress that covering the silicon nitride film in PMOS device provides declines, thus decrease the impact of silicon nitride etch barrier layer 301 on PMOS device performance,
Wherein, ultraviolet process can be carried out to the etching barrier layer 301 that transistor seconds 201 covers in steps d, the intrinsic crystal structure of etching barrier layer 301 is destroyed, to reduce the technique effect of the tensile stress that 301 pairs, this partial etching barrier layer transistor seconds 201 provides to reach;
Further, also heavy particle injection can be carried out to the etching barrier layer 301 that transistor seconds 201 covers in steps d, play equally and destroy the intrinsic crystal structure of etching barrier layer 301, reduce the technique effect of the tensile stress that 301 pairs, this partial etching barrier layer transistor seconds 201 provides.
Wherein, in steps d, heavy particle injection technology adopts Sn, Kr.
Step e: photoresist is removed.
In sum, owing to have employed technique scheme, the present invention effectively reduces via etch stop-layer strain technique and the method that PMOS affects is solved to the silicon nitride usually only having tensile stress in the via etch stop-layer technical matters of prior art, while nmos device performance is got a promotion, the characteristic of PMOS device is had to the problem of decay to a certain degree, (UV process is specifically comprised by certain technique processing method, heavy ion bombardment, such as Sn, Kr etc.) certain process is done to the tensile stress silicon nitride film of PMOS area, destroy the crystal structure that it is intrinsic, thus discharge the tensile stress of its intrinsic, thus reach the object reducing PMOS device characteristic attenuation.
It should be appreciated by those skilled in the art that those skilled in the art can realize described change case in conjunction with prior art and above-described embodiment, do not repeat them here.Such change case does not affect flesh and blood of the present invention, does not repeat them here.
Above preferred embodiment of the present invention is described.It is to be appreciated that the present invention is not limited to above-mentioned particular implementation, the equipment wherein do not described in detail to the greatest extent and structure are construed as to be implemented with the common mode in this area; Any those of ordinary skill in the art, do not departing under technical solution of the present invention ambit, the Method and Technology content of above-mentioned announcement all can be utilized to make many possible variations and modification to technical solution of the present invention, or being revised as the Equivalent embodiments of equivalent variations, this does not affect flesh and blood of the present invention.Therefore, every content not departing from technical solution of the present invention, according to technical spirit of the present invention to any simple modification made for any of the above embodiments, equivalent variations and modification, all still belongs in the scope of technical solution of the present invention protection.
Claims (4)
1. the method effectively reducing via etch stop-layer strain technique and PMOS is affected, be applied in CESL technique, to reduce the object of PMOS device characteristic attenuation, described method is included on a silicon substrate and forms a first transistor and a transistor seconds, it is characterized in that, further comprising the steps of:
Step a: grow an etching barrier layer on a silicon substrate, the first transistor, transistor seconds cover by etching barrier layer simultaneously, and etching barrier layer provides tensile stress to the first transistor, transistor seconds;
Step b: spin coating photoresist on substrate, covers completely by etching barrier layer;
Step c: the photoresist covered on transistor seconds is removed in photoetching;
Steps d: process the etching barrier layer that transistor seconds covers, destroys crystal structure intrinsic for this partial etching barrier layer, to reduce the tensile stress that this partial etching barrier layer provides transistor seconds;
Step e: photoresist is removed;
Wherein, carry out heavy particle injection in steps d to the etching barrier layer that transistor seconds covers, described heavy particle injection technology adopts Sn, Kr.
2. effective minimizing via etch stop-layer according to claim 1 strains the method that technique affects PMOS, and it is characterized in that, etching barrier layer is silicon nitride layer.
3. effective minimizing via etch stop-layer according to claim 1 strains the method that technique affects PMOS, and it is characterized in that, the first transistor is nmos device, and transistor seconds is PMOS device.
4. effective minimizing via etch stop-layer according to claim 1 strains the method that technique affects PMOS, it is characterized in that, carries out ultraviolet process in steps d to the etching barrier layer that transistor seconds covers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110235242.5A CN102437121B (en) | 2011-08-17 | 2011-08-17 | The method that effective minimizing via etch stop-layer strain technique affects PMOS |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110235242.5A CN102437121B (en) | 2011-08-17 | 2011-08-17 | The method that effective minimizing via etch stop-layer strain technique affects PMOS |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102437121A CN102437121A (en) | 2012-05-02 |
| CN102437121B true CN102437121B (en) | 2016-01-27 |
Family
ID=45985109
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110235242.5A Active CN102437121B (en) | 2011-08-17 | 2011-08-17 | The method that effective minimizing via etch stop-layer strain technique affects PMOS |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102437121B (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101266949A (en) * | 2007-03-16 | 2008-09-17 | 联华电子股份有限公司 | Method for making strain silicon CMOS transistor |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060249795A1 (en) * | 2005-05-04 | 2006-11-09 | Neng-Kuo Chen | Semiconductor device and fabricating method thereof |
-
2011
- 2011-08-17 CN CN201110235242.5A patent/CN102437121B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101266949A (en) * | 2007-03-16 | 2008-09-17 | 联华电子股份有限公司 | Method for making strain silicon CMOS transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102437121A (en) | 2012-05-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20100038685A1 (en) | Enhanced dislocation stress transistor | |
| TW200802628A (en) | Semiconductor structure and fabrications thereof | |
| CN101924107B (en) | Stress enhanced CMOS (Complementary Metal-Oxide-Semiconductor) transistor structure | |
| CN102437121B (en) | The method that effective minimizing via etch stop-layer strain technique affects PMOS | |
| WO2009054115A1 (en) | SEMICONDUCTOR DEVICE OF SOI (Silicon on insulator) STRUCTURE, AND ITS MANUFACTURING METHOD | |
| US7863646B2 (en) | Dual oxide stress liner | |
| CN102364663A (en) | Grid side wall etching method, metal-oxide-semiconductor (MOS) device manufacturing method and MOS device | |
| CN102254808B (en) | Method for reducing LER and device for implementing the method | |
| US8569137B1 (en) | Method of improving PMOS performance in a contact etch stop layer process | |
| CN105070688B (en) | A kind of CMOS trap forming methods for saving light shield | |
| CN103972147A (en) | Narrow trench manufacturing method | |
| CN103943507A (en) | Embedded germanium-silicon epitaxy dislocation fault improving method | |
| CN103258731B (en) | Avoid the method that surface of silicon is damaged | |
| CN102709179B (en) | Forming method of dual-stress silicon nitride etched block layer and manufacturing method of semiconductor device | |
| KR100808797B1 (en) | Method of implanting ion in semiconductor device | |
| CN100452324C (en) | A method to etch barrier layer of self-alignment refractory metal silicide | |
| CN102354680A (en) | Field oxide wet etching method and semiconductor device | |
| CN102437046A (en) | Common manufacturing process of metal silicide barrier layer and stress memory layer | |
| CN104425345A (en) | Formation method for shallow trench isolation structure | |
| CN103337458B (en) | Improve the method for semiconductor device electrical property parameter | |
| CN100474565C (en) | Front technique for manufacturing high voltage LCD driving device | |
| TW200642037A (en) | Semiconductor device and fabricating method thereof | |
| CN108155238B (en) | Strain NMOSFET device with surface stress modulation structure | |
| JP2008108913A (en) | Method of manufacturing semiconductor device | |
| CN101488478A (en) | Integrated method for protecting polycrystalline and substrate surface |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |