CN102437102B - 用于活化能辅助烘烤的方法和装置 - Google Patents
用于活化能辅助烘烤的方法和装置 Download PDFInfo
- Publication number
- CN102437102B CN102437102B CN201110268878.XA CN201110268878A CN102437102B CN 102437102 B CN102437102 B CN 102437102B CN 201110268878 A CN201110268878 A CN 201110268878A CN 102437102 B CN102437102 B CN 102437102B
- Authority
- CN
- China
- Prior art keywords
- baking
- aea
- substrate
- pattern
- dielectric layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 75
- 239000000758 substrate Substances 0.000 claims abstract description 75
- 238000005530 etching Methods 0.000 claims abstract description 32
- 238000004140 cleaning Methods 0.000 claims abstract description 9
- 238000005498 polishing Methods 0.000 claims abstract description 9
- 230000008569 process Effects 0.000 claims description 26
- 229910052751 metal Inorganic materials 0.000 claims description 25
- 239000002184 metal Substances 0.000 claims description 25
- 230000004913 activation Effects 0.000 claims description 8
- 238000001259 photo etching Methods 0.000 claims description 5
- 239000000126 substance Substances 0.000 abstract description 15
- 239000010410 layer Substances 0.000 description 68
- 239000000463 material Substances 0.000 description 24
- 229920002120 photoresistant polymer Polymers 0.000 description 19
- 230000005855 radiation Effects 0.000 description 17
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 13
- 229910052802 copper Inorganic materials 0.000 description 13
- 239000010949 copper Substances 0.000 description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 238000005229 chemical vapour deposition Methods 0.000 description 9
- 239000013078 crystal Substances 0.000 description 8
- 238000000151 deposition Methods 0.000 description 8
- 239000004065 semiconductor Substances 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 7
- 235000012239 silicon dioxide Nutrition 0.000 description 7
- 230000008021 deposition Effects 0.000 description 6
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 6
- 239000006227 byproduct Substances 0.000 description 5
- 239000007789 gas Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000012545 processing Methods 0.000 description 4
- 239000010453 quartz Substances 0.000 description 4
- 239000002002 slurry Substances 0.000 description 4
- 238000005411 Van der Waals force Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 239000012528 membrane Substances 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- 229910008051 Si-OH Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910006358 Si—OH Inorganic materials 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 2
- 239000006117 anti-reflective coating Substances 0.000 description 2
- 125000004429 atom Chemical group 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000012634 fragment Substances 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 125000002496 methyl group Chemical group [H]C([H])([H])* 0.000 description 2
- 239000002243 precursor Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 244000132059 Carica parviflora Species 0.000 description 1
- 235000014653 Carica parviflora Nutrition 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 1
- 208000034189 Sclerosis Diseases 0.000 description 1
- 229920002472 Starch Polymers 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- OBNDGIHQAIXEAO-UHFFFAOYSA-N [O].[Si] Chemical compound [O].[Si] OBNDGIHQAIXEAO-UHFFFAOYSA-N 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- XKRFYHLGVUSROY-UHFFFAOYSA-N argon Substances [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- -1 argon ion Chemical class 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000007334 copolymerization reaction Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000005518 electrochemistry Effects 0.000 description 1
- 230000005670 electromagnetic radiation Effects 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 239000004088 foaming agent Substances 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 229910001507 metal halide Inorganic materials 0.000 description 1
- 150000005309 metal halides Chemical class 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- SCPYDCQAZCOKTP-UHFFFAOYSA-N silanol Chemical compound [SiH3]O SCPYDCQAZCOKTP-UHFFFAOYSA-N 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 238000004611 spectroscopical analysis Methods 0.000 description 1
- 235000019698 starch Nutrition 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 238000001429 visible spectrum Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76811—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving multiple stacked pre-patterned masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76813—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76828—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02134—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material comprising hydrogen silsesquioxane, e.g. HSQ
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02137—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material comprising alkyl silsesquioxane, e.g. MSQ
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02203—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being porous
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
本发明提供一种用于在衬底上形成互连件的方法和装置,包括在超低k电介质中蚀刻图样并使用活化能辅助烘烤从超低k电介质中去除湿气。在活化能辅助烘烤期间,以大约300至400摄氏度的温度,加热超低k电介质并将其暴露给仅具有大于400nm波长的光大约1至20分钟。在湿式清洁之后或者在化学机械抛光之后或者在二者之后执行活化能辅助烘烤。
Description
技术领域
本发明总的来说涉及半导体制造工艺,更具体地,涉及半导体工艺以及用于形成互连件的工具。
背景技术
为了减少互连件延迟和电容,低介电常数(低k)材料被用作集成电路(IC)器件中金属线的绝缘电介质。近年来,已经开发了低k(k大约小于3.5)材料来代替相对较高介电常数的绝缘材料,诸如二氧化硅。具体地,低k膜被用于半导体器件中金属线之间的层间和层内电介质层。此外,一些超低k(k大约小于2.5)材料膜利用细孔,即,多孔低k电介质膜来形成。这种超低k膜可以通过与光刻胶的涂覆类似的旋涂电介质(SOD)方法或者通过化学气相沉积(CVD)来沉积。因此,低k和超低k材料的使用被容易地适用于现有的半导体制造工艺。
低k和超低k材料没有传统的二氧化硅坚固,因此在等离子体处理期间容易损坏。它们还容易在湿式处理期间吸收环境中的湿气。湿气的吸收、等离子体损坏以及它们形成中的副产品会对产品的电性能和可靠性产生不利的影响。
虽然形成互连件的现有方法已经非常充分,但还不能在每一个方面都完全满意。希望继续寻求更加有效的方法和室,其能够去除不需要的湿气和副产品,并修复损坏而不增加介电常数。
发明内容
本发明的一个方面涉及用于在衬底上形成互连件的方法。该方法包括:在衬底上沉积超低k电介质层;在超低k电介质中蚀刻第一图样;活化能辅助(active energy assist,AEA)烘烤衬底;用金属填充图样;以及对金属进行平面化以露出超低k电介质层的一部分。AEA烘烤可以(1)在蚀刻之后填充图样之前,和/或(2)在平面化之后执行。在活化能辅助烘烤期间,以大约300至大约400摄氏度的温度,超低k电介质层被加热并暴露给具有波长仅大于400nm的光大约1至大约20分钟。
本发明的另一方面涉及用于在SPSE(特殊图样/特殊蚀刻)工艺之后在衬底上形成互连件的方法。该方法包括:在衬底上沉积超低k电介质层;执行第一光刻工艺以形成第一图样;在超低k电介质层蚀刻第一图样;执行第二光刻工艺以形成第二图样;在超低k电介质层蚀刻第二图样;对衬底进行湿式清洁;在湿式清洁之后活化能辅助烘烤(AEA)衬底;用金属填充图样;以及对金属进行化学机械抛光以露出超低k电介质层的一部分。活化能辅助烘烤还可以在化学机械抛光之后执行。在SPSE工艺中,如果叠加,第一图样和第二图样形成不能使用一个光掩模分辨的图像。
本发明的又一方面涉及活化能辅助(AEA)烘烤室,包括AEA光源组件、加热器基座和控制器,控制器用于控制输入至AEA光源组件和加热器基座中的能量。下面参照相关的附图讨论本发明的这些和其他方面。
附图说明
当读取附图时,根据以下详细描述更好地理解本发明的各个方面。重点强调的是,根据工业的标准实践,各个部件没有按比例绘制。实际上,为了讨论的清晰,各个部件的尺寸可以任意增加或减小。
图1是示出根据本发明各个实施例的形成互连件的方法的流程图;
图2A至图2D示出了根据图1方法的各个实施例的处于各个制造阶段的互连件的一层的截面图;
图3和图4示出了适合于实践本发明的各个方法实施例的室的实施例;以及
图5是示出包括本发明实施例的来自经受各种烘烤条件的衬底的湿气含量的测量数据的图表。
具体实施方式
应该理解,以下公开提供了用于实现各个实施例的不同特征的许多不同的实施例或实例。以下描述了组件和配置的具体实例以简化本公开。当然,它们仅仅是实例并且不是用于限制的目的。例如,以下描述中在第二部件上方或上形成第一部件可包括第一和第二部件被形成为直接接触的实施例,并且还包括可以在第一和第二部件之间形成附加部件的实施例,使得第一和第二部件可以不直接接触。当然,描述可指定部件彼此直接接触的状态。此外,本公开可以在各个实例中重复参考标号和/或字母。这种重复是为了简化和清楚的目的,并不是表示所讨论的各个实施例和/或结构之间的关系。
随着临界尺寸持续缩小,具有较低介电常数的电介质材料被越来越多地用作互连结构中的绝缘电介质。已知的互连结构包括金属填充的通孔和沟槽的多个金属层,在通孔和沟槽之间具有电介质材料。一般如下形成根据镶嵌处理的典型金属层。在包括部分制造的器件和/或电路的衬底上沉积电介质层。然后,在电介质层上形成图样以限定金属部件(其可以包括沟槽和通孔)。然后,图样被用于蚀刻电介质层,并在一些地方露出层下方的任何金属接触。典型的蚀刻工艺是各向异性干式蚀刻,随后为湿式清洁。由此蚀刻的图样随后在若干操作中被填充有金属(通常为铜)。在蚀刻图样中沉积阻挡/晶种材料的薄膜,以防止随后的铜扩散以及提供用于铜电镀的晶种层。然后,在图样中电镀铜以对其进行填充。铜不仅填充图样,而且累积在电介质层的未图样化部分上方的场地区域中。然后,使用化学机械抛光(CMP)使衬底平滑,以从场地区域中去除铜来露出电介质层。
该典型工艺包括湿气进入层的许多机会。只要电介质层暴露给周围环境,大多数通常在衬底离开半导体工具之后并在下一操作之前等待时,周围环境中的湿气就会进入电介质层。湿气还存在于湿式处理中:在湿式清洁和CMP期间。湿式蚀刻和CMP浆中的湿气可进入电介质材料。
湿气吸收量部分依赖于电介质材料的条件。非常多孔的超低k材料比较少孔的材料吸收更多的湿气。此外,更多的湿气趋于通过等离子体损坏的表面(诸如由蚀刻而得到的表面)来吸收。湿气吸收可以被粗略划分为两类:自由键和Van der Waals。在等离子体蚀刻之后,一些硅自由键保留并容易与湿式蚀刻剂或浆中的环境湿气结合。湿气还通过较弱范德华力(Van der Waals force)被吸引到电介质材料。通过自由键吸收的湿气比通过Van der Waals吸收的湿气更加难以去除。
尽管衬底在每个湿式工艺之后干燥,但干燥处理仅去除了没有吸收和结合的湿气。在炉子或单晶片烘烤(SWB)室中通过热烘烤衬底的进一步干燥被用于去除一些被结合的湿气。典型地,衬底以大约350℃的温度被烘烤大约一分钟以上。然而,通过使用非常多孔的材料,需要越来越长的烘烤时间来充分去除湿气和其他工艺的副产品。以30分钟以上的烘烤时间,烘烤操作对生产产生不利的效果并影响了循环时间。在通过自由键方法吸收更多湿气的一些情况下,会要求甚至更高的衬底温度来去除湿气,高温的使用被允许处理衬底的总热量预算所限制。
除了或代替根据本发明各个实施例的热烘烤,活化能辅助(AEA)烘烤被用于去除湿气。AEA烘烤包括将衬底暴露给光辐射,其仅具有大于约400nm的波长或者仅具有约400nm至约1000nm之间的波长。衬底可通过加热器基座被同时加热。衬底被AEA烘烤至少一分钟,约5至20分钟,或者约10分钟。在AEA烘烤期间,衬底温度上升并保持在大约350摄氏度,或者大约300至400摄氏度。光强度为大约10W/cm2至大约500W/cm2,或者至少10W/cm2。
以小于约400nm的波长,光能足以促进电介质膜中硅-氧键的交联。虽然更高的交联提高了电解质膜的机械特性,但其还引起了膜收缩并增加了电介质膜的介电常数。膜收缩通过使通孔和沟槽更大而改变了临界尺寸。介电常数的增加是不期望的,因为其与使用低k和超低k材料作为电介质层的目的相矛盾。因此,AEA烘烤不包括以小于约400nm或小于约350nm的波长将衬底暴露给足以促进交联的光能。
大约400nm和1000nm之间的波长范围覆盖了可见光谱和近红外线的一部分。在这些波长处,光能足以破坏硅烷醇(Si-OH)键,并克服吸收湿气和电介质材料之间的van der Waals吸引力,但是不足以引起有害的交联。在AEA烘烤期间,从互连件形成工艺的各个阶段去除湿气和副产品。副产品的实例可以是利用电介质材料沉积的附加成分,其趋向于在随后的处理期间被离析和去除。
在长于1000nm并短于1mm的波长处,辐射大多数为热辐射,并且不足以以烘烤温度破坏键。因此,AEA烘烤不排除将衬底暴露给波长长于约1000nm的辐射,但是处于该波长范围的辐射不用于湿气的去除,而是主要将衬底温度升高到烘烤温度。
根据特定实施例,使用AEA烘烤形成互连件与仅热烘烤相比提高了工艺时间。工艺时间的提高减少了成本并增加了工具利用率和循环时间。AEA烘烤的使用还节省了后端热预算。
如上所述,AEA烘烤对于多孔超低k电介质膜和SPSE(特殊图样/特殊蚀刻)处理的实施尤其有用。在SPSE处理中,电介质层被图样化并被蚀刻两次,以形成不能使用一个光掩模分辨的图样。第一底部抗反射涂层(BARC)和第一光刻胶层被沉积在电介质层上,被曝光、显影和蚀刻以在电介质层中形成第一图样,并在沉积第二BARC和第二光刻胶层来在电介质层中形成第二图样之前被去除。图1以及图2A至图2D示出了互连件形成条件下的SPSE处理和AEA烘烤。相信SPSE处理比其他图样化工艺引起更多的湿气吸收和等离子体损坏。
图1示出了根据本发明各个实施例的使用超低k电介质膜和SPSE处理形成互连件的方法11。在操作13中,超低k电介质层被沉积在衬底上。衬底的顶面可以为半导体、金属导体或电介质膜将被形成在其上的任何其他材料。更普遍地,衬底包括部分制造的半导体器件,其具有先前沉积材料的层。电介质膜可具有小于SiO2的介电常数(其大约为4(例如,热二氧化硅的介电常数可以在3.8至3.9的范围内))的介电常数值。电介质膜可具有小于2.5的介电常数、小于2.2的介电常数或小于1.7的介电常数。电介质膜可被描述为超低k膜。电介质膜可包括有机、无机和无机-有机混合材料中的至少一种。此外,电介质膜可以是多孔或非多孔的。
电介质膜可包括单相或双相多孔膜,其包括结构形成材料和孔生成材料。结构形成材料可包括原子、分子或源自结构形成前体的分子片段。孔生成材料可包括原子、分子或源自孔生成前体(例如,致孔剂)的分子片段。单相或双相多孔膜在去除孔生成材料之前比去除孔生成材料之后可具有更大的介电常数。例如,形成单相多孔电介质膜包括在衬底的表面上沉积结构形成分子,其具有弱结合至结构形成分子的孔生成分子侧基。此外,例如,形成双相多孔电介质膜包括在衬底的表面上共聚结构形成分子和孔生成分子。
电介质膜的实例包括可从Applied Materials公司得到的Black DiamondTMCVD有机硅酸盐玻璃(OSG)膜或者可从Novellus Systems得到的CoralTMCVD膜。其他电介质膜包括使用SOD技术沉积的无机、硅酸盐基材料,诸如含氢硅酸盐(HSQ)或甲基倍半硅氧烷(methyl silsesquioxane,MSQ)。这种膜的实例包括可从Dow Corning得到的FOx HSQ、可从Dow Corning得到的XLK多孔HSQ以及可从JSR Microelectronics得到的JSRLKD-5109。其他实例包括可从Dow Chemical得到的各种SiLK半导体电介质树脂以及可从Honeywell得到的FLARETM和NanoglassTM。
电介质膜可使用化学气相沉积(CVD)技术或旋涂电介质(SOD)技术来形成,诸如可从Tokyo Electron Limited(TEL)、Applied Materials公司或Novellus System得到的那些。
在操作15中,在超低k电介质层中形成并蚀刻第一图样。图2A示出了形成第一图样。衬底31在蚀刻停止层33的下方,蚀刻停止层33在超低k电介质层35的下方。抗反射层37(ARL)和图样化硬掩模层39被形成在超低k电介质层35的上方。第一底部抗反射涂层(BARC)41和第一光刻胶层43被沉积在硬掩模层39的上方,因此也在电介质层35的上方。光刻胶层43的部分45通过改变所露出部分中光刻胶的化学特性的光掩模来暴露给辐射,使其易于被显影剂化学物所溶解。在图2A中,光刻胶层43的部分45被暴露给辐射、显影和去除。光刻胶层的剩余部分被硬化。由此在光刻胶中形成第一图样。然后,图样45通过蚀刻延伸到超低k电介质层35。如图2B所示,蚀刻使开口45延伸到超低k电介质层35,形成通孔47。选择蚀刻条件,使得光刻胶层43的开口部分45下方的材料比光刻胶层43的硬化剩余部分更优先被蚀刻。在形成通孔47之后,在剥离工艺中去除BARC 41和光刻胶层43的剩余部分,得到图2B所示的结构。
在图1的下一操作中,在操作17中,在超低k电介质层中形成并蚀刻第二图样。图2C示出了形成第二图样。在硬掩模层39并由此在电介质层35上沉积第二BARC 49和第二光刻胶层51,填充先前形成的通孔47。光刻胶的一部分通过改变光刻胶的化学特性的光掩模被暴露给辐射,使其易于被显影剂化学物所溶解。在图2C中,光刻胶层51的部分53被暴露给辐射,并在显影之后被去除。由此在光刻胶中形成第二图样。然后,图样53通过蚀刻延伸到超低k电介质层35中。
然后,去除光刻胶层51以及任选地去除BARC 49。如图2D所示,进一步的蚀刻将开口53和45延伸到超低k电介质层35中,现在使用硬掩模39中的开口作为图样来形成延伸通过蚀刻停止层33的沟槽/通孔部件55和57。在剥离工艺中去除任何剩余的BARC和光刻胶。在剥离之后,衬底可以被湿式清洁。
如上所讨论的,当一个光刻工艺不能在电介质层中创建期望的图样时,使用SPSE工艺。SPSE工艺比可以通过使用一个光掩模创建的图像所实现的部件创建更加靠近且数量更多的部件。因此,SPSE工艺中图样化部件之间的距离可以小于一个光掩模中部件之间的最小间隔。因为部件的数量更多或更加靠近,所以在蚀刻工艺之后露出更多的超低k电介质表面。当被蚀刻工艺损坏时,较大的表面积容易吸收周围环境和湿式工艺中的湿气。传统的单独的热烘烤不能充分去除这些湿气,代替传统的热烘烤或除传统的热烘烤之外使用活化能辅助(AEA)烘烤。
返回参照图1,在操作19中,衬底被任选地经受初步热烘烤。初步热烘烤类似于传统的热烘烤,其中,衬底被加热到大约300至大约400摄氏度,或者大约350摄氏度持续几秒到几小时、或者大约1分钟。初步热烘烤去除了表面未结合湿气以及一些弱结合湿气,即,通过范德华力结合的湿气。
然后,在操作21中活化能辅助(AEA)烘烤衬底,以去除更多的结合湿气。AEA烘烤包括将衬底暴露给特定光辐射,同时保持衬底温度。在特定实施例中,AEA烘烤包括将衬底暴露给仅具有波长大于400nm或者波长仅在400nm和1000nm之间的光辐射。可通过加热器基座控制衬底温度。衬底被AEA烘烤至少1分钟,大约1至20分钟,或者大约10分钟。在AEA烘烤期间,衬底温度被上升并保持在大约350摄氏度,或者大约300至400摄氏度。
AEA烘烤和初步热烘烤可发生在相同腔室或不同腔室中。例如,在基座加热器上将衬底暴露给AEA光辐射之前在初步热烘烤条件下通过相同的基座加热器加热衬底。在其他实施例中,衬底可在湿式蚀刻之后立即被热烘烤并储存在储料器中直到AEA烘烤。发现AEA烘烤减少了电介质材料的后续湿气吸收性。换句话说,AEA烘烤具有损坏修复效果,其中,一些湿气吸收的地方在AEA烘烤之后失效,使得在AEA烘烤之后吸收更少的湿气。根据该特征,AEA烘烤可以在湿式工艺之后立刻执行,以减小电介质层的湿气吸收性。当然,AEA烘烤可以在用金属填充沟槽和通孔之前执行。在一些情况下,AEA烘烤可以在阻挡晶种层之前执行而不需要破坏真空。
然后,在操作23中,用金属填充衬底图样。金属通常为铜。铜填充包括阻挡晶种层和块填充。阻挡晶种层可包括多个薄层,包括衬垫层、阻挡层和晶种层。每个阻挡晶种层都可以使用已知的技术(诸如物理气相沉积(PVD)、化学气相沉积(CVD)或不太常用的电或无电沉积技术)来沉积。用于铜填充的阻挡晶种层通常包括除铜之外的材料。示例性材料包括钛、钽、钌、钴、钯、镍、铜和具有这些金属的组合物和合金(诸如氮化钽)。然后,用金属(可以为铜或其他常用的导体)填充图样。通常利用本领域已知的电化学电镀来实现块铜填充。
为了确保完全的填充,块填充工艺可以对图样的一些部分过量填充。在这种情况下,在操作25中对衬底进行图样化。图样化可以包括化学机械抛光(CMP)。在平面化期间,从露出一部分超低k电介质层的衬底表面去除过量金属。在CMP期间,衬底被置于浆环境中具有研磨表面的压盘上。CMP浆通常是水性的(water-based),并且包括以化学方法抛光衬底表面的化学物。随着铜被去除,露出的电介质表面从浆中吸收湿气。传统的干燥和热烘烤不能充分去除这些湿气,在特定实施例中还使用AEA烘烤。
衬底可以在操作27中进行AEA烘烤,以在CMP之后去除湿气。在CMP之后,代替传统的热烘烤或除传统的热烘烤之外,使用AEA烘烤。还在操作21中的金属填充之前代替传统的热烘烤或除传统的热烘烤之外使用AEA烘烤。至少一个AEA烘烤被用于在根据本发明的各个实施例的形成互连件的各个方法中去除湿气。在一些实施例中,在金属填充之前使用第一AEA烘烤,以及在平面化之后使用第二AEA烘烤。第一和第二AEA烘烤不需要具有相同的工艺条件。例如,第一AEA烘烤可以比第二AEA烘烤进行较长的持续时间或更高的温度。例如,第一AEA烘烤可以在350℃下持续10分钟,第二AEA烘烤可以在300℃下持续2分钟。
在另一方面中,本发明的各个实施例包括用于AEA烘烤的硬件。图3和图4示出了AEA烘烤室的不同实施例。在图3中,衬底61通过加热器基座63进行加热,并接收来自密封室67内的AEA光源组件65的辐射。腔室67还可以包括用于在AEA烘烤期间控制腔室67的压力和环境的气体入口69和泵出口71。例如,可以在诸如氮的惰性环境中以低于1个大气压的压力发生AEA烘烤。在一些情况下,AEA烘烤可以发生在包括氢或合成气体的环境中。在一些实施例中,腔室67包括可再生湿气的吸气剂,以利于湿气去除。
在图3的实施例中,AEA光源组件65包括一个或多个灯泡和光源,其能够以波长仅大于约400nm的电磁辐射照射衬底。AEA光源可包括一个或多个被设计为不发出短于约400nm波长的辐射的电灯泡。AEA光源可被设计为照射整个衬底或者仅照射衬底的一部分。在一些实施例中,AEA光源可以为一个或多个激光器,其发出大约在400nm和1000nm之间的一个或多个波长的辐射。例如,可以使用以458nm发出辐射的氩离子激光器或633nm的氦-氖激光器。为了照射整个衬底,一个或多个激光器可以扫描衬底的表面。可使用的各种灯泡的实例包括高强度放电(HID)灯泡和气体放电灯泡。HID灯泡的进一步实例包括纳蒸汽和金属卤化物灯泡。
AEA光源的能量与衬底上曝光的持续时间相关。AEA光源可以为大约0.5至10千瓦,或者至少500瓦以限制工艺时间。
在图4的实施例中,衬底73被置于密封室81内的基架75上。衬底通过室81外部的石英窗接收来自AEA光源组件91的辐射77。室81还可以包括用于在AEA烘烤期间控制室81的压力和环境的气体入口83和真空泵85。在一些实施例中,室81还包括可再生湿气的吸气剂,以利于湿气去除。
所示出的AEA光源组件还包括滤光器89。通过滤光器89过滤光源79发射的光,该滤光器去除一部分光防止所去除的部分到达衬底,使得整体上由整个AEA光源组件生成的光不包括短于400nm的波长。本领域的技术人员应该注意,石英窗87也可以是滤光器。形成具有滤光器特性的石英窗的已知方法包括在形成期间利用各种添加物掺杂石英。AEA光源组件还可以包括其他光学元件,包括反射器和透镜。例如,可以在本发明的一些实施例中使用排除长于大约1000nm波长的滤光器。
进行试验来比较各种烘烤处理之后的衬底。图5是各个衬底的傅里叶变换光谱IR(FTIP)数据。线101是沉积电介质层之后的结果。线103是来自在湿式蚀刻之后且在任何烘烤之前具有大多数湿气的衬底的结果。因此,线101和103是用于比较各种湿气去除烘烤的效率的基线。通常,曲线下方的区域代表湿气量,线101包含最少量的湿气。相信波数大于约3600的曲线下方的区域表示自由键的湿气,诸如Si-OH键。波数小于约3600的曲线下方的区域表示较弱结合(bond,或键)的湿气,诸如van der Wals键。
在下表中总结了用于生成数据的工艺条件:
线# | 先前工艺 | 烘烤条件 | 烘烤温度(℃) | 持续时间 |
101 | 沉积 | 无 | ||
103 | 湿式蚀刻 | 无 | ||
105 | 湿式蚀刻 | 单晶片烘烤 | 350 | 1分钟 |
107 | 湿式蚀刻 | 间歇式炉 | 300 | 1.5小时 |
109 | 湿式蚀刻 | AEA烘烤 | 350 | 1分钟 |
111 | 湿式蚀刻 | UV光+烘烤 | 350 | 1分钟 |
线105,单晶片烘烤,表示在烘烤之后具有大量湿气的衬底。线107,间歇式炉(batch furnace)烘烤,类似于线105。线109表示根据本发明一些实施例的工艺。线109和111示出了波数小于约3500的比较结果。在波数大于3600处,线111,UV光辅助烘烤,示出了比线109的衬底低的强度、总体要求较少的湿气。然而,如上所讨论的,暴露给UV光导致超低k膜中的交联,其改变膜的介电常数和部件的尺寸。在许多情况下,是不期望交联的。因此,线109的AEA烘烤去除了湿气,该湿气的去除可以与UV辅助烘烤相匹敌而不具有交联。
前面已经概述了若干实施例的特征,使得本领域的技术人员可以更好地理解上述详细描述。本领域的技术人员应该理解,他们可以容易地使用本公开作为设计或修改用于执行与本文所引入实施例相同的目的和/或实现相同优点的其他工艺和结构的基础。例如,不同于上述的室硬件设计可以适合于生成具有用于实践本发明的方法实施例的特定波长的光。然而,应该理解,这些优点并不是限制性的,而是其他实施例可提供其他优点。本领域的技术人员还应该意识到,这些等效限制并不背离本公开的精神和范围,并且在不背离本发明的精神和公开的情况下,他们可以进行各种改变、替换和变化。
Claims (17)
1.一种用于在衬底上形成互连件的方法,所述方法包括:
在所述衬底上沉积超低k电介质层;
在所述超低k电介质层中蚀刻第一图样;
通过将所述衬底暴露给仅具有大于400nm的波长的光来进行活化能辅助AEA烘烤;
用金属填充所述图样;以及
对所述金属进行平面化,以露出所述超低k电介质层的一部分,
其中,k值小于2.5。
2.根据权利要求1所述的方法,还包括:在平面化之后对所述衬底进行AEA烘烤。
3.根据权利要求1所述的方法,其中,在用金属填充所述图样之前执行对所述衬底进行活化能辅助AEA烘烤。
4.根据权利要求1所述的方法,还包括:在与蚀刻第一图样分离的蚀刻操作中,在所述超低k电介质层中蚀刻第二图样。
5.根据权利要求1所述的方法,还包括:在AEA烘烤之前初步烘烤,所述初步烘烤包括:将所述衬底加热到350摄氏度持续30秒至2分钟。
6.根据权利要求1所述的方法,其中,光强度从10W/cm2至500W/cm2。
7.根据权利要求1所述的方法,其中,所述光仅具有400nm和1000nm之间的波长。
8.根据权利要求6所述的方法,其中,AEA烘烤还包括:用热的方式加热所述衬底。
9.根据权利要求1所述的方法,其中,所述衬底的所述AEA烘烤被执行1至20分钟的时间。
10.根据权利要求1所述的方法,其中,所述AEA烘烤期间的衬底具有300至400摄氏度的温度。
11.根据权利要求1所述的方法,其中,所述AEA烘烤期间的衬底被加热到350摄氏度的温度。
12.根据权利要求1所述的方法,其中,衬底的所述AEA烘烤操作去除在所述超低k电介质层中吸收的一部分湿气。
13.根据权利要求1所述的方法,其中,所述平面化为化学机械抛光CMP。
14.一种用于在衬底上形成互连件的方法,所述方法包括:
在所述衬底上沉积超低k电介质层;
执行第一光刻工艺以形成第一图样;
在所述超低k电介质层中蚀刻所述第一图样;
执行第二光刻工艺以形成第二图样;
在所述超低k电介质层中蚀刻所述第二图样;
湿式清洁所述衬底;
在所述湿式清洁之后,通过将所述衬底暴露给仅具有大于400nm的波长的光来对所述衬底进行活化能辅助(AEA)烘烤;
用金属填充图样;以及
化学机械抛光所述金属,以露出所述超低k电介质层的一部分,
其中,k值小于2.5。
15.根据权利要求14所述的方法,还包括:在所述化学机械抛光之后,对所述衬底进行AEA烘烤。
16.根据权利要求15所述的方法,其中,光强度从10W/cm2至500W/cm2。
17.根据权利要求15所述的方法,其中,在所述湿式清洁之后用于AEA烘烤的工艺条件不同于在所述化学机械抛光之后用于AEA烘烤的工艺条件。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/893,399 | 2010-09-29 | ||
US12/893,399 US8481412B2 (en) | 2010-09-29 | 2010-09-29 | Method of and apparatus for active energy assist baking |
Publications (2)
Publication Number | Publication Date |
---|---|
CN102437102A CN102437102A (zh) | 2012-05-02 |
CN102437102B true CN102437102B (zh) | 2014-06-18 |
Family
ID=45871079
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201110268878.XA Active CN102437102B (zh) | 2010-09-29 | 2011-09-07 | 用于活化能辅助烘烤的方法和装置 |
Country Status (2)
Country | Link |
---|---|
US (2) | US8481412B2 (zh) |
CN (1) | CN102437102B (zh) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9390941B2 (en) * | 2009-11-17 | 2016-07-12 | Hitachi High-Technologies Corporation | Sample processing apparatus, sample processing system, and method for processing sample |
US8927909B2 (en) * | 2010-10-11 | 2015-01-06 | Stmicroelectronics, Inc. | Closed loop temperature controlled circuit to improve device stability |
US9196551B2 (en) | 2011-08-26 | 2015-11-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Automatically adjusting baking process for low-k dielectric material |
CN103374698A (zh) * | 2012-04-23 | 2013-10-30 | 北京北方微电子基地设备工艺研究中心有限责任公司 | 加热腔室以及等离子体加工设备 |
US9093265B2 (en) * | 2013-10-15 | 2015-07-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | High UV curing efficiency for low-k dielectrics |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1617323A (zh) * | 2003-11-13 | 2005-05-18 | 海力士半导体有限公司 | 用于形成半导体器件中的金属布线的方法 |
CN101621001A (zh) * | 2003-03-04 | 2010-01-06 | 气体产品与化学公司 | 通过紫外光辐射改善致密和多孔有机硅酸盐材料的机械性能 |
CN101816059A (zh) * | 2007-09-13 | 2010-08-25 | 东京毅力科创株式会社 | 使介电膜固化的方法 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5722162A (en) * | 1995-10-12 | 1998-03-03 | Fujitsu Limited | Fabrication procedure for a stable post |
JP3627011B2 (ja) * | 2001-02-13 | 2005-03-09 | インターナショナル・ビジネス・マシーンズ・コーポレーション | 接合方法 |
US6605413B1 (en) * | 2001-03-29 | 2003-08-12 | Advanced Micro Devices, Inc. | Chemical treatment to strengthen photoresists to prevent pattern collapse |
EP1304092B1 (en) * | 2001-10-22 | 2007-12-05 | Terumo Kabushiki Kaisha | Stent and method of producing the same |
US20080026579A1 (en) * | 2006-07-25 | 2008-01-31 | Kuo-Chih Lai | Copper damascene process |
US7919225B2 (en) * | 2008-05-23 | 2011-04-05 | International Business Machines Corporation | Photopatternable dielectric materials for BEOL applications and methods for use |
US8187897B2 (en) * | 2008-08-19 | 2012-05-29 | International Business Machines Corporation | Fabricating product chips and die with a feature pattern that contains information relating to the product chip |
US20100068897A1 (en) | 2008-09-16 | 2010-03-18 | Tokyo Electron Limited | Dielectric treatment platform for dielectric film deposition and curing |
-
2010
- 2010-09-29 US US12/893,399 patent/US8481412B2/en active Active
-
2011
- 2011-09-07 CN CN201110268878.XA patent/CN102437102B/zh active Active
-
2013
- 2013-06-11 US US13/915,287 patent/US9004914B2/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101621001A (zh) * | 2003-03-04 | 2010-01-06 | 气体产品与化学公司 | 通过紫外光辐射改善致密和多孔有机硅酸盐材料的机械性能 |
CN1617323A (zh) * | 2003-11-13 | 2005-05-18 | 海力士半导体有限公司 | 用于形成半导体器件中的金属布线的方法 |
CN101816059A (zh) * | 2007-09-13 | 2010-08-25 | 东京毅力科创株式会社 | 使介电膜固化的方法 |
Also Published As
Publication number | Publication date |
---|---|
CN102437102A (zh) | 2012-05-02 |
US9004914B2 (en) | 2015-04-14 |
US8481412B2 (en) | 2013-07-09 |
US20120077339A1 (en) | 2012-03-29 |
US20130273732A1 (en) | 2013-10-17 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN101828249B (zh) | 形成气隙结构的方法和*** | |
US10068765B2 (en) | Multi-step system and method for curing a dielectric film | |
KR101425332B1 (ko) | Uv 처리를 사용하는 탄소 함유 로우-k 유전율 복구 | |
TWI431689B (zh) | 介電膜之硬化方法 | |
CN102437102B (zh) | 用于活化能辅助烘烤的方法和装置 | |
US6444136B1 (en) | Fabrication of improved low-k dielectric structures | |
US6583067B2 (en) | Method of avoiding dielectric layer deterioration with a low dielectric constant | |
US20090227119A1 (en) | Method for curing a porous low dielectric constant dielectric film | |
TWI421939B (zh) | 多孔性低介電常數介電膜之硬化方法 | |
KR20110052436A (ko) | 반도체 공정의 k값 회복 및 표면 세정을 위한 uv 및 환원제 처리 | |
US7829268B2 (en) | Method for air gap formation using UV-decomposable materials | |
TW200836261A (en) | Method for selective removal of damaged multi-stack bilayer films | |
JP4359847B2 (ja) | 低k誘電体フィルムのための乾燥処理 | |
JP2010278121A (ja) | 半導体装置およびその製造方法 | |
KR101653907B1 (ko) | 경화 다공질 유전체로부터 다시 충전되는 기공 충전제를 제거하는 방법 | |
JP5565314B2 (ja) | 半導体装置の製造方法及びその製造装置 | |
KR20160011160A (ko) | Uv-경화된 초 저-k 유전체 필름들에 대한 탄성 계수 및 경도의 강화 | |
JP2007129003A (ja) | 半導体装置の製造方法および残留物質除去装置 | |
JPH10125571A (ja) | パターン形成方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant |