CN102436848A - Phase change storage cell-based nonvolatile T flip-flop circuit and implementation method thereof - Google Patents
Phase change storage cell-based nonvolatile T flip-flop circuit and implementation method thereof Download PDFInfo
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Abstract
The invention discloses a phase change storage cell-based nonvolatile T flip-flop circuit and an implementation method thereof. The phase change storage cell-based nonvolatile T flip-flop circuit comprises a T flip-flop element and a phase change storage cell which are connected in series, has the capacity of bit-level storage and recovery, can realize the function of a conventional T flip-flop, can enable the T flip-flop to save the current state thereof when power fails and return to the state before the power fails after the power is restored, and has the characteristics of not destroying the function of the conventional flip-flop and being compatible with the complementary metal oxide semiconductor (CMOS) process.
Description
Technical field
The present invention relates to a kind of integrated circuit, especially relate to a kind of non-volatile T flip-flop circuit and implementation method based on phase-changing memory unit.
Background technology
The T trigger is a kind of circuit unit in the digital circuit trigger.The T trigger has reset, set, maintenance and turn over function, and in practical application, it not only has very strong versatility, and can change the trigger of other types neatly.The T trigger is a kind of basic circuit that can store a bit sign indicating number, and it can keep " 1 " or " 0 " two stable status voluntarily, is called bistable circuit again.Under the different input signals effect, its output can be set to one state or " 0 " attitude, and after input signal disappeared, the new state that trigger obtains can keep.Trigger is one of device of widespread use in the digital circuit, in counter, intelligence question-and-answer game apparatus, computing machine, digital camera, digital audio deck, can both see it.And in VLSI Design, T trigger one of the primary element that is absolutely necessary.But common T trigger all can not keep its state under the state of power down.
The present invention has overcome the defective of T trigger meeting lossing signal under power-down state in the prior art, has proposed a kind of non-volatile T flip-flop circuit and its implementation based on phase-change memory cell.The non-volatile T trigger that the present invention is based on phase-change memory cell has the ability of position level storage and recovery; Can be when realizing traditional T trigger function; Can also make the T trigger when power down, preserve its current state, and can behind power up, return to the state before the power down.The present invention has and does not destroy original trigger function, with the characteristics of CMOS process compatible.
Summary of the invention
The present invention proposes a kind of non-volatile T flip-flop circuit, comprise T flip-flop element and phase-change memory cell based on phase-change memory cell; Said T trigger and said phase-change memory cell are connected in series.
Wherein, said T flip-flop element comprises output terminal, the output terminal of the two or three input nand gate, the output terminal of T trigger, the reversed-phase output of T trigger, two input nand gates, T trigger input end, the clock signal input terminal of the one or three input nand gate;
Said T trigger input end is connected with the input end of said the one or three input nand gate, the two or three input nand gate; Clock signal input terminal connects respectively at the input end of said the one or three input nand gate, the input end of the two or three input nand gate; The output terminal of said the one or three input nand gate is connected with the input end of the one or two input nand gate; The output terminal of said the two or three input nand gate is connected with the input end of the two or two input nand gate; The output terminal of said the one or two input nand gate is connected with the input end of the input end of said the two or three input nand gate, the two or two input nand gate, the output terminal of T trigger, and the output terminal of said the two or two input nand gate is connected with the input end of the input end of said the one or three input nand gate, the one or two input nand gate, the reversed-phase output of T trigger.
Wherein, said phase-change memory cell comprises phase change resistor and oxide-semiconductor control transistors;
The positive pole of said first phase change resistor is connected with the output terminal of said T trigger, the drain electrode of negative pole and said first oxide-semiconductor control transistors; The source electrode of said first oxide-semiconductor control transistors is connected with bit line, and grid is connected with recovery control signal end with said storage;
The positive pole of said second phase change resistor is connected with the reversed-phase output of said T trigger, and negative pole is connected with the drain electrode of said second oxide-semiconductor control transistors; The source electrode of said second oxide-semiconductor control transistors is connected with said antiposition line, and grid is connected with recovery control signal end with said storage.
Wherein, through program current the control of the grid of said oxide-semiconductor control transistors is realized the programming for said phase-change memory cell resistance value.
Wherein, it is characterized in that said T trigger can be JK flip-flop, d type flip flop or rest-set flip-flop.
Wherein, the phase-change material of said phase-change memory cell can be a Ge-Sb-Te, silicon antimony tellurium or aluminium antimony tellurium.
The present invention also proposes a kind of implementation method of the non-volatile T flip-flop circuit based on phase-change memory cell, comprising: steps A: storage data and/or step B: restore data.
Wherein, when the storage data:
Steps A 1: with said bit line and antiposition line ground connection, clock signal input terminal keeps low level state;
Steps A 2: said storage and recovery control signal end are controlled; Said first phase change resistor and second phase change resistor are programmed; When the state of said T trigger output terminal or T trigger reversed-phase output is high level; Coupled phase change resistor can be programmed, and another one remains unchanged;
Steps A 3: said bit line and antiposition line are connect high level simultaneously and control said storage and recovery control signal end; When the state of said T trigger output terminal or T trigger reversed-phase output is low level; Coupled phase change resistor can be programmed, and another one remains unchanged;
Steps A 4: said storage is made as low level with recovery control signal end accomplishes storing process.
Wherein, when restore data:
Step B1: clock signal input terminal keeps low level state;
Step B2: said bit line and antiposition line are carried out precharge, said storage and recovery control signal end are made as high level;
Step B3: the resistance states of said first phase change resistor and second phase change resistor carries out initialization to the output terminal and the T trigger reversed-phase output of said T trigger, recovers the preceding state of power down;
Step B4: said storage is made as low level with recovery control signal end accomplishes rejuvenation.
The non-volatile T trigger that the present invention is based on phase-change memory cell has the ability of position grade storage and recovery, can when realizing that traditional T trigger is preserved data, also can make the T trigger after power down, can return to power down state before.
Description of drawings
Fig. 1 is the logical circuitry of the non-volatile T flip-flop circuit based on phase-change memory cell of the present invention.
Fig. 2 is the truth table synoptic diagram of under the high level time clock, working of T trigger.
Fig. 3 the present invention is based on Sheffer stroke gate latch transistor level circuit diagram in the non-volatile T flip-flop circuit of phase-change memory cell.
Fig. 4 is the non-volatile T flip-flop circuit based on phase-change memory cell that utilizes asymmetric T trigger to constitute.
Embodiment
In conjunction with following specific embodiment and accompanying drawing, the present invention is done further detailed description, protection content of the present invention is not limited to following examples.Under spirit that does not deviate from inventive concept and scope, variation and advantage that those skilled in the art can expect all are included among the present invention, and are protection domain with the appending claims.
Shown in Fig. 1-4,1-T flip-flop element, 2-phase-change memory cell, the output terminal of 3-three input nand gates 12, the output terminal of 4-three input nand gates 13; The output terminal of 5-T trigger, the reversed-phase output of 6-T trigger, 7-phase change resistor, 8-phase change resistor, 9-oxide-semiconductor control transistors; The 10-oxide-semiconductor control transistors, 12-three input nand gates, 13-three input nand gates, 14-two input nand gates, 15-two input nand gates; The 16-PMOS transistor, 17-PMOS transistor, 18-PMOS transistor, 19-PMOS transistor; The 20-NMOS transistor, 21-NMOS transistor, 22-NMOS transistor, 23-NMOS transistor.
Non-volatile T flip-flop circuit based on phase-change memory cell of the present invention comprises: T flip-flop element 1, phase-change memory cell 2.T flip-flop element and phase-change memory cell are connected in series.Phase-change memory cell comprises 7,8 and two oxide-semiconductor control transistors 9,10 of two phase change resistors.T trigger elementary cell 1 can realize the normal logic function of T trigger, and phase-change memory cell 2 can be realized the storage of position level and the function of recovery,
Wherein, the phase-change material of phase-change memory cell can be a Ge-Sb-Te, silicon antimony tellurium or aluminium antimony tellurium.
Wherein, the T trigger can be JK flip-flop, d type flip flop or rest-set flip-flop.
As shown in Figure 1, connected mode is following:
T trigger input end is connected with the input end of three input nand gates 12, three input nand gates 13; Clock signal input terminal connects respectively at the input end of three input nand gates 12, the input end of three input nand gates 13; The output terminal 3 of three input nand gates 12 is connected with the input end of two input nand gates 14; The output terminal 4 of three input nand gates 13 is connected with the input end of two input nand gates 15; The output terminal of two input nand gates 14 is connected with the input end of three input nand gates 13, the input end of two input nand gates 15, the output terminal 5 of T trigger, and the output terminal of two input nand gates 15 is connected with the input end of three input nand gates 12, the input end of two input nand gates 14, the reversed-phase output 6 of T trigger.
The positive pole of phase change resistor 7 is connected with the output terminal 5 of T trigger, the drain electrode of the negative pole of phase change resistor 7 and oxide-semiconductor control transistors 9; The source electrode of oxide-semiconductor control transistors 9 is connected with bit line, and the grid of oxide-semiconductor control transistors 9 is connected with recovery control signal end WL with storage.
The positive pole of phase change resistor 8 is connected with the output terminal 6 of T trigger, and the negative pole of phase change resistor 8 is connected with the drain electrode of oxide-semiconductor control transistors 10; The source electrode of oxide-semiconductor control transistors 10 is connected with the antiposition line, and the grid of oxide-semiconductor control transistors 10 is connected with recovery control signal end WL with storage.
As shown in Figure 1, T is the input end of T trigger, and CLK is a clock signal input terminal, and WL is for storage and recover the control signal end, and QW is a bit line, and QBW is the antiposition line.Output terminal 5 and output terminal 6 are respectively two the reverse output Q and the QB of T trigger.When CLK input clock pulse signals " 1 "; When CLK clock input pulse signal " 0 ", three input nand gates 12,13 are by locked, and input signal changes does not have influence to the output of three input nand gates 12,13; Be always " 0 " or " 1 ", trigger is in the state of keeping.When CLK clock input pulse signal " 1 ", the T trigger is in running order.
Truth table when Fig. 2 is the T flip-flop operation, wherein Qn is the state of output terminal Q, Qn+1 is the next state of Qn.
If ortho states Qn is " 0 ", the output of two input nand gates 15 feeds back to three input nand gates, 12, three input nand gates 12 and is in closed state, and the output of two input nand gates 14 feeds back to three input nand gates, 13, three input nand gates 13 and is in opening.When input high level signal T (T=" 1 "), three input nand gates 13 are output as 0, three input nand gate 12 and are output as 0, and then Q is turned over by " 0 " and is " 1 ".
Likewise; When if ortho states Qn is " 1 ", the output of two input nand gates 15 feeds back to three input nand gates, 12, three input nand gates 12 and is in opening; The output of two input nand gates 14 feeds back to three input nand gates, 13, three input nand gates 13 and is in closed state.When T was " 1 ", trigger Q end was " 0 " by " 1 " upset.
Non-volatile T trigger storage and recover control signal end WL be low level when using as the T trigger with the T trigger is identical normally.
As shown in Figure 3, two input nand gates 14,15 in the T flip-flop element, T trigger output terminal 5,6, and phase-change memory cell 2 has constituted a non-volatile Sheffer stroke gate latch.Non-volatile Sheffer stroke gate storer can realize that the data of T trigger keep function, when power down, accomplishes data storage function simultaneously, when power up, accomplishes data recovery function.
The source electrode of PMOS transistor 16 is connected with positive source VDD, and grid is connected with the output terminal 3 of three input nand gates 12, and drain electrode is connected with the output terminal 5 of T trigger.The source electrode of PMOS transistor 17 is connected with positive source VDD, and grid is connected with the drain electrode of PMOS transistor 18, and drain electrode is connected with the output terminal 5 of T trigger.The source electrode of PMOS transistor 18 is connected with positive source VDD, and grid is connected with the drain electrode of PMOS transistor 17, and drain electrode is connected with the reversed-phase output 6 of T trigger.The source electrode of PMOS transistor 19 is connected with positive source VDD, and grid is connected with the output terminal 4 of three input nand gates 13, and drain electrode is connected with the reversed-phase output 6 of T trigger.The source electrode of nmos pass transistor 20 is connected with the drain electrode of nmos pass transistor 22, and grid is connected with the reversed-phase output 6 of T trigger, and drain electrode is connected with the output terminal 5 of T trigger.The source electrode of nmos pass transistor 21 is connected with the drain electrode of nmos pass transistor 23, and grid is connected with the output terminal 5 of T trigger, and drain electrode is connected with the reversed-phase output 6 of T trigger.The source electrode of nmos pass transistor 22 is connected with power cathode VSS, and grid is connected with the output terminal 3 of three input nand gates 12, and drain electrode is connected with the source electrode of nmos pass transistor 20.The source electrode of nmos pass transistor 23 is connected with power cathode VSS, and grid is connected with the output terminal 4 of three input nand gates 13, and drain electrode is connected with the source electrode of nmos pass transistor 21.The positive pole of phase change resistor 7 is connected with T trigger output terminal 5 in the phase-change memory cell 2, and the positive pole of phase change resistor 8 is connected with T trigger inverse output terminal 6.
The non-volatile T flip-flop circuit that the present invention is based on phase-change memory cell has the position level and stores and restore funcitons.With storage and recovery of Q=" 1 ", QB=" 0 " is example explanation storage and rejuvenation.
, may further comprise the steps when the storage data based on the non-volatile T flip-flop circuit of phase-change memory cell:
Steps A 1: with bit line and antiposition line ground connection, clock signal input terminal keeps low level state;
Steps A 2: storage and recovery control signal end are controlled; Phase change resistor 7 and phase change resistor 8 are programmed; When the state of T trigger output terminal 5 or T trigger reversed-phase output 6 was high level, coupled phase change resistor can be programmed, and another one remains unchanged;
Steps A 3: bit line and antiposition line are connect high level and control store and recovery control signal end simultaneously, and when the state of T trigger output terminal 5 or T trigger reversed-phase output 6 was low level, coupled phase change resistor can be programmed, and another one remains unchanged;
Steps A 4: will store with recovery control signal end and be made as low level completion storing process.
With storage Q=" 1 ", QB=" 0 " is example:
With bit line and antiposition line ground connection, clock signal input terminal power down simultaneously.When the output Q=" 1 " of output terminal 5, be high level, this moment, the oxide-semiconductor control transistors 9,10 of phase-change memory cell was opened, and based on the characteristic of phase-change material, can form on the phase change resistor 7 and become electric current, and electric current flows to QW from Q through phase change resistor 7, oxide-semiconductor control transistors 9.Through the voltage of control WL, can control current pulse shape through phase change resistor 7.Suppose that low resistance state is " 1 ", because the characteristic of phase-change material, phase change resistor 7 can be set to low resistance state by the suitable programmed electric current.Because QB=" 0 " does not have program current on the phase change resistor 8, remains unchanged.QWB and QW connect high level simultaneously, and WL still is a high level, the program current that on phase change resistor 8, also can form, and the program current on this electric current and the phase change resistor 7 is reverse, and phase change resistor 8 is changed to high-impedance state.
If same hypothesis high-impedance state is " 1 ", then phase change resistor 7 can be set to high-impedance state by the suitable programmed electric current, and phase change resistor 8 is changed to low resistance state.Whole like this storing process has just been accomplished.
, may further comprise the steps when the restore data based on the non-volatile T flip-flop circuit of phase-change memory cell:
Step B1: clock signal input terminal keeps low level state;
Step B2: pairs of bit line and antiposition line carry out precharge, will store and recover the control signal end and be made as high level;
Step B3: the resistance states of phase change resistor 7 and phase change resistor 8 carries out initialization to the output terminal 5 of T trigger with T trigger reversed-phase output 6, recovers the preceding state of power down;
Step B4: will store with recovery control signal end and be made as low level completion rejuvenation.
With recovery of Q=" 1 ", QB=" 0 " is example:
CLK keeps power-down state.QB, QBW are carried out precharge reach certain potentials, WL=" 1 ", transistor 9 and 10 is opened, and electric current flows to the Q end from the phase change resistor 7 of low resistance state, thus Q reverts to " 1 ".And for the high-impedance state of QBW, seldom electric current can flow to QB, and therefore, QB can be resumed and be " 0 ", and through bistable structure, Q and QB can be write as " 1 " and " 0 " respectively again.
If the hypothesis high-impedance state is " 1 " equally, QW, QBW connect the lowland during recovery, and this moment is meeting initialization Q=" 1 " equally, QB=" 0 ".The state control table of definition of two kinds of different logical states and storage and rejuvenation is as shown in table 1.
Table 1:
After resetting WL is changed to " 0 ", closes transistor 9,10, T trigger state before this is resumed like this, and the T trigger gets into normal logic function operation afterwards.
Whole like this rejuvenation has just been accomplished.Thereby the T trigger is still preserved data after having reached power down, returns to the effect of power down state before behind the power up.
The present invention also is applicable to other types T trigger, and the output terminal Q of other types T trigger is connected to phase change resistor 7 positive poles, and QB is connected to the positive pole of phase change resistor 8, and working method is identical.As Fig. 4 be asymmetric T trigger and phase-change memory cell form non-volatile T flip-flop circuit.The formation that non-volatile asymmetric T trigger is the T flip-flop element is slightly different with the foregoing description, and phase-change memory cell is identical with the annexation of T trigger and the process and the mechanism of recovery of stomge.
Claims (9)
1. the non-volatile T flip-flop circuit based on phase-change memory cell is characterized in that, comprises T flip-flop element (1) and phase-change memory cell (2); Said T trigger and said phase-change memory cell are connected in series.
2. according to claim 1 based on the non-volatile T flip-flop circuit of phase-change memory cell; It is characterized in that said T flip-flop element (1) comprises output terminal (3), the output terminal (4) of the two or three input nand gate (13), the output terminal (5) of T trigger, the reversed-phase output (6) of T trigger, two input nand gates (14,15), T trigger input end, the clock signal input terminal of the one or three input nand gate (12);
Said T trigger input end is connected with the input end of said the one or three input nand gate (12), the two or three input nand gate (13); Clock signal input terminal connects respectively at the input end of said the one or three input nand gate (12), the input end of the two or three input nand gate (13); The output terminal (3) of said the one or three input nand gate (12) is connected with the input end of the one or two input nand gate (14); The output terminal (4) of said the two or three input nand gate (13) is connected with the input end of the two or two input nand gate (15); The output terminal of said the one or two input nand gate (14) is connected with the input end of the input end of said the two or three input nand gate (13), the two or two input nand gate (15), the output terminal (5) of T trigger, and the output terminal of said the two or two input nand gate (15) is connected with the input end of the input end of said the one or three input nand gate (12), the one or two input nand gate (14), the reversed-phase output (6) of T trigger.
3. like the said non-volatile T flip-flop circuit of claim 2, it is characterized in that said phase-change memory cell (2) comprises phase change resistor (7,8) and oxide-semiconductor control transistors (9,10) based on phase-change memory cell;
The positive pole of said first phase change resistor (7) is connected with the output terminal (5) of said T trigger, the drain electrode of negative pole and said first oxide-semiconductor control transistors (9); The source electrode of said first oxide-semiconductor control transistors (9) is connected with bit line, and grid is connected with recovery control signal end with said storage;
The positive pole of said second phase change resistor (8) is connected with the reversed-phase output (6) of said T trigger, and negative pole is connected with the drain electrode of said second oxide-semiconductor control transistors (10); The source electrode of said second oxide-semiconductor control transistors (10) is connected with said antiposition line, and grid is connected with recovery control signal end with said storage.
4. according to claim 1 based on the non-volatile T flip-flop circuit of phase-change memory cell, it is characterized in that, the control of the grid of said oxide-semiconductor control transistors (9,10) is realized the programming for said phase-change memory cell resistance value through program current.
5. according to claim 1 based on the non-volatile T flip-flop circuit of phase-change memory cell, it is characterized in that said T trigger can be JK flip-flop, d type flip flop or rest-set flip-flop.
6. according to claim 1 based on the non-volatile T flip-flop circuit of phase-change memory cell, it is characterized in that the phase-change material of said phase-change memory cell can be a Ge-Sb-Te, silicon antimony tellurium or aluminium antimony tellurium.
7. according to claim 1 based on the implementation method of the non-volatile T flip-flop circuit of phase-change memory cell, it is characterized in that, comprising: steps A: storage data and/or step B: restore data.
8. like the implementation method of the said non-volatile T flip-flop circuit based on phase-change memory cell of claim 6, it is characterized in that, when the storage data:
Steps A 1: with said bit line and antiposition line ground connection, clock signal input terminal keeps low level state;
Steps A 2: said storage and recovery control signal end are controlled; Said first phase change resistor (7) and second phase change resistor (8) are programmed; When the state of said T trigger output terminal (5) or T trigger reversed-phase output (6) is high level; Coupled phase change resistor can be programmed, and another one remains unchanged;
Steps A 3: said bit line and antiposition line are connect high level simultaneously and control said storage and recovery control signal end; When the state of said T trigger output terminal (5) or T trigger reversed-phase output (6) is low level; Coupled phase change resistor can be programmed, and another one remains unchanged;
Steps A 4: said storage is made as low level with recovery control signal end accomplishes storing process.
9. like the implementation method of the said non-volatile T flip-flop circuit based on phase-change memory cell of claim 6, it is characterized in that, when restore data:
Step B1: clock signal input terminal keeps low level state;
Step B2: said bit line and antiposition line are carried out precharge, said storage and recovery control signal end are made as high level;
Step B3: the resistance states of said first phase change resistor (7) and second phase change resistor (8) carries out initialization to the output terminal (5) and the T trigger reversed-phase output (6) of said T trigger, recovers the preceding state of power down;
Step B4: said storage is made as low level with recovery control signal end accomplishes rejuvenation.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104282332A (en) * | 2013-07-10 | 2015-01-14 | 中国科学院上海微***与信息技术研究所 | Trigger circuit with real-time trigger state storage function |
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| US20050128791A1 (en) * | 2003-12-13 | 2005-06-16 | Hynix Semiconductor Inc. | Phase change resistor cell and nonvolatile memory device using the same |
| CN1647279A (en) * | 2002-04-10 | 2005-07-27 | 松下电器产业株式会社 | Non-volatile flip-flop |
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| CN1647279A (en) * | 2002-04-10 | 2005-07-27 | 松下电器产业株式会社 | Non-volatile flip-flop |
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| CN104282332A (en) * | 2013-07-10 | 2015-01-14 | 中国科学院上海微***与信息技术研究所 | Trigger circuit with real-time trigger state storage function |
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Application publication date: 20120502 |