[summary of the invention]
The invention provides a kind of high-voltage inversion protection circuit, the high-voltage output end+HV1 of inverter or+when HV2 open circuit, effectively protective circuit.
Technical scheme of the present invention is:
A kind of high-voltage inversion protection circuit, comprising: the first electric capacity, the second electric capacity, the 3rd electric capacity, the 4th electric capacity, the 5th electric capacity, the 6th electric capacity, the 7th electric capacity, the first resistance, the second resistance, the 3rd resistance, the 4th resistance, the first diode and the first voltage stabilizing didoe;
One of them high-voltage output end of one termination inverter of the first electric capacity, the other end is connected with another high-voltage output end of inverter with the 4th electric capacity by the second electric capacity, the 3rd electric capacity successively; The tie point ground connection of the second electric capacity and the 3rd electric capacity, the first resistance is connected with the second Capacitance parallel connection, and the second resistance is connected with the 3rd Capacitance parallel connection; One of them anodic bonding of the tie point of the first electric capacity and the second electric capacity and the first diode, the tie point of the 3rd electric capacity and the 4th electric capacity and another anodic bonding of the first diode, the negative electrode of the first diode is connected with the negative electrode of the first voltage stabilizing didoe and one end of the 5th electric capacity respectively, the other end ground connection of the 5th electric capacity, the anode of the first voltage stabilizing didoe is connected, passes through the 6th capacity earth by the 3rd resistance respectively with the tripod of chip UCC25600; The tripod of one chip termination UCC25600 of the 7th electric capacity, other end ground connection, the 4th resistance is connected with the 7th Capacitance parallel connection.
High-voltage inversion protection circuit of the present invention; the high-voltage output end+HV1 of inverter or+when HV2 open circuit; through the sampling of the first electric capacity, the second electric capacity, the 3rd electric capacity, the 4th electric capacity, the first resistance and the second resistance; to a high level signal of tripod input of chip UCC25600; now chip UCC25600 enters lock machine state; effectively protection half-bridge circuit and inverter, guarantees the normal work of circuit.
[embodiment]
Below in conjunction with accompanying drawing, specific embodiments of the invention are done to a detailed elaboration.
As Fig. 1, high-voltage inversion protection circuit of the present invention, comprising: the first capacitor C 1, the second capacitor C 2, the 3rd capacitor C 3, the 4th capacitor C 4, the 5th capacitor C 5, the 6th capacitor C 6, the 7th capacitor C 7, the first resistance R 1, the second resistance R 2, the 3rd resistance R 3, the 4th resistance R 4, the first diode D1 and the first voltage stabilizing didoe Z1;
One of them high-voltage output end+HV1 of one termination inverter of the first capacitor C 1, the other end is connected with another high-voltage output end+HV2 of inverter with the 4th capacitor C 4 by the second capacitor C 2, the 3rd capacitor C 3 successively; The tie point ground connection of the second capacitor C 2 and the 3rd capacitor C 3, the first resistance R 1 and the second capacitor C 2 are connected in parallel, and the second resistance R 2 and the 3rd capacitor C 3 are connected in parallel; The tie point VS1 of the first capacitor C 1 and the second capacitor C 2 is connected with one of them anode 1 of the first diode D1, the tie point VS2 of the 3rd capacitor C 3 and the 4th capacitor C 4 is connected with another anode 3 of the first diode D1, the negative electrode 2 of the first diode D1 is connected with the negative electrode 2 of the first voltage stabilizing didoe Z1 and one end of the 5th capacitor C 5 respectively, the other end ground connection of the 5th capacitor C 5, the anode 1 of the first voltage stabilizing didoe Z1 is connected, passes through the 6th capacitor C 6 ground connection by the 3rd resistance R 3 respectively with the tripod pin3 of chip UCC25600; The tripod pin3 of one chip termination UCC25600 of the 7th capacitor C 7, other end ground connection, the 4th resistance R 4 and the 7th capacitor C 7 are connected in parallel.
The high-voltage output end+HV1 of inverter or+when HV2 open circuit; through the sampling of the first capacitor C 1, the second capacitor C 2, the 3rd capacitor C 3, the 4th capacitor C 4, the first resistance R 1 and the second resistance R 2; to a high level signal of tripod pin3 input of chip UCC25600; now chip UCC25600 enters lock machine state; effectively protection half-bridge circuit and inverter, guarantees the normal work of circuit.
In addition, for prevent inverter high-voltage output end+HV1 and+HV2 opens a way simultaneously, as Fig. 2, the present invention also comprises the second diode D2, the 3rd diode D3, the 4th diode D4, the 5th diode D5, the 8th capacitor C 8, the 9th capacitor C 9, the tenth capacitor C the 10, the 11 capacitor C the 11, the 12 capacitor C the 12, the 13 capacitor C 13, the 5th resistance R 5, the 6th resistance R 6, the 7th resistance R 7, the 8th resistance R 8, the 9th resistance R 9, the tenth resistance R the 10, the 11 resistance R the 11, the 12 resistance R 12, NPN triode Q1 and a PNP triode Q2;
The anode 1 of the second diode D2 is connected with the tie point VS1 of the first capacitor C 1 and the second capacitor C 2, and the anode 1 of the 3rd diode D3 is connected with the tie point VS2 of the 3rd capacitor C 3 and the 4th capacitor C 4, the negative electrode 2 of the second diode D2 is connected with one of them negative electrode 3 of the 4th diode D4, one end of the 8th capacitor C 8, one end of the 12 resistance R 12 respectively, and the other end of the 12 resistance R 12 and the 8th capacitor C 8 is ground connection respectively, the negative electrode 2 of the 3rd diode D3 is connected with another negative electrode 1 of the 4th diode D4, one end of the 9th capacitor C 9, one end of the 5th resistance R 5 respectively, and the other end of the 5th resistance R 5 and the 9th capacitor C 9 is ground connection respectively, the anode 2 of the 4th diode D4 respectively with one end of the 6th resistance R 6, one end of the tenth capacitor C 10, one end of the 7th resistance R 7 connects, another termination power (shown in figure being+12V) of the 6th resistance R 6, the other end ground connection of the tenth capacitor C 10, the other end of the 7th resistance R 7 respectively with the base stage 1 of NPN triode Q1, one end of the 9th resistance R 9 connects, by the 12 capacitor C 12 ground connection, by the 8th resistance R 8 ground connection, emitter 3 ground connection of NPN triode Q1, collector electrode 2 by the 11 resistance R 11 respectively with one end of the 13 capacitor C 13, one end of the tenth resistance R 10 is connected with the base stage 1 of a PNP triode Q2, the other end of the 13 capacitor C 13 and the tenth resistance R 10 is connected with the emitter 3 of a PNP triode Q2 respectively, the emitter 3 of the one PNP triode Q2 connects power supply (shown in figure being+5V), the other end of the 9th resistance R 9 is connected with the collector electrode 2 of a PNP triode Q2, the anode 1 of the 5th diode D5, one end of the 11 capacitor C 11 respectively, the other end ground connection of the 11 capacitor C 11, the negative electrode 2 of the 5th diode D5 meets the tripod pin3 of chip UCC25600.
When the high-voltage output end+HV1 of inverter and+HV2 is while opening a way simultaneously, through the first capacitor C 1, the second capacitor C 2, the 3rd capacitor C 3, the 4th capacitor C 4, the sampling of the first resistance R 1 and the second resistance R 2, again through the second diode D2, the 3rd diode D3, the 8th capacitor C 8, the 9th capacitor C 9, the 12 resistance R 12, the AND circuit of the 5th resistance R 5 and the 4th diode composition, in the time that sampled signal VS1 and VS2 are high level simultaneously, trigger by the tenth capacitor C 10, the 7th resistance R 7, the 12 capacitor C 12, the 8th resistance R 8, the 9th resistance R 9, the 11 resistance R 11, the tenth resistance R 10, the 13 capacitor C 13, NPN triode Q1, the one PNP triode Q2, the 5th diode D5, the ghyristor circuit that the 11 capacitor C 11 forms, now the tripod pin3 of chip UCC25600 can input a voltage that is greater than 2V, make chip UCC25600 enter lock machine state, effectively protective circuit.
In order to prevent High voltage output arcing, as Fig. 3, the present invention also comprises: the 6th diode D6, the 7th diode D7, the 8th diode D8, the 13 resistance R the 13, the 14 resistance R the 14, the 15 resistance R the 15, the 16 resistance R the 16, the 17 resistance R the 17, the 14 capacitor C the 14, the 15 capacitor C 15 and the 2nd PNP triode Q3;
One end of the 14 resistance R 14 is connected with the tie point VS1 of the first capacitor C 1 and the second capacitor C 2, one end of the 13 resistance R 13 is connected with the tie point VS2 of the 3rd capacitor C 3 and the 4th capacitor C 4, the other end of the 13 resistance R 13 and the 14 resistance R 14 is connected with the anode 1 of the 6th diode D6 respectively, the negative electrode 2 of the 6th diode D6 respectively with one end of the 14 capacitor C 14, one end of the 15 resistance R 15, the anode 1 of the 7th diode D7, the emitter 3 of the 2nd PNP triode Q3 connects, the 14 capacitor C 14 and the other end of the 15 resistance R 15 and the negative electrode of the 7th diode D7 3 ground connection respectively, the collector electrode 2 of the 2nd PNP triode Q3 is connected with the tie point of the 7th resistance R 7 and the 12 capacitor C 12, the base stage 1 of the 2nd PNP triode Q3 is by the 16 resistance R 16 ground connection, the 15 capacitor C the 15 and the 17 resistance R 17 is connected between the emitter 3 and base stage 1 of the 2nd PNP triode Q3, the base stage 1 of the 2nd PNP triode Q3 is also connected with the negative electrode 2 of the 8th diode D8, and the anode of the 8th diode D8 is connected with the tie point of the 3rd resistance R 3 and the first voltage stabilizing didoe Z1.
When normal work, the voltage effective value of the high-voltage output end of inverter equates substantially, and the voltage of the 6th diode D6 the 2nd pin is 0V substantially, in the time that the high-voltage output end of inverter has arcing, can cause the variation of the high-voltage output end high pressure of inverter, the voltage of this variation can produce voltage signal at the 2nd pin of the 6th diode D6, this signal can be through the 14 capacitor C 14, the 15 resistance R 15, the rectification of the 7th diode D7 is clamped, the 15 capacitor C 15, the 17 resistance R 17, the time delay of the 16 resistance R 16, trigger the 2nd PNP triode Q3 conducting, then trigger the ghyristor circuit of NPN triode Q1 and PNP triode Q2 composition, now the 3rd pin of chip UCC25600 can be inputted a voltage that is greater than 2V, make chip UCC25600 enter lock machine state, high-tension circuit enters protection.
In addition, as Fig. 1, be also connected in parallel to filter capacitor C81 at the two ends of the 7th capacitor C 7, play filtering processing effect, prevent the interference of other signals.
Above-described embodiment of the present invention, does not form limiting the scope of the present invention.Any modification of doing within the spirit and principles in the present invention, be equal to and replace and improvement etc., within all should being included in claim protection range of the present invention.