CN102412180A - Semiconductor on insulator (SOI) substrate, semiconductor device with SOI substrate and forming methods for SOI substrate and semiconductor device - Google Patents
Semiconductor on insulator (SOI) substrate, semiconductor device with SOI substrate and forming methods for SOI substrate and semiconductor device Download PDFInfo
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- CN102412180A CN102412180A CN2010102915416A CN201010291541A CN102412180A CN 102412180 A CN102412180 A CN 102412180A CN 2010102915416 A CN2010102915416 A CN 2010102915416A CN 201010291541 A CN201010291541 A CN 201010291541A CN 102412180 A CN102412180 A CN 102412180A
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Abstract
The invention provides a method for forming a semiconductor on insulator substrate and a structure of the semiconductor on insulator substrate. The method comprises the following steps of: A, providing a first semiconductor wafer, wherein the first semiconductor wafer comprises a first surface and a second surface which are opposite to each other; B, etching the first surface to ensure that at least two flat regions are formed on the first semiconductor wafer, wherein each flat region has a uniform thickness, and the flat regions totally have at least two kinds of the thicknesses; C, forming a first insulation layer on the first surface, wherein the first insulation layer covers the flat regions so as to form a flat surface; and D, bonding a second semiconductor wafer on the first insulation layer. By forming the semiconductor on insulator substrate which comprises two flat regions with at least two kinds of thicknesses, a partially-depleted semiconductor on insulator (PDSOI) device and a fully-depleted semiconductor on insulator (FDSOI) device are integrated on the same chip, and the performance of an integrated circuit can be enhanced conveniently.
Description
Technical field
The present invention relates to semiconductor design and manufacturing field thereof, particularly a kind of SOI (Semiconductor on Insulator, semiconductor-on-insulator) substrate with have semiconductor device of SOI substrate and forming method thereof.
Background technology
Along with the sustainable development of semiconductor technology, SOI technology is owing to significantly improving device and performance of integrated circuits enjoys favor.So-called SOI technology is about to MOSFET (mos field effect transistor) device and is formed on the semiconductive thin film that is positioned on the insulator.As shown in Figure 1, a typical SOI substrate comprises Semiconductor substrate 10 (like body silicon), insulating barrier 20 (like the oxygen buried layer silica) and semiconductive thin film 30 (like activated silica) from bottom to up successively, and wherein, active silicon layer can embed shallow trench isolation from (STI) 40.
Two kinds of SOI devices are arranged at present: PD SOI (PDSOI, partially-depleted SOI) device and complete depletion type SOI (FDSOI, fully-depleted SOI) device.Wherein, than the FDSOI device, the PDSOI device need form thicker semiconductive thin film in substrate.Two kinds of each tool advantages of SOI device are beneficial to the enhancing performance of integrated circuits so the two is integrated in the same chip.Patent " Semiconductor-on-insulator chip incorporating partially-depleted; fully-depleted; and multiple gate devices; US 6720619 B1 " and " Method of fabricating a combined fully-depleted silicon-on-insulator (FDSOI) and partially-depleted silicon-on-insulator (PDSOI) devices, US 7198993B2 " have disclosed integrated PDSOI and FDSOI device respectively in the method for same chip.But owing to be difficult to realize that based on existing soi wafer and technology this is integrated, remain one of this hot research fields so how PDSOI device and FDSOI device are integrated in the same chip.
Summary of the invention
The object of the invention is intended to solve the problems of the technologies described above at least, has particularly solved PDSOI device and FDSOI device are integrated in the same chip.
For achieving the above object, on the one hand, the present invention proposes a kind of formation method of SOI substrate; It is characterized in that; May further comprise the steps: A. provides first semiconductor wafer, and said first semiconductor wafer comprises first surface and second surface, and said first surface is relative with said second surface; B. the said first surface of etching, so that first semiconductor wafer forms at least two flat regions, wherein, each said flat region has homogeneous thickness, said flat region comprises at least two kinds of said thickness altogether; C. form first insulating barrier at said first surface, said first insulating barrier covers said flat region and forms the surface of planarization; D. bonding second semiconductor wafer on said first insulating barrier.
Alternatively, before key and said second semiconductor wafer or after, also comprise: embed isolated groove at said first semiconductor wafer.
On the other hand, the present invention proposes a kind of method that on above-mentioned SOI substrate, forms semiconductor device, comprising: on said first semiconductor wafer, form a plurality of semiconductor device, each said device is positioned on the single said flat region.
Wherein, Above-mentioned formation SOI substrate and on said SOI substrate, forming in the method for semiconductor device; Alternatively; Be included in said first semiconductor wafer step that embeds isolated groove, this step can be before said second semiconductor wafer of bonding or after, perhaps after forming said semiconductor device, carry out.
On the one hand, the present invention proposes a kind of SOI substrate, it is characterized in that again; Comprise: first semiconductor layer, second semiconductor layer and first insulating barrier, wherein, said first insulating barrier is between said first semiconductor layer and second semiconductor layer; And said first semiconductor layer comprises at least two flat regions; Wherein, each said flat region has homogeneous thickness, and said flat region comprises at least two kinds of said thickness altogether.
Alternatively, be formed with isolated groove in said first semiconductor layer.
On the one hand, the present invention proposes a kind of semiconductor device that is formed on the said SOI substrate, it is characterized in that, comprises a plurality of semiconductor device again, and each said device is positioned on the single said flat region.
The present invention proposes a kind of SOI substrate and is formed on semiconductor device on the SOI substrate and forming method thereof, has realized PDSOI device and FDSOI device are integrated in the same chip, thereby has been beneficial to the enhancing performance of integrated circuits.
Aspect that the present invention adds and advantage part in the following description provide, and part will become obviously from the following description, or recognize through practice of the present invention.
Description of drawings
Above-mentioned and/or additional aspect of the present invention and advantage are from obviously with easily understanding becoming the description of embodiment below in conjunction with accompanying drawing, and accompanying drawing of the present invention is schematically, does not therefore draw in proportion.Wherein:
Fig. 1 is the SOI substrat structure sketch map of prior art;
Fig. 2-5 is the intermediate steps and the structural representation thereof of the SOI substrate of the formation embodiment of the invention;
Fig. 6 is the structural representation that on SOI substrate shown in Figure 5, forms semiconductor device of the embodiment of the invention.
Embodiment
Describe embodiments of the invention below in detail, the example of said embodiment is shown in the drawings, and wherein identical from start to finish or similar label is represented identical or similar elements or the element with identical or similar functions.Be exemplary through the embodiment that is described with reference to the drawings below, only be used to explain the present invention, and can not be interpreted as limitation of the present invention.
Disclosing of hereinafter provides many various embodiment or example to be used for realizing different structure of the present invention.Of the present invention open in order to simplify, hereinafter the parts and the setting of specific examples are described.Certainly, they only are example, and purpose does not lie in restriction the present invention.In addition, the present invention can be in different examples repeat reference numerals and/or letter.This repetition is in order to simplify and purpose clearly, itself not indicate the relation between various embodiment that discuss of institute and/or the setting.In addition, various specific technology and the examples of material that the invention provides, but those of ordinary skills can recognize the use of the applicability and/or the other materials of other technologies.In addition; First characteristic of below describing second characteristic it " on " structure can comprise that first and second characteristics form the embodiment of direct contact; Can comprise that also additional features is formed on the embodiment between first and second characteristics, such first and second characteristics possibly not be direct contacts.
Fig. 2-5 shows the intermediate steps sketch map of the method for the SOI substrate that forms the embodiment of the invention, below will be described with reference to the accompanying drawings the method for optimizing of the embodiment of the invention and the device architecture that obtains thus.
Steps A: first semiconductor wafer 100 is provided, two apparent surfaces of first semiconductor wafer 100 are defined as first surface 100A and second surface 100B respectively, as shown in Figure 2.Substrate 100 is an example with body silicon, in the practice, can comprise any suitable semiconductor substrate materials, specifically can be but is not limited to silicon, germanium, SiGe, carborundum, GaAs or any III/V compound semiconductor etc.According to the known designing requirement of prior art (for example p type substrate or n type substrate), substrate 100 can comprise various doping configurations.
Step B: etching first surface 100A, so that first semiconductor wafer 100 forms at least two flat regions, wherein, each said flat region has homogeneous thickness, said flat region comprises at least two kinds of said thickness altogether.The etching of this step is equivalent on same chip different semiconductor layer (body silicon layer) thickness of definition, is example (shown in arrow among the figure) with two thickness among Fig. 3.Wherein, thin flat region 300 is the FDSOI device area, and thicker flat region 200 is the PDSOI device area, and flat region 300 has the uniform thickness in the fabrication error allowed band respectively with flat region 200.Certainly, can design a plurality of different thickness according to actual needs, a plurality of to form in order to carry the zone of FDSOI device or PDSOI device.
Step C: form the surface that first insulating barrier, 400, the first insulating barriers 400 cover said flat region and form planarization at first surface 100A, as shown in Figure 4.The material of first insulating barrier 400 comprises Si
3N
4, SiO
2, any one or more the combination among SiOF, SiCOH, SiO, SiCO, SiCON and the SiON, the embodiment of the invention is with SiO
2Be example.The deposition of first insulating barrier 400 can adopt conventional depositing operation, for example pulsed laser deposition (PLD),, atomic layer deposition (ALD), plasma enhanced atomic layer deposit (PEALD) or other suitable methods.Preferably, form first insulating barrier 400 after, planarization is carried out on its surface, like chemico-mechanical polishing (CMP).
Step D: bonding second semiconductor wafer 500 on first insulating barrier 400, thus be formed on the SOI substrate that the top body silicon layer has at least two flat region thickness, as shown in Figure 5.Second semiconductor wafer 500 can comprise any suitable semiconductor substrate materials, can be with reference to the selecting for use of the aforementioned first semiconductor die sheet material, and the embodiment of the invention is an example with body silicon still.Be pointed out that, for reducing thermal expansion mismatch, improve bond strength, before bonding, can take in the following dual mode any one that second semiconductor wafer surface is carried out preliminary treatment.Method one: on second semiconductor wafer 500, form second insulating barrier 600; Then second insulating barrier 600 is bonded on first insulating barrier 400; Wherein, The formation method of second insulating barrier 600 and material are selected all can be with reference to first insulating barrier 400, and to form and first insulating barrier, 400 identical materials are preferred version, second insulating barrier 600 of present embodiment is SiO
2Method two: oxidation second semiconductor wafer 500 (serves as that description is easy to form oxide layer 600 on its surface; Said second insulating barrier and oxide layer all indicate with 600 among Fig. 5); Then oxide layer 600 is bonded on first insulating barrier 400, wherein, the formation method of oxide layer 600 can be a thermal oxidation method; In the present embodiment because second semiconductor wafer adopts body silicon, so oxidation generation SiO
2
Alternatively, can after forming said flat region, and then in first semiconductor wafer 100, form embedded isolated groove, to isolate the different components that will form; Also can after whole SOI substrate forms, before bonding second semiconductor wafer 600, in first semiconductor wafer 100, form embedded isolated groove; Can also after bonding second semiconductor wafer 600, in first semiconductor wafer 100, form embedded isolated groove.For for simplicity, not shown isolated groove among Fig. 3 to Fig. 5.The formation of isolated groove can be adopted at present or the method well known in the art that possibly occur in the future, and for example shallow trench isolation is from the technology of (STI), and the present invention does not limit this.
So far, just formed the SOI substrate that comprises FDSOI and PDSOI device area simultaneously, as shown in Figure 5; Comprise: first semiconductor layer 100, second semiconductor layer 500 and first insulating barrier 400; Wherein, said first insulating barrier 400 is between said first semiconductor layer 100 and second semiconductor layer 500, and said first semiconductor layer 500 comprises at least two flat regions; Flat region 200 and flat region 300 as shown in Figure 5; Wherein, each said flat region has the uniform thickness in the fabrication error allowed band, and said flat region comprises at least two kinds of said thickness altogether.As shown in Figure 5, thicker flat region 200 is the PDSOI device area, and thin flat region 300 is the FDSOI device area.According to actual needs, first semiconductor layer 100 can comprise the flat region of two above different-thickness, thereby forms a plurality of corresponding FDSOI and PDSOI device area.Wherein, first semiconductor layer 100 and second semiconductor layer 500 can comprise any suitable semi-conducting material, specifically can be but are not limited to silicon, germanium, SiGe, carborundum, GaAs or any III/V compound semiconductor etc.; The material of first insulating barrier 400 comprises Si
3N
4, SiO
2, any one or more the combination among SiOF, SiCOH, SiO, SiCO, SiCON and the SiON.
Preferably, accompany second insulating barrier, 600, the second insulating barriers 600 between first insulating barrier 400 and second semiconductor layer 500 and comprise Si
3N
4, SiO
2, any one or more the combination among SiOF, SiCOH, SiO, SiCO, SiCON and the SiON.
Alternatively, comprise the trench isolations that embeds first semiconductor layer 100, Fig. 5 is not shown.
The present invention also further proposes on above-mentioned SOI substrate, to form the method for semiconductor device, and this method comprises: the SOI substrate with formation shown in Figure 5 is the basis, on its first semiconductor wafer 100, forms a plurality of semiconductor device; Each said device is positioned on the single said flat region; As shown in Figure 6, be example with four devices among the figure, be designated as 700A, 700B, 700C, 700D respectively; All devices all are positioned on the second surface 100B of said first semiconductor wafer 100; And device 700A and 700D are positioned at flat region 200, and device 700A and 700D can be the PDSOI device, and device 700B and 700C are positioned at flat region 300; Device 700B and 700C can be the FDSOI device, have so just realized PDSOI device and FDSOI device are integrated on the same chip.Need explanatorily be, the present invention limit the concrete device architecture that is formed on the said SOI substrate, and all integrated circuit structures existing and that possibly occur in the future all are included within protection scope of the present invention.Particularly, can comprise the MOS device, for example can be fin formula field effect transistor (FinFET).
Be pointed out that alternatively, the step of isolated groove also can be carried out after forming each said semiconductor device.As shown in Figure 6, preferably, isolated groove 800 can run through top body silicon layer (first semiconductor wafer 100), to strengthen isolation effect.
The method that on SOI substrate shown in Figure 5, forms semiconductor device according to above embodiment of the invention proposition; Can obtain semiconductor device structure as shown in Figure 6; Comprise a plurality of semiconductor device, each device is positioned on the single flat region like the described SOI substrate of Fig. 5.As shown in Figure 6, be example with four devices among the figure, be designated as 700A, 700B, 700C, 700D respectively; All devices all are positioned on the second surface 100B of said first semiconductor wafer 100; And device 700A and 700D are positioned at flat region 200, and device 700A and 700D can be the PDSOI device, and device 700B and 700C are positioned at flat region 300; Device 700B and 700C can be the FDSOI device, and PDSOI device and FDSOI device that promptly said semiconductor device structure comprises are formed on the same chip.Wherein said device can comprise the MOS device, for example can be fin formula field effect transistor (FINFET).Alternatively, first semiconductor layer 500 of SOI substrate comprises embedded isolated groove 800, and preferably, isolated groove 800 runs through first semiconductor wafer 100, is beneficial to strengthen isolation effect.
The present invention proposes a kind of SOI substrate and is formed on semiconductor device on the SOI substrate and forming method thereof, has realized PDSOI device and FDSOI device are integrated in the same chip, thereby has been beneficial to the enhancing performance of integrated circuits.
Although illustrated and described embodiments of the invention; For those of ordinary skill in the art; Be appreciated that under the situation that does not break away from principle of the present invention and spirit and can carry out multiple variation, modification, replacement and modification that scope of the present invention is accompanying claims and be equal to and limit to these embodiment.
Claims (14)
1. the formation method of a semiconductor-on-insulator substrate is characterized in that, may further comprise the steps:
A., first semiconductor wafer is provided, and said first semiconductor wafer comprises first surface and second surface, and said first surface is relative with said second surface;
B. the said first surface of etching, so that first semiconductor wafer forms at least two flat regions, wherein, each said flat region has homogeneous thickness, said flat region comprises at least two kinds of said thickness altogether;
C. form first insulating barrier at said first surface, said first insulating barrier covers said flat region and forms the surface of planarization;
D. bonding second semiconductor wafer on said first insulating barrier.
2. formation method as claimed in claim 1 is characterized in that, said step D comprises:
On said second semiconductor wafer, form second insulating barrier;
Said second insulating barrier is bonded on said first insulating barrier.
3. formation method as claimed in claim 2 is characterized in that, said second insulating barrier comprises Si
3N
4, SiO
2, any one or more the combination among SiOF, SiCOH, SiO, SiCO, SiCON and the SiON.
4. formation method as claimed in claim 1 is characterized in that, said step D comprises:
Said second semiconductor wafer of oxidation is to form oxide layer on its surface;
Said oxide layer is bonded on said first insulating barrier.
5. formation method as claimed in claim 1 is characterized in that, said first insulating barrier comprises Si
3N
4, SiO
2, any one or more the combination among SiOF, SiCOH, SiO, SiCO, SiCON and the SiON.
6. formation method as claimed in claim 1 is characterized in that, before said second semiconductor wafer of bonding or after, also comprise: embed isolated groove at said first semiconductor wafer.
7. method that forms semiconductor device on like each described semiconductor-on-insulator substrate of claim 1-6; It is characterized in that; Comprise: on said first semiconductor wafer, form a plurality of semiconductor device, each said device is positioned on the single said flat region.
8. a method that forms semiconductor device on like each described semiconductor-on-insulator substrate of claim 1-5 is characterized in that, comprising:
On said first semiconductor wafer, form one or more semiconductor device, each said device is positioned on the single said flat region;
Embed isolated groove at said first semiconductor wafer.
9. a semiconductor-on-insulator substrate is characterized in that, comprising: first semiconductor layer, second semiconductor layer and first insulating barrier; Wherein, Said first insulating barrier is between said first semiconductor layer and second semiconductor layer, and said first semiconductor layer comprises at least two flat regions, wherein; Each said flat region has homogeneous thickness, and said flat region comprises at least two kinds of said thickness altogether.
10. semiconductor-on-insulator substrate as claimed in claim 9 is characterized in that, and also accompanies second insulating barrier between said first insulating barrier and said second semiconductor layer.
11. semiconductor-on-insulator substrate as claimed in claim 10 is characterized in that, said second insulating barrier comprises Si
3N
4, SiO
2, any one or more the combination among SiOF, SiCOH, SiO, SiCO, SiCON and the SiON.
12. semiconductor-on-insulator substrate as claimed in claim 9 is characterized in that, is formed with isolated groove in said first semiconductor layer.
13. formation method as claimed in claim 9 is characterized in that, said first insulating barrier comprises Si
3N
4, SiO
2, any one or more the combination among SiOF, SiCOH, SiO, SiCO, SiCON and the SiON.
14. one kind is formed on like the semiconductor device structure on each described semiconductor-on-insulator substrate of claim 9-13, it is characterized in that, comprise a plurality of semiconductor device, each said device is positioned on the single said flat region.
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| CN2010102915416A CN102412180A (en) | 2010-09-25 | 2010-09-25 | Semiconductor on insulator (SOI) substrate, semiconductor device with SOI substrate and forming methods for SOI substrate and semiconductor device |
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| CN2010102915416A CN102412180A (en) | 2010-09-25 | 2010-09-25 | Semiconductor on insulator (SOI) substrate, semiconductor device with SOI substrate and forming methods for SOI substrate and semiconductor device |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103208737A (en) * | 2012-12-20 | 2013-07-17 | 上海显恒光电科技股份有限公司 | Manufacturing method for ultraviolet light output screen and manufactured ultraviolet light output screen and application |
| US9899415B1 (en) | 2016-08-17 | 2018-02-20 | International Business Machines Corporation | System on chip fully-depleted silicon on insulator with rf and mm-wave integrated functions |
| CN113658624A (en) * | 2021-09-03 | 2021-11-16 | 广东省大湾区集成电路与***应用研究院 | Semiconductor memory and memory array |
| US11670503B2 (en) * | 2015-03-20 | 2023-06-06 | Lam Research Corporation | Method of atomic layer deposition |
| CN113658624B (en) * | 2021-09-03 | 2024-05-31 | 广东省大湾区集成电路与***应用研究院 | Semiconductor memory and memory array |
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| US6492209B1 (en) * | 2000-06-30 | 2002-12-10 | Advanced Micro Devices, Inc. | Selectively thin silicon film for creating fully and partially depleted SOI on same wafer |
| CN1851930A (en) * | 2006-04-11 | 2006-10-25 | 北京大学深圳研究生院 | Partial consumption SOI MOS transistor and making method |
| US20070099372A1 (en) * | 2005-10-31 | 2007-05-03 | Sailesh Chittipeddi | Device having active regions of different depths |
-
2010
- 2010-09-25 CN CN2010102915416A patent/CN102412180A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6492209B1 (en) * | 2000-06-30 | 2002-12-10 | Advanced Micro Devices, Inc. | Selectively thin silicon film for creating fully and partially depleted SOI on same wafer |
| US20070099372A1 (en) * | 2005-10-31 | 2007-05-03 | Sailesh Chittipeddi | Device having active regions of different depths |
| CN1851930A (en) * | 2006-04-11 | 2006-10-25 | 北京大学深圳研究生院 | Partial consumption SOI MOS transistor and making method |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103208737A (en) * | 2012-12-20 | 2013-07-17 | 上海显恒光电科技股份有限公司 | Manufacturing method for ultraviolet light output screen and manufactured ultraviolet light output screen and application |
| US11670503B2 (en) * | 2015-03-20 | 2023-06-06 | Lam Research Corporation | Method of atomic layer deposition |
| US9899415B1 (en) | 2016-08-17 | 2018-02-20 | International Business Machines Corporation | System on chip fully-depleted silicon on insulator with rf and mm-wave integrated functions |
| US10217766B2 (en) | 2016-08-17 | 2019-02-26 | International Business Machines Corporation | System on chip fully-depleted silicon on insulator with RF and MM-wave integrated functions |
| CN113658624A (en) * | 2021-09-03 | 2021-11-16 | 广东省大湾区集成电路与***应用研究院 | Semiconductor memory and memory array |
| CN113658624B (en) * | 2021-09-03 | 2024-05-31 | 广东省大湾区集成电路与***应用研究院 | Semiconductor memory and memory array |
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Application publication date: 20120411 |