CN102411983A - Random access memory powered according to data dynamics - Google Patents
Random access memory powered according to data dynamics Download PDFInfo
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- CN102411983A CN102411983A CN2010102959005A CN201010295900A CN102411983A CN 102411983 A CN102411983 A CN 102411983A CN 2010102959005 A CN2010102959005 A CN 2010102959005A CN 201010295900 A CN201010295900 A CN 201010295900A CN 102411983 A CN102411983 A CN 102411983A
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Abstract
The invention provides a random access memory powered according to data dynamics. The random access memory has a plurality of memory cells. In one embodiment, memory cells arranged at a same column are coupled with a same contraposition line and correspond to a same power supply circuit. Each memory cell is provided with two inverters, and a power supply circuit is provided with two power switches. To all the memory cells at a same column, two power switches can carry out independent power supply control for two inverters in each memory cell respectively according to the voltage of a bit line, i.e., desired write data of the bit line during write operation. The invention enables both read and write-in of the random access memory to be attended.
Description
Technical field
The present invention relates to a kind of RAS, and be particularly related to and a kind ofly two phase inverters in the same row static storage cell carried out independently-powered control respectively to take into account the RAS of readwrite performance to classify the basis as.
Background technology
RAS for example is a static RAM, is one of most important construction assembly of contemporary electronic systems.The layout area of reduction RAS, reduction RAS WV then are the development trends of modern RAS to improve power consumption dissipating bind structure.
RAS is provided with and a plurality ofly follows row (column), row (row) is arranged as the storage unit of matrix, and each cell stores one digit number supplies access according to this.For instance, (6transistors 6T) has two phase inverters and two gateway transistors to six basic transistors in the static storage cell, each phase inverter is formed by a pair of complementary transistor respectively.Wherein, the output terminal of a phase inverter couples the input end of another phase inverter, forms the breech lock framework of latch data; And the output terminal of two phase inverters can be considered a pair of back end, writes down one data and its anti-phase respectively with differential form.In each storage unit of same row, a pair of back end of each storage unit couples via a gateway transistor respectively with in the pair of bit lines one of them separately.In the storage unit with delegation, the gateway transistor of each storage unit then couples same character line in grid, makes each gateway transistor according to the conducting between the Control of Voltage corresponding data node of character line and corresponding bit line.In addition, five transistors (5transistors, storage unit 5T) and eight transistors (8transistors, storage unit 8T) are also arranged.A gateway transistor only is set in five transistor cells, and each storage unit of same row is only via single bit line access.Eight transistorized storage unit are in order to realize even port (dual-port) or dual-port (two-port) RAS, and each storage unit can be carried out access by two pairs of bit line.Be provided with two pairs of gateway transistors in eight transistor cells, each to the gateway transistor according to control whether conducting to a pair of corresponding bit lines of two back end respectively with the voltage of a pair of character line.
RAS can be described below the access running of storage unit.In the time will reading the data of a certain storage unit, corresponding bit lines can be precharged to the high voltage of logical one earlier.Read Qi Shishi, a data node of storage unit can be by corresponding gateway transistor turns to this bit line; If what this back end stored is the logical zero of low-voltage, the phase inverter that the voltage of this bit line will be stored in the unit drags down, with the data content of reflection logical zero.When reading when not beginning as yet, the not conducting of gateway transistor, this back end is with stored logic 0 by n channel metal oxide semiconductor transistor conducting to the low-voltage in the phase inverter.But, when reading Qi Shihou, because this back end can be separately by the bit line of gateway transistor turns to high voltage, therefore the voltage of this back end can raise.Say that equivalently when reading when beginning to carry out, the n channel metal oxide semiconductor transistor in the gateway transistor AND gate phase inverter can carry out dividing potential drop as dividing point with this back end between logical one high voltage and logical zero low-voltage.If the voltage of this back end is drawn high too high; Will surpass the escape voltage (trip voltage) of storage unit breech lock framework and be stored the unit and think logical one by mistake, and be logical one with the data of this back end by the logical zero upset by error via the feedback mechanism of latch circuit.In order to prevent to cause wrong data upset when the reading of data, when realizing storage unit, can adopt usually one weak (raceway groove is long or narrow, the conducting degree is relatively poor, source electrode and drain between conducting resistance bigger) the gateway transistor; Thus; When reading when carrying out; N channel metal oxide semiconductor transistor in the phase inverter has lower resistance relatively, and the voltage ratio that can make this back end is near the low-voltage of logical zero, and keeps bigger noise immunity (margin) with escape voltage.
More weak gateway transistor helps data and reads, and can cause negative influence but data are write.For example, in the time will low logic voltage 0 being write to a back end of a certain storage unit via a bit line, this back end can be by the gateway transistor turns to this bit line, makes the voltage of this back end can reach the low-voltage of logical zero.Suppose this back end originally by the p channel metal oxide semiconductor transistor conducting in the phase inverter to high voltage and stored logic 1; In the time will logical zero being write to this back end, the p channel metal oxide semiconductor transistor in the gateway transistor AND gate phase inverter of conducting is in this back end dividing potential drop.If the gateway transistor a little less than, the voltage of this back end will be difficult for being pulled low to the low-voltage of logical zero comparatively near the high voltage of logical one.Say that equivalently when logical zero was write the back end of logical one, gateway transistor tendency was pulled low to low-voltage with back end, the p channel metal oxide semiconductor transistor in the phase inverter then is inclined to back end is maintained at high voltage, and both can vie each other.If the data consideration of reading and adopt more weak gateway transistor, the gateway transistor will weaken writing fashionable competitive power, is unfavorable for that data write.On the other hand, in the time will high voltage logic 1 being write to a back end of a certain storage unit via a bit line, this back end can be by the gateway transistor turns to this bit line, makes the voltage of this back end can reach the high voltage of logical one.Suppose this back end originally by the n channel metal oxide semiconductor transistor conducting in the phase inverter to low-voltage and stored logic 0; In the time will logical one being write to this back end, the n channel metal oxide semiconductor transistor in the gateway transistor AND gate phase inverter of conducting is in this back end dividing potential drop.If the gateway transistor a little less than, the voltage of this back end will be comparatively near the low-voltage of logical zero, difficult quilt is drawn high the high voltage to logical one.Say that equivalently when logical one was write the back end of logical zero, gateway transistor tendency drew high back end to high voltage, the n channel metal oxide semiconductor transistor in the phase inverter then is inclined to back end is maintained at low-voltage, and both can vie each other.If the data consideration of reading and adopt more weak gateway transistor, the gateway transistor will weaken writing fashionable competitive power, is unfavorable for that data write.
In other words, to read the demand that writes with data be conflicting to data; For the advanced technologies RAS/storage unit of small size, low-work voltage, above-mentioned contradiction is more obvious.
Summary of the invention
To the problems referred to above, read and write in order to take into account data, the present invention proposes a kind of to classify the basis as, to be the independently-powered RAS of two phase inverters in each storage unit of same row according to bit line data (voltage).
The purpose of this invention is to provide a kind of RAS, it includes a plurality of power circuits that are arranged as the storage unit and a correspondence of row (column).Each storage unit is provided with one first power end, one second power end and an end, and the position end of a plurality of storage unit all is coupled to same bit line.Be provided with one first phase inverter, one second phase inverter and a gateway transistor in each storage unit.First phase inverter has a power end, an input end and an output terminal, couples first power end, one second back end and one first back end respectively.Second phase inverter also has a power end, an input end and an output terminal, couples second power end, first back end and second back end respectively.Gateway transistor one end couples the position end, and the other end couples one of them of second back end and first back end.Power circuit is provided with a feeder ear, couples first power end of a plurality of storage unit of same row; Whether power circuit includes a power switch, couples bit line and feeder ear, will be with feeder ear conducting to a WV with the voltage decision according to bit line.
In one embodiment of the invention, aforesaid power circuit includes an electric power maintainer in addition, couples feeder ear; When power switch during not with feeder ear conducting to WV, the electric power maintainer provides an electric current in feeder ear.
In one embodiment of the invention, aforesaid power switch includes a power transistor, has a grid and two links, couples bit line, WV and feeder ear respectively.
In one embodiment of the invention, aforesaid power switch includes a logical circuit in addition, is coupled between grid and the bit line; Logical circuit carries out logical operation with the voltage and a write control signal of bit line, and power transistor be according to the decision of the operation result of logical circuit whether with the feeder ear conducting to WV.
In one embodiment of the invention; Gateway transistor in aforesaid each storage unit is coupled between first back end and the position end; And each storage unit is provided with a "A" end of car in addition, and includes one second gateway transistor in addition, is coupled between second back end and the "A" end of car; The "A" end of car of a plurality of storage unit all is coupled to one second bit line; Power circuit is provided with one second feeder ear in addition; Couple second power end of a plurality of storage unit; And power circuit includes one second power switch in addition; Whether second power switch couples second bit line and second feeder ear, will be with the second feeder ear conducting to WV with the voltage decision according to second bit line.
In one embodiment of the invention, each storage unit in aforesaid a plurality of storage unit is provided with one the 3rd power end and one the 4th power end in addition; First phase inverter in each storage unit is provided with a second source end in addition, couples the 3rd power end; Second phase inverter in each storage unit is provided with a second source end in addition, couples the 4th power end; And RAS includes a second source circuit in addition, and the second source circuit is provided with a feeder ear, couples the 4th power end of a plurality of storage unit; Whether and the second source circuit includes one second power switch, and second power switch couples the feeder ear of bit line and second source circuit, will be with feeder ear conducting to one second WV of second source circuit with the voltage decision according to bit line; Wherein second WV and WV are different.
In one embodiment of the invention, aforesaid second source circuit includes one second electric power maintainer in addition, and the second electric power maintainer is coupled to the feeder ear of second source circuit; When second power switch during not with feeder ear conducting to the second WV of second source circuit, the second electric power maintainer provides an electric current in the feeder ear of second source circuit.
In one embodiment of the invention; Gateway transistor in aforesaid each storage unit is coupled between first back end and the position end; And each storage unit is provided with a "A" end of car, one the 3rd power end and one the 4th power end in addition; And include one second gateway transistor in addition, be coupled between second back end and the "A" end of car; And first phase inverter in each storage unit is provided with a second source end in addition, couples the 3rd power end; Second phase inverter in each storage unit is provided with a second source end in addition, couples the 4th power end; The "A" end of car of a plurality of storage unit all is coupled to one second bit line, and RAS includes a second source circuit in addition, is provided with a feeder ear, couples the 4th power end of a plurality of storage unit; Whether and the second source circuit includes one second power switch, couples the feeder ear of second bit line and second source circuit, will be with feeder ear conducting to one second WV of second source circuit with the voltage decision according to second bit line; Wherein second WV and WV are different.
In one embodiment of the invention; Gateway transistor in aforesaid each storage unit is coupled between first back end and the position end; And each storage unit is provided with a "A" end of car and one second gateway transistor in addition, and the second gateway transistor is coupled between first back end and the "A" end of car; The "A" end of car of a plurality of storage unit all is coupled to one second bit line, and the power switch in the power circuit according to the voltage decision of the voltage of bit line and second bit line whether with the WV conducting to feeder ear.
In one embodiment of the invention, include a power transistor in the aforesaid power switch, have a grid and two links, two links couple WV and feeder ear respectively; One logical circuit is coupled between grid, bit line and second bit line of power transistor; Logical circuit carries out logical operation with the voltage of bit line and the voltage of second bit line, and power transistor be according to the decision of the operation result of logical circuit whether with the feeder ear conducting to WV.
In the present invention, can read demand according to data earlier and adopt more weak gateway transistor.To writing demand; In the time will logical zero being write to the back end of a script stored logic 1 via a bit line; The tentation data node originally by the p channel metal oxide semiconductor transistor conducting in one first phase inverter to high voltage; Write fashionable; The present invention can be via to the power supply of phase inverter control and in first phase inverter, reduce the source electrode supply voltage (making its source electrode suspension joint) of its p channel metal oxide semiconductor transistor, but in second phase inverter, keep the source electrode supply voltage of its p channel metal oxide semiconductor transistor.The source electrode supply voltage that in first phase inverter, reduces the p channel metal oxide semiconductor transistor can reduce its source voltage and conducting degree, makes the gateway transistor more be prone to the back end of script stored logic 1 is pulled low to the low-voltage of logical zero.Simultaneously, concerning the p channel metal oxide semiconductor transistor of second phase inverter, because its source electrode supply voltage remains unchanged, its conducting degree is unaffected, makes it can be with the high voltage of voltage fast lifting to the logical one of corresponding data node.When realizing, the present invention can judge that the p channel metal oxide semiconductor transistor in that phase inverter of reply reduces the source electrode supply voltage according to the voltage (also promptly desiring to write data) of bit line.
Symmetrically; The discussion of continuity the preceding paragraph; The present invention also can increase its source electrode supply voltage (making its source electrode suspension joint) to the n channel metal oxide semiconductor transistor in first phase inverter; It is poor to reduce its grid and voltage between source electrodes equally, reduces its conducting degree, so that logical one is write to a back end of stored logic 0 originally via a bit line; Simultaneously, to the n channel metal oxide semiconductor transistor in second phase inverter, its source electrode supply voltage then remains unchanged, and its conducting degree is unaffected, makes it can apace the voltage of its corresponding data node be pulled low to the low-voltage of logical zero.
Above-mentioned explanation only is the general introduction of technical scheme of the present invention; Understand technological means of the present invention in order can more to know; And can implement according to the content of instructions, and for let above and other objects of the present invention, feature and advantage can be more obviously understandable, below special act embodiment; And conjunction with figs., specify as follows.
Description of drawings
Fig. 1 illustrates the RAS of one embodiment of the invention.
Fig. 2 illustrates the operation situation of RAS shown in Figure 1.
Fig. 3 illustrates the RAS of another embodiment of the present invention.
Fig. 4 illustrates the operation situation of RAS shown in Figure 3.
Fig. 5 illustrates the RAS of further embodiment of this invention.
Fig. 6 illustrates the operation situation of RAS shown in Figure 5.
Fig. 7 illustrates the RAS of yet another embodiment of the invention.
Fig. 8 illustrates the operation situation of RAS shown in Figure 7.
Fig. 9 illustrates the RAS of another embodiment of the present invention.
Figure 10 illustrates the operation situation of RAS shown in Figure 9.
Figure 11 illustrates the RAS of further embodiment of this invention.
Figure 12 illustrates the operation situation of RAS shown in Figure 11.
Figure 13 illustrates the RAS of yet another embodiment of the invention.
Figure 14 illustrates the operation situation of RAS shown in Figure 13.
Figure 15 illustrates the RAS of another embodiment of the present invention.
Figure 16 illustrates the operation situation of RAS shown in Figure 15.
Description of reference numerals in the above-mentioned accompanying drawing is following:
The 101-108 RAS
U (m, n)-U (m ', n '), Uf (m, n)-Uf (m ', n), Ue (m, n)-Ue (m ', n) storage unit
21a-25a, 21b-25b, 25c-25d, 26,26c, 27a-27c, 28a-28b power switch
31a-35a, 31b-35b, 35c-35d, 36,36c, 37a-37c, 38a-38b electric power retainer
PC 1 (n)-PC8 (n), PC 1 (n '), PC5N (n)-PC7N (n) power circuit
BL (n), BLB (n), BL (n '), BLB (n '), BL 1 (n)-BL2 (n), BLB 1 (n)-BLB2 (n) bit line
WL (m), WL (m '), WL1 (m)-WL2 (m), WL1 (m ')-WL2 (m ') character line
WEB, WE write control signal
VDD, VSS WV
VVDD1, VVDD2, VVSS1, VVSS2 voltage
M1-M8, N1-N2, P1-P2, T1-T4, NM1-NM4 transistor
The NR1-NR2 rejection gate
The ND1-ND2 Sheffer stroke gate
Iv1-iv2, IVa-IVd phase inverter
I3-I4, I7-I8 electric current
Nb1-nb4, ns1-ns4, np1-np2, Q, QB, nn1-nn2 node
Embodiment
Please refer to Fig. 1, that it is illustrated is an embodiment of RAS of the present invention.In the present embodiment, RAS 101 can be a static RAM, has a plurality of storage unit, in Fig. 1 with storage unit U (m, n), U (m, n '), U (m ', n) with U (m ', n ') as representative; Each storage unit can be six transistorized static storage cells.These storage unit are arranged as array, and for instance, (m n) is arranged in same delegation with U (m, n '), corresponding to same character line W (m) to storage unit U; Storage unit U (m ', n) then be arranged in another row, corresponding to character line W (m ') with U (m ', n ').Moreover, storage unit U (m, n) with U (m ', n) be arranged in same row, corresponding to pair of bit lines BL (n) and BLB (n); Storage unit U (m, n ') and U (m ', n ') then belong to same row, corresponding another pairs of bit line BL (n ') and BLB (n ').
In RAS 101, and each storage unit U (m, n) framework to U (m ', n ') is identical; With storage unit U (m; N) be example, it has transistor N1 and N2 (can be the n channel metal oxide semiconductor transistor), the transistor P1 of two mutual couplings and the transistor T 1 and the T2 (can be the n channel metal oxide semiconductor transistor) of P2 (can be the p channel metal oxide semiconductor transistor) and two mutual couplings of two mutual couplings.Transistor P1 and N1 form a phase inverter iv1, and input end couples the source electrode that node QB, output terminal couple node Q, transistor P1 and couples node ns1, and the source electrode of transistor N1 couples WV VSS (like a ground terminal voltage).Symmetrically, transistor P2 and N2 form a phase inverter iv2, and input end couples the source electrode that node Q, output terminal couple node QB, transistor P2 and couples node ns2, and the source electrode of transistor N2 couples WV VSS.Transistor T 1 and T2 are as the gateway transistor, and both grids are controlled by character line WL (m); Transistor T 1 is coupled between node nb1 and the Q, and 2 of transistor Ts are coupled between node nb2 and the QB.Node ns1 and ns2 can be considered storage unit U, and (node Q and QB are two back end for m, two power ends n), and node nb1 and nb2 then can be considered two ends.
In order to realize technology of the present invention, also be provided with a plurality of power circuits in the RAS 101, each power circuit is corresponding to the storage unit of row; In Fig. 1, power circuit PC1 (n) promptly corresponding to storage unit U (m, n) with U (m ', the row under n), power circuit PC1 (n ') are another row under corresponding stored unit U (m, n ') and the U (m ', n ') then.Identical and the coupling of circuit framework of each power circuit PC1 (n) and PC1 (n ') below is that example is explained with power circuit PC1 (n) promptly.
In the embodiment in figure 1, be provided with two power switch 21a and 21b among the power circuit PC1 of the present invention (n), and two electric power maintainer 31a and 31b.Wherein, node np1 and np2 can be considered the feeder ear of power circuit PC1 (n), node np1 be coupled to each storage unit U (m, n) with U (m ', node ns1 n) is the supply of the phase inverter iv1 in storage unit voltage VVDD1.Symmetrically, node np2 be coupled to each storage unit U (m, n) with U (m ', node ns2 n) is the supply of the phase inverter iv2 in storage unit voltage VVDD2.Be respectively equipped with the transistor M1 of mutual coupling and rejection gate NR1 and the NR2 that M2 (can be the p channel metal oxide semiconductor transistor) and two matees each other among power switch 21a and the 21b.The source electrode of transistor M1 couples WV VDD, and drain electrode couples node np1, and rejection gate NR1 then is coupled between bit line BL (n) and the transistor M1; Rejection gate NR1 does anti-or logical operation to a voltage and the write control signal WEB of bit line BL (n); Its output terminal couples the grid of transistor M1, makes transistor M1 be able to whether will put the np1 conducting to WV VDD (it can be a voltage that is higher than WV VSS) according to anti-or logic operation result decision.Symmetrically, rejection gate NR2 then does anti-or logical operation to voltage and the write control signal WEB of bit line BLB (n), makes transistor M2 whether will put the np2 conducting to WV VDD according to anti-or logic operation result decision. Electric power maintainer 31a and 31b are provided with the transistor M3 and the M4 (can be p type metal oxide semiconductor transistor) of two mutual couplings, and its grid couples WV VSS, and source electrode couples WV VDD, and drain electrode couples node np1 and np2 respectively.In preferred embodiment of the present invention, it is stronger than transistor M3 and M4 that transistor M1 and M2 can design; In other words, compare with transistor M1 (M2), the raceway groove of transistor M3 (M4) is long or narrower, and driving force is relatively poor, and the conducting resistance between source electrode and drain electrode is bigger.
The embodiment of continuity Fig. 1 please refer to Fig. 2, and it is to be that example is illustrated the operation situation of RAS 101 of the present invention with the coherent signal of power circuit PC1 (n) and state.RAS 101 can alternately operate on read mode (being denoted as " read " among Fig. 2), standby mode (" standby ") and write pattern (" write ").When RAS 101 operated on standby mode, character line WL (m) (with WL (m ')) was a logical zero, any storage unit of not access; Bit line BL (n) and BLB (n) can be maintained at the high voltage (for example being WV VDD) of logical one, and write control signal WEB then is controlled as logical one.Via the logical operation of rejection gate NR1 and NR2, transistor M1 and M2 are switched on (being denoted as " on " among Fig. 2), and node np1 and np2 are distinguished conducting to WV VDD, make voltage VVDD1 and VVDD2 all equal WV VDD.Under this situation, each storage unit U (m, n) with U (m ', phase inverter iv1 in n) and iv2 all normal operation with latch data.
RAS 101 also can operate on the pattern of writing and with one data write to storage unit U (m, n).To write logical one is that example (being denoted as " write " 1 " " among Fig. 2) is explained; Will (m writes logical one in n), and will make node Q exactly is the high voltage of logical one, and to make the node QB of anti-phase be the logical zero low-voltage at storage unit U.So writing Qi Shishi, bit line BL (n) is a logical one, and bit line BLB (n) is a logical zero, character line WL (m) be logical one with turn-on transistor T1 and T2, write control signal WEB then is a logical zero.What suppose that node Q stores originally is the logical zero of low-voltage, and node QB can store the logical one of anti-phase.When writing Qi Shishi; The transistor P2 of conducting can be inclined to node QB is maintained logical one; The transistor N1 of conducting can be inclined to node Q is maintained logical zero; And these two transistor N1 and P2 can strengthen the tendency that it keeps voltage each other via the breech lock framework: when transistor P2 is maintained at high voltage with node OB, also guarantee the conducting of transistor N1; Symmetrically, when transistor N1 is maintained at low-voltage with node Q, also guarantee the conducting of transistor P2.For realizing that the purpose that writes makes the voltage upset of node Q and QB, transistor T 1 should be drawn high the voltage of node Q, 2 voltages that should drag down node QB of transistor T.But, compare with N2 with transistor N1 and since transistor T 1 and T2 a little less than, order about node Q and QB change voltage effectively than difficulty.
But; Under the running of power circuit PC1 of the present invention (n); When writing Qi Shishi; The logical zero of bit line BLB (n) and the logical zero of write control signal WEB can the transistor M2 among the power switch 21b be closed via rejection gate NR2 (among Fig. 2 with " off " representative), only keep the voltage VVDD2 of node np2 with transistor M4 regulation and control.With respect to transistor M2, because transistor M4 is designed to a more weak transistor, so even transistor M4 conducting, the voltage VVDD2 of node np2 also no longer is maintained at WV VDD and can reduces.Thus, transistor P2 also diminishes at the source voltage of node ns2, and the conducting degree of transistor P2 is died down, thereby makes transistor T 2 be prone to node QB is pulled low to the low-voltage of logical zero.Moreover because the voltage of node QB reduces, the also difficult voltage with node Q of transistor N1 is maintained at low-voltage, and bit line BL (n) can be more quickly promoted the voltage of node Q.
On the other hand; When writing Qi Shishi; The logical one of bit line BL (n) and the logical zero of write control signal WEB can make the transistor M1 among the power switch 21a keep conducting via rejection gate NR1, so voltage VVDD1 maintains the transistor P1 of WV VDD normal power supply to the phase inverter iv1.That is to say that when the voltage of node QB begins to descend, transistor P1 can normally begin conducting, so that the voltage of node Q is drawn high to WV VDD; Via the breech lock framework, the voltage that quickens node Q rises and also can make transistor N2 conducting quickly, further helps the voltage of node QB is pulled low to WV VSS.
In other words; Under the running of power circuit PC1 of the present invention (n), if will write logical zero at node QB, the pairing power switch 21b of transistor P2 can close not conducting; Make node np2 be similar to suspension joint, reduce the source electrode supply voltage (voltage VVDD2 just) of transistor P2; At anti-phase node Q, (voltage VVDD1) is then unaffected for the source electrode supply voltage of transistor P1, still is equivalent to WV VDD.More than can both effectively accelerate speed and the efficient that data write, and improve static noise nargin (Static Noise Margin).Symmetrically; When will be at storage unit U (m; N) write logical zero in; Just to write logical one and when node Q write logical zero, the pairing power switch 21a of transistor P1 can close at node QB, node np1 can be similar to suspension joint and the source electrode supply voltage VVDD1 that makes transistor P1 less than WV VDD; The source electrode supply voltage VVDD2 of transistor P2 is then unaffected.That is to say that power switch 21a of the present invention and 21b are that both independently operate, and in each storage unit of same row, control the source electrode supply voltage of phase inverter iv1 and phase inverter iv2 respectively; According to writing data (being respectively logical zero/logical one or logical one/logical zero) on bit line BL (n)/BLB (n); Two phase inverter iv1 and iv2 have only the source electrode supply voltage of one of them to reduce; Another source electrode supply voltage then remains unchanged, with the ability that keeps its driving voltage and the feedback mechanism of latch circuit.
In a kind of prior art, write fashionablely when carrying out data, can unify two phase inverters in the storage unit are reduced supply voltage in the lump.For example, when will when node QB writes logical zero, the source electrode supply voltage of transistor P1 and P2 being reduced.Though this conducting degree that can reduce transistor P2 is to reduce transistor P2 keeps voltage at node QB ability; But also can injure the ducting capacity of transistor P1; Transistor P1 can not be normally reduced with the voltage of node OB increases the conducting degree, influences transistor P1 and draws high, and meeting of the present invention is dynamically adjusted according to the demand that data write; Only in two phase inverters, reduce the power supply of one of them, to promote the write performance of RAS of the present invention effectively.In addition, because the supply voltage that changes a phase inverter is only switched in the present invention, so the present invention also can be lower in the power consumption of switching supply voltage, the speed of accomplishing switching also can be than comparatively fast.
In RAS 101 of the present invention, as power switch 21a (21b) when closing, the voltage VVDD1 (VVDD2) of node np1 (np2) can be relevant with each drain current of storage of same row.For example, (m, when node QB n) write logical zero, the transistor M2 among the power switch 21b closed not conducting, made node np2 present the state of approximate suspension joint at storage unit U when will be via bit line BLB (n).Since node np2 can with electric power coiling be coupled to same row each storage unit U (m, and even n) U (m ', n), the equivalent capacity of this electric power coiling can be kept the voltage of node np2 with electric charge; Each storage unit U (m, and even n) U (m ', each the transistor P2 in n) then thus the electric power coiling draw leakage current (no matter the transistor P2 in each storage unit whether conducting), the voltage VVDD2 of node np2 is reduced because of discharge.Properly design the parameter of transistor M4; Can make transistor M4 conducting one appropriate current I4 compensate each drain current of storage of same row; The voltage VVDD2 of node np2 can stably be maintained at be lower than WV VDD but can low excessively degree, to safeguard stored data in each storage unit of same row.Symmetrically, when the transistor M1 stop conducting among the power switch 21a, transistor M3 also can provide electric current I 3 to compensate each drain current of storage of same row.
Please refer to Fig. 3 and Fig. 4; Fig. 3 signal be another embodiment of RAS of the present invention, Fig. 4 signal then be the situation that the RAS of present embodiment operates on various patterns.Be similar to RAS 101 (Fig. 1), the RAS 102 of present embodiment also is that ((m n) is provided with a corresponding power circuit PC2 (n) with U (m ', n) representative) with U for each storage unit of n row.Node np1 and np2 are two feeder ears of power circuit PC2 (n), are coupled to node ns1 and the ns2 in each storage unit of same row with the electric power coiling respectively, so that voltage VVDD1 and VVDD2 to be provided the source electrode supply voltage as transistor P1 and P2.Also be provided with two power switch 22a and 22b among the power circuit PC2 (n), and two electric power maintainer 32a and 32b.Electric power maintainer 32a and 32b can realize that with transistor M3 and M4 (can be the p channel metal oxide semiconductor transistor of two couplings) grid of transistor M3 and source electrode couple WV VSS and VDD respectively respectively, and drain electrode then couples node np1; Symmetrically, the drain electrode of transistor M4 then couples node np2.Power switch 32a is provided with a transistor M1 and a phase inverter Iva; Phase inverter IVa is with data (voltage) anti-phase of bit line BL (n) grid with oxide-semiconductor control transistors M1.Transistor M1 is then as a power transistor (for example being a p channel metal oxide semiconductor transistor), and its source electrode couples WV VDD and node np1 respectively with drain electrode.Symmetrically; Power switch 32b is provided with a transistor M2 (can be a transistor with transistor M1 coupling) and a phase inverter IVb, make transistor M2 can according to the reverse voltage decision of bit line BLB (n) whether between its source drain with WV VDD conducting to node np2.
The principle of work of power circuit PC2 (n) is similar to the power circuit PC1 (n) among Fig. 1; Can be that phase inverter iv1 and the iv2 of same array storage unit supplies two separate voltage VVDD1 and VVDD2 respectively according to the data voltage of bit line BL (n) and BLB (n), with source electrode supply voltage as transistor P1 and P2.But; RAS 102 has been cancelled the write control signal WEB among Fig. 1; So the on-off circuit 22a of power circuit PC2 (n) can only regulate and control voltage VVDD1 according to bit line BL (n), on-off circuit 22b can only regulate and control voltage VVDD2 according to bit line BLB (n).As shown in Figure 4, when writing fashionablely carrying out data, the operation situation of power circuit PC2 (n) can be analogized by the operation situation of power circuit PC1 (n), so power circuit PC2 (n) also follows the advantage of power circuit PC1 (n).For example, when will data cell U (m, when writing the position of logical one in n), bit line BLB (n) can be pulled low to the low-voltage of logical zero, via the running of phase inverter IVb, and even the conducting degree of transistor M2 reduces closes fully, makes node np2 be similar to suspension joint; Same array storage unit U (m; N) and even other not by the storage unit U of access (m '; N) meeting is drawn leakage current via the electric power coiling of node np2 and voltage VVDD2 is dragged down; Electric power maintainer M4 then provides electric current I 4 suitably to compensate the leakage current of same array storage unit, and voltage VVDD2 is maintained at an appropriate voltage that is lower than WV VDD.This voltage VVDD2 can storage unit U (m reduces the conducting degree of transistor N1 and P2 in n), improvement to storage unit U (m, data n) write, but can not influence other storage unit U (m ', the data in n).The transistor M1 of conducting among the power switch 22a then is maintained at WV VDD with voltage VVDD1, and (m, the transistor P1 in n) and N2 completion inerrably fast write to assist storage unit U.
On the other hand, when RAS 102 will storage unit U (m, n) in during reading of data, if storage unit U (m, the position that stores in n) be logical one (in Fig. 4, be denoted as " read " 1 " "), node Q and QB can distinguish stored logic 1 and logical zero; Reading when carrying out, the voltage of bit line BLB (n) can be dragged down, and the transistor M2 among the power switch 22b can reduce the conducting degree accordingly, loosens the control to voltage VVDD2; At this moment, same array storage unit U (m, and even n) not by the storage unit U of access (m ', n) all can draw leakage current by the coiling of the electric power of node np2, voltage VVDD2 is reduced.But, compare with the running that writes logical one, when reading logical one, the degree that the voltage of bit line BLB (n) is dragged down is less, and speed is slower, so less relatively to the influence of the storage unit of same row.In other words, via suitable circuit design, as long as the transistor M4 of electric power maintainer 32b can keep suitable voltage VVDD2 when writing logical one, the running that just can guarantee to read logical one is errorless, can not influence the data that store in each storage unit of same row.Symmetrically, if transistor M3 can keep suitable voltage VVDD1 when writing logical zero, the running of reading logical zero also can be correct.In addition,, with IVb it is exported the standard that is changed into logical one by logical zero, also can guarantee to read the correctness of running if the standard that employed sensing amplifier (not icon) detects logical zero when reading is higher than phase inverter IVa via suitable circuit design.For example; When reading logical one; When the voltage of bit line BLB (n) dropped to (VDD-dV), wherein dV was a difference voltage, and this moment, sensing amplifier can be logical zero with the data identification on the bit line BLB (n); But phase inverter IVb will bit line BLB (n) regards as logical one and still to transistor M2 output logic 0, transistor M2 just can not reduce the conducting degree.
Please refer to Fig. 5 and Fig. 6; That Fig. 5 illustrates is another embodiment of RAS of the present invention, the operation situation of RAS under various patterns then shown in Figure 5 of Fig. 6 signal.In the present embodiment, ((m n) provides voltage VVDD1 and VVDD2 respectively with U (m ', n)) like storage unit U to be provided with each storage unit that power circuit PC3 (n) thinks n row in the RAS 103.Be similar to power switch 21a and the 21b of Fig. 1 power circuit PC1 (n), also be provided with power switch 23a and 23b among the power circuit PC3 (n), but omitted the electric power maintainer.Under the control of write control signal WEB, power switch 23a and 23b can supply two independent voltage VVDD1 and VVDD2 writing phase inverter iv1 and the iv2 that fashionable voltage according to bit line BL (n) and BLB (n) is respectively same each storage unit of row.For example, when will (m be when n) writing data 1 at data cell U; Because write control signal WEB and bit line BLB (n) are logical zero, the not conducting of transistor M2 among the power switch 23b makes node np2 be similar to suspension joint; Voltage VVDD2 also will reduce, and writes running with improvement.Under suitable circuit design; As long as node np2 can be when not conducting of transistor M2 with the electric charge of equivalent capacity/stray capacitance each drain current of storage of same row of suitably contending with; Just can guarantee to write the normally errorless of running, also can not influence in the same row not by the storage unit of access.
Please refer to Fig. 7 and Fig. 8; That Fig. 7 illustrates is the another embodiment of RAS of the present invention, and what Fig. 8 illustrated then is the situation that RAS operates on various patterns among Fig. 7.In the present embodiment, RAS 104 also is the power circuit PC4 (n) that n storage unit that is listed as is provided with a correspondence.Be provided with power switch 24a, 24b and electric power maintainer 34a and 34b among the power circuit PC4 (n).Power switch 24a and 24b realize with transistor NM1 and NM2 respectively; Transistor NM1 and NM2 can be two n channel metal oxide semiconductor transistors of coupling each other.The drain electrode of transistor NM1, grid and source electrode couple WV VDD, bit line BL (n) and node np1 respectively; Symmetrically, the drain electrode of transistor NM2, grid and source electrode couple WV VDD, bit line BLB (n) and node np2 respectively.Electric power maintainer 34a and 34b are then realized by transistor NM3 and NM4 respectively; These two transistors can be the n channel metal oxide semiconductor transistors that matees each other, and two transistor is diode separately and connects, and drain electrode is coupled to WV VDD jointly with grid, and source electrode then couples node np1 and np2 respectively.
According to the data voltage of bit line BL (n), whether power switch 24a can determine WV VDD conducting to node np1; For example; As shown in Figure 8, when RAS 104 will (m writes logical zero in n) and when making bit line BL (n) for logical zero at storage unit U; Not conducting of transistor NM1 among the power switch 24a; Make node np1 be similar to suspension joint, and node np1 will reduce for the source electrode supply voltage VVDD1 that each storage unit provides, to promote the usefulness that data write.No matter read or write; Transistor NM3 among the electric power maintainer 34a can afford redress electric current I 3 suitably to keep voltage VVDD1 when transistor not conducting of NM1 or conducting degree are low; Make voltage VVDD1 be lower than WV VDD; But be unlikely to low, guaranteeing in the same row, stored data can be not influenced in each storage unit except the storage unit that to be ready being written into data.Symmetrically, power switch 24b and electric power maintainer 34b can regulate and control the voltage VVDD2 of node np2 according to the data of bit line BLB (n).
Please refer to Fig. 9 and Figure 10; That Fig. 9 illustrates is the another embodiment of RAS of the present invention, and what Figure 10 illustrated then is the situation that RAS shown in Figure 9 operates on various patterns.In aforementioned each embodiment; The power circuit of RAS 101 to 104 of the present invention is for the transistor P1 in each storage unit of same row and P2 source electrode supply voltage VVDD1 and VVDD2 to be provided, and dynamically adjusts voltage VVDD1 and VVDD2 respectively according to the data voltage of character line.In Fig. 9 and embodiment shown in Figure 10; RAS 105 is that n each storage unit that is listed as is (like storage unit U (m with power circuit PC5 (n) not only; N) with U (m '; N)) voltage VVDD1 and VVDD2 are provided, also in addition come voltage VVSS1 and VVSS2 to be provided respectively for the transistor N1 in each storage unit of same row and N2 with the power circuit PC5N (n) that sets up.
In RAS 105, the circuit framework of power circuit PC5 (n) and the power circuit PC1 (n) that disposes similar Fig. 1.At storage unit U (m; N) (with U (m '; N)) in; The transistor P1 of phase inverter iv1 and iv2 and P2 are coupled node np1 and the np2 of power circuit PC5 (n) respectively by node ns1 and ns2, and the source electrode supply voltage that voltage VVDD1 that power circuit PC5 (n) provides at node np1 and np2 and VVDD2 just become transistor P1 and P2.Power circuit PC5 (n) is provided with power switch 25a, 25b and electric power maintainer 35a, 35b.Power switch 25a according to the decision of the voltage of write control signal WEB and bit line BL (n) whether with node np1 conducting to WV VDD; Symmetrically, power switch 25b according to the decision of the voltage of write control signal WEB and bit line BLB (n) whether with node np2 conducting to WV VDD.When power switch 25a made node np1 be similar to suspension joint, electric power maintainer 25a can assist to make voltage VVDD1 to be lower than voltage VDD but be unlikely to low; In like manner, electric power maintainer 25b can assist to keep suitable voltage VVDD2 when node np2 is similar to suspension joint.
On the other hand, two node nn1 and the nn2 of power circuit PC5N (n) can be considered two feeder ears, supply voltage VVSS1 and VVSS2 respectively; At storage unit U (m; N) (and even U (m '; N)) among two the phase inverter iv1 and iv2, the source electrode of transistor N1 and N2 promptly couples node nn1 and nn2 by node ns3 and ns4 respectively, with voltage VVSS1 and the VVSS2 source electrode supply voltage as transistor N1 and N2.Be provided with power switch 25c, 25d and electric power maintainer 35c, 35d among the power circuit PC5N (n).Be provided with a transistor M5 and a Sheffer stroke gate ND1 among the power switch 25c; Symmetrically, transistor M6 and Sheffer stroke gate ND2 then are set among the power switch 25d.Transistor M5 and M6 can be the n channel metal oxide semiconductor transistors of two couplings, and source electrode is coupled to WV VSS.Sheffer stroke gate ND1 does anti-and logical operation with the data voltage of bit line BL (n) and another write control signal WE, and the grid of oxide-semiconductor control transistors M5 in view of the above.According to the output of Sheffer stroke gate ND1, whether transistor M5 can determine between its drain electrode and source electrode node nn1 conducting to WV VSS.Symmetrically, Sheffer stroke gate ND2 does anti-and computing to bit line BLB (n) and write control signal WE, makes the transistor M6 conducting between Control Node nn2 and WV VSS according to this.Electric power maintainer 35c and 35d realize with transistor M7 and M8 respectively; These two transistors can be the n channel metal oxide semiconductor transistors that matees each other; Grid and source electrode couple WV VDD and VSS respectively, and drain electrode then couples node nn1 and nn2 respectively.When transistor M5 closes not conducting; Node nn1 is similar to suspension joint, and the leakage current that each storage unit of same row is injected node nn1 can make voltage VVSS1 be higher than WV VSS, and transistor M7 then can draw appropriate current I7; So that voltage VVSS1 is higher than WV VSS, but can be not too high.Symmetrically, when the not conducting of transistor M6 among the power switch 25d, the transistor M8 among the electric power maintainer 35d can conducting electric current I 8 keep suitable voltage VVSS2 with assistance.
Power circuit PC5 (n) can explain as follows with the situation of PC5N (n) Collaboration.Write control signal WEB and WE be inversion signal each other, reads or during standby mode, write control signal WE can anergy be a logical zero when RAS 105 operates on, and write control signal WEB then is a logical one.In power circuit PC5 (n), the write control signal WEB of logical one can make transistor M1 and M2 conducting, makes voltage VVDD1 and VVDD2 all be maintained at WV VDD, and normal power supply is given transistor P1 and the P2 in each storage unit of same row.In like manner; Logical zero write control signal WE can make transistor M5 and the M6 conducting among the power circuit PC5N (n); Make voltage VVSS1 and VVSS2 all be maintained at WV VSS, normally the source electrode supply voltage is provided for transistor N1 and N2 in each storage unit of same row.
When RAS 105 will be write fashionable; Write control signal WE activation is a logical one; Write control signal WEB then is the logical zero of anti-phase, impels power circuit PC5 (n) and PC5N (n) to come to regulate and control respectively voltage VVDD1, VVDD2, VVSS1 and VVSS2 according to bit line BL (n) and BLB (n).For example, when will (m be when writing logical one in n) at storage unit U; Bit line BLB (n) is a logical zero; Transistor M2 stop conducting among the power circuit PC5 (n) makes node np2 be similar to suspension joint, reduces voltage VVDD2; The logical one of bit line BL (n) then makes transistor M1 keep conducting, and voltage VVDD1 is maintained normal WV VDD.On the other hand, the bit line BL (n) of logical one and logical one write control signal WE close the transistor M5 among the power switch 25c via Sheffer stroke gate ND1, and node nn1 be similar to suspension joint, make upwards drift and above WV VSS of voltage VVSS1; Transistor M7 then makes voltage VVSS1 be unlikely to too high, lets in the same row not by other storage unit of access (like storage unit U (m ', n)) correct storage data still.Logical zero bit line BLB (n) then makes the transistor M6 normally among the power switch 25d, and voltage VVSS2 is maintained normal WV VSS.
Suppose storage unit U (m, n) script stored logic 0 (node Q is a logical zero, and node QB is a logical one); When RAS 105 will storage unit U (m, when writing logical one in n), just as leading portion said; Voltage VVDD2 can reduce, and in storage unit U (m, n) the middle conducting degree that reduces transistor P2; The voltage of node QB is reduced via 2 discharges of gateway transistor T, and it be logical zero that node QB can be overturn by logical one quickly.In addition, voltage VVSS1 then raises, and reduces the conducting degree of transistor N1, and the voltage of node Q is raise, and it is logical one that node Q can more promptly be overturn by logical zero via transistor P1 charging.At the same time; Voltage VVDD1 can normally be maintained at WV VDD; Assist transistor P1 normally and node Q is increased to the high voltage of logical one; In like manner, voltage VVSS2 can normally be maintained at WV VSS, makes the transistor N1 can normally and node QB is pulled low to the low-voltage of logical zero.That is to say that via power circuit PC5 of the present invention (n) and the respectively regulation and control of PC5N (n) to voltage VVDD1, VVDD2, VVSS1 and VVSS2, RAS 105 of the present invention can effectively promote the usefulness that data write.
In RAS 105, power circuit PC5 (n) and PC5N (n) can be regarded as head (header) power circuit and pin (footer) power circuit respectively.Power circuit PC5N (n) among Fig. 9 is merely a kind of embodiment of the present invention; The embodiment of other kind can be analogized with PC4 (n) by power circuit PC2 (n), the PC3 (n) of Fig. 3, Fig. 5 and Fig. 7.In addition, the RAS among Fig. 3, Fig. 5 and Fig. 7 also can be according to the framework of RAS 105, comes to regulate and control the source electrode supply voltage respectively for the transistor N1 in each storage unit of same row and N2 with the circuit that is similar to power circuit PC5N (n).
Please refer to Figure 11 and Figure 12; That Figure 11 illustrates is a kind of embodiment that RAS of the present invention is applied to five transistor static storage cells, and what Figure 12 illustrated is the situation that RAS shown in Figure 11 operates.In the present embodiment, RAS 106 can have a plurality of storage unit that are respectively in a plurality of row, among Figure 11 with n row in storage unit Uf (m, n) with Uf (m ', n) as the representative.Be similar to aforesaid six transistor static storage cell U (m, n), storage unit Uf (m forms two phase inverter iv1 and iv2 respectively with transistor P1 and N1, transistor P2 and N2 in n), and with node Q and QB as back end.But, in RAS 106, each storage unit Uf of same row (m, n) with Uf (m ', n) only via single bit lines BL (n) access data; So storage unit Uf (m, n) (also have only a gateway transistor T 1 with Uf (m ', n)), its grid couples character line WL (m), and source drain is coupled between node nb1 and the Q, with according to the voltage decision of character line WL (m) whether with node Q conducting to bit line BL (n).
Concerning five transistorized storage unit,,, be comparatively difficult so in writing running, need to write logical one (making node Q is logical one, and node QB is a logical zero) via bit line BL (n) owing to do not have the anti-phase bit line that Control of Voltage is provided on the node QB.In order to assist writing of logical one, RAS 106 of the present invention can be provided with power circuit PC6 (n) and PC6N (n) for each storage unit of n row.Be provided with a power switch 26 and an electric power maintainer 36 among the power circuit PC6 (n), so that a voltage VVDD2 to be provided at node np2; Node np2 can be coupled to each storage unit Uf (m, n) with Uf (m ', node ns2 n), the transistor P2 that voltage VVDD2 can be in each storage unit of same row provides the source electrode supply voltage.In power switch 26, transistor M2 (for example being a p channel metal oxide semiconductor transistor) is as a power transistor, and source electrode couples WV VDD and node np2 respectively with drain electrode.Phase inverter IVc AND NR2 then forms a logical circuit, and whether transistor M2 is able to according to the decision of the data voltage of write control signal WEB and bit line BL (n) node np2 conducting to WV VDD.Electric power maintainer 36 can use a transistor M4 (like a p channel metal oxide semiconductor transistor) to realize that its source electrode, grid and drain electrode couple WV VDD, WV VSS and node np2 respectively.Compared to transistor M2, transistor M4 can be a more weak transistor; When not conducting of transistor M2; Node np2 can be similar to suspension joint makes voltage VVDD2 depart from WV VDD; And transistor M4 will provide the electric current I 4 compensation leakage current that same array storage unit is drawn by node np2; Make voltage VVDD2 be lower than WV VDD, but can be not low excessively, to safeguard the data in each storage unit of same row.
Based on similar techniques spirit, be provided with power switch 26c and electric power maintainer 36c among the power circuit PC6N (n), with the voltage VVSS1 of regulation and control node nn1.Node nn1 can be coupled to the node ns3 in each storage unit of same row, and the transistor N1 that makes voltage VVSS1 can be same each storage unit of row provides the source electrode supply voltage.Be provided with a transistor M5 (like a n channel metal oxide semiconductor transistor) among the power switch 26c, and form a logical circuit with Sheffer stroke gate ND1 and phase inverter IVd.The drain electrode of transistor M5 and source electrode couple node nn1 and WV VSS respectively; Sheffer stroke gate ND1 does anti-and logical operation with the inversion signal of write control signal WEB and the data voltage of bit line BL (n), and transistor M5 is promptly according to the nn1 of Control Node as a result of anti-and logical operation and the conducting between WV VSS.Electric power maintainer 36c can realize that its drain electrode, grid and source electrode couple node nn1, WV VDD and VSS respectively by a transistor M7 (like a n channel metal oxide semiconductor transistor).Compared to transistor M5, transistor M7 can be a more weak transistor.When transistor M5 stop conducting; Node nn1 can be similar to suspension joint; Make voltage VVSS1 depart from WV VSS, but then conducting electric current I of transistor M7 7 make voltage VVSS1 be higher than WV VSS to draw the leakage current that each storage unit of same row is charged to node nn1; But can be not too high, do not influence the data in the same array storage unit.
But the running brief introduction of RAS 106 of the present invention is following.When reading or during standby mode, write control signal WEB is that logical one does not write with representative.Logical one write control signal WEB can make transistor M2 and M5 conducting, no matter bit line BL (n) is logical zero or 1.Therefore, power circuit PC6 (n) and PC6N (n) are maintained at WV VDD and VSS respectively with voltage VVDD2 and VVSS1, make each storage unit of same row can obtain normal power supply.
Fashionable when writing, write control signal WEB can change into logical zero, and power circuit PC6 (n) will regulate and control voltage VVDD2 and VVSS1 respectively according to the voltage of bit line BL (n) with PC6N (n).When bit line BL (n) for logical zero will storage unit Uf (m, when writing logical zero in n), transistor M2 and M5 still can normallies, voltage VVDD2 and VVSS1 can normally be maintained at WV VDD and VSS.Relatively, when bit line BL (n) be logical one with storage unit Uf (m, when writing logical one in n), transistor M2 and M5 can stop conductings; Therefore, node np2 and nn1 are similar to suspension joint, and voltage VVDD2 reduction, voltage VVSS1 are raise.Storage unit Uf (m, n) in, can the weaken conducting degree of transistor P2 of the voltage VVDD2 of reduction, and reduce the voltage of node QB makes node QB more easily via transistor N2 discharge and transfer logical zero to; The voltage VVSS1 that the raises conducting degree of transistor N1 that then weakens, and improve the voltage of node Q makes node Q more easily via transistor P1 charging and transfer logical one writing with completion logic 1 to.
The embodiment of continuity Figure 11 please refer to Figure 13 and Figure 14.That Figure 13 illustrates is the another embodiment of RAS of the present invention, and Figure 14 then illustrates the operation situation of the RAS among Figure 13.Be similar to the RAS 106 among Figure 11, in the present embodiment, RAS 107 also adopts five transistorized static storage cells, and is power circuit PC7 (n) and PC7N (n) that the n row are provided with a correspondence.But, the power circuit PC6 (n) of RAS 106 is main in order to improve writing of logical one, so one group of power switch and electric power maintainer only are set among the power circuit PC6 (n) with PC6N (n).For writing all of logical zero and logical one is improved, the power circuit PC7 (n) of RAS 107 is provided with two groups of power switches and electric power maintainer.Shown in figure 13, be provided with power switch 27a, 27b and electric power maintainer 37a, 37b among the power circuit PC7 (n).The basic framework of power switch 27b and electric power maintainer 37b is identical with power switch 26, the electric power maintainer 36 of function and Figure 11.Power switch 27a, electric power maintainer 37a are then at node np1 regulation and control voltage VVDD1; This voltage VVDD1 can provide the source electrode supply voltage for transistor P1 at the node ns1 of same array storage unit.
In power switch 27a, be provided with a transistor M1 and a rejection gate NR1, transistor M1 and transistor M2 coupling; Rejection gate NR1 then does anti-or logical operation to the data on write control signal WEB and the bit line BL (n), make transistor M1 can be according to result's decision of anti-or logical operation whether with node np1 conducting to WV VDD.The transistor M4 of transistor M3 among the electric power maintainer 37a and electric power maintainer 37b matees each other; When not conducting of transistor M1, transistor M3 provides electric current I 3 to keep suitable voltage VVDD1.
The situation that RAS 107 writes running can be described below.When will (m, when writing logical one in n), logical zero write control signal WEB and logical one bit line BL (n) make transistor M1 conducting, transistor M2 and then not conducting of M5 at storage unit Uf.Therefore, voltage VVDD2 reduces, voltage VVSS1 raises, and voltage VVDD1 then normally is maintained WV VDD.Therefore, storage unit Uf (m, n) in, the conducting degree of transistor P2, N1 weakens, the ducting capacity of transistor P1 is then unaffected, can be normally with node Q conducting to logical one.
Relatively, when (m is when writing logical zero in n) at storage unit Uf; The logical zero of bit line BL (n) makes transistor M2 and M5 conducting, and transistor M1 then closes and makes node np1 be similar to suspension joint, and voltage VVDD1 descends; With at storage unit Uf (m; N) the conducting degree of reduction transistor P1 in is quickened the voltage via gateway transistor T 1 discharge reduction node Q, and it is more smooth to make writing of logical zero can carry out ground.So, RAS 107 just can improve writing of logical one and writing of logical zero comparatively all sidedly.
Please refer to Figure 15 and Figure 16; Figure 15 is applied to a kind of embodiment of dual-port eight transistor static storage cells for RAS of the present invention, and Figure 16 illustrates the operation situation of the RAS among Figure 15.In the present embodiment, be provided with a plurality of storage unit that are arranged in a plurality of row in the RAS 108, among Figure 15 with n row storage unit Ue (m, n) with Ue (m ', n) as the representative.(m n) is example, and it is to be the dual-port static storage unit with storage unit Ue; Wherein, Transistor P1 and N1 form phase inverter iv1, transistor P2 and N2 and form another phase inverter iv2, and this two phase inverters iv1 and iv2 form the breech lock framework, to store one data at node Q and QB.(m, node nb1 n) and nb2 can be considered two differential position ends of same port to storage unit Ue, couple the bit line BLB1 (n) of bit line BL1 (n) and anti-phase respectively; Transistor T 1 and T2 this to the gateway transistor according to the voltage of character line WL1 (m) respectively Control Node Q and QB whether can conducting to bit line BL1 (n) and BLB1 (n).In like manner, node nb3 and nb4 are two differential position ends of another port, couple bit line BL2 (n) and BLB2 (n) respectively, and gateway transistor T 3 is controlled bit line BL2 (n) and the access of BLB2 (n) to node Q and QB with T4 respectively according to another character line WL2 (m).Utilize eight transistorized storage unit, RAS 108 can be realized out the static RAM of an even port (dual port).
For promoting writing usefulness, improving the characteristic write running of eight transistor static storage cells; Can corresponding power circuit be set for each array storage unit in the RAS 108; Power circuit PC8 (n) among Figure 15 is promptly corresponding to n each storage unit Ue (m that is listed as; N) with Ue (m ', n).Be provided with power switch 28a, 28b and electric power maintainer 38a, 38b among the power circuit PC8 (n), with voltage VVDD1 and the VVDD2 of regulation and control node np1 and np2.Node np1 and np2 are coupled to node ns1 and the ns2 in each storage unit of same row respectively, make voltage VVDD1 and VVDD2 can be respectively as the source electrode supply voltage of transistor P1 and P2.Be provided with transistor M1 and Sheffer stroke gate ND1 among the power switch 28a; The source electrode of transistor M1 (like a p channel metal oxide semiconductor transistor) couples WV VDD and node np1 respectively with drain electrode; Sheffer stroke gate ND1 does anti-and logical operation with bit line BL1 (n) with the data voltage of BL2 (n), and transistor M1 is then according to the conducting between anti-and logic operation result Control Node np1 and WV VDD.Electric power maintainer 38a can be realized by transistor M3 (like a p channel metal oxide semiconductor transistor); Compared to transistor M1, transistor M3 is a transistor that ducting capacity is more weak.When transistor M1 stop conducting, node np1 is similar to suspension joint and makes voltage VVDD1 decline depart from WV VDD; 3 of the electric current I of transistor M3 conducting can assist to keep suitable voltage VVDD1.Symmetrically, be provided with transistor M2 (can mate) and Sheffer stroke gate ND2 among the power switch 28b, with the anti-conducting that reaches between logic operation result Control Node np2 and WV VDD according to bit line BLB1 (n) and BLB2 (n) with transistor M1.Transistor M4 among the electric power maintainer 38b then can mate with transistor M3; When transistor M2 closes and when making the approximate suspension joint of node np2, the electric current I 4 of transistor M4 conducting can assist to keep suitable voltage VVDD2.
The operation situation of RAS 108 can be summarized as follows.When RAS 108 operated on standby mode, bit line BL1 (n), BL2 (n), BLB1 (n) were logical one with BLB2 (n), and transistor M1 and M2 conducting make voltage VVDD1 and VVDD2 normal dimensions be held in WV VDD.Write fashionablely in any pair of bit lines BL1 (n)/BLB1 (n) or BL2 (n)/BLB2 (n), the operation situation of power circuit PC8 (n) is similar to the power circuit PC2 (n) among Fig. 3.
Write fashionable; Suppose RAS 108 will via bit line BL1 (n)/this port of BLB1 (n) with logical one write to storage unit Ue (m, n), so character line WL1 (m) can turn-on transistor T1 and T2; Bit line BL1 (n) is a logical one, and bit line BLB1 (n) is a logical zero.The bit line BLB1 (n) of logical zero can close transistor M2, makes the approximate suspension joint of node np2 and reduces voltage VVDD2; Storage unit Ue (m, n) in, therefore the conducting degree of transistor P2 can reduce, the voltage of node QB also can descend, upset is logical zero via 2 discharges of gateway transistor T more easily to make node QB.In addition, logical one bit line BL1 (n) makes transistor M1 conducting, and voltage VVDD normal dimensions is held in WV VDD, make storage unit Ue (m, the transistor P1 in n) can be successfully with the high voltage of node Q conducting to logical one.
In summary, discussed like the front, modern RAS faces the demand contradictory between reading and writing.If be optimized (similarly being in storage unit, to adopt more weak gateway transistor) to the demand that reads, usefulness and the characteristic that writes running be deterioration relatively.Write running for taking into account; RAS of the present invention is respectively to classify the basis as; Come regulation and control that two phase inverters that form the breech lock framework in each storage unit of same row are supplied power respectively according to the data of bit line; The resistance memory cell data that can weaken write the tendency of (data upset), and keep/strengthen the tendency that storage unit acceptance/driving data writes (data upset), to promote the usefulness that data write; Improve the characteristic (similarly being signal noise nargin) write running, the speed, usefulness and the characteristic that RAS of the present invention can be taken into account read and write.
In some technology; Can when writing a certain storage unit be corresponding word line acts provide extra high voltage (voltage that is higher than logical one) increasing the transistorized conducting degree of gateway, but this can cause comparatively serious half selected select interference (half-select disturb) problem and degree of stability (stability) doubt; That is to say that concerning same delegation, couple other storage unit of same character line, the transistorized conducting degree of its gateway also can increase, and makes its stored data by upset by error easily.In comparison, the present invention does not need extra raising word line voltages when the storage unit of access delegation, can not cause the half selected interference problem of selecting.In other prior art, then can more weak supply voltage be provided writing two phase inverters of fashionable unification to each storage unit; The tendency that the resistance memory cell data write though this kind prior art can weaken, the feedback mechanism of latch circuit is also related to be weakened, and can't improve data all sidedly and write running.And because this prior art will be simultaneously for two phase inverters of storage unit switch supply voltage in the lump, power consumption is higher, and speed is also slower, and the time of accomplishing switching is longer.In comparison, each phase inverter that The present invention be directed in each storage unit carries out the supply voltage regulation and control separately, writes usefulness so can more fully promote; And the present invention only is required to be phase inverter and switches supply voltage, and power consumption can be kept to half the, and switch speed also can be accelerated.
Some prior art can increase extra transistor and carry out the supply voltage regulation and control for two phase inverters of breech lock framework in storage unit.But, this will make the layout area of storage unit increase, and be unfavorable for the lifting of layout aggregation degree.In addition, owing to all extra transistor need be set in each storage unit of same row, so can significantly increase the length and the load of bit line, the response speed of bit line is reduced, data are read and write all has adverse influence.Compared to this kind prior art; The present invention need not change the basic framework of storage unit; Can in storage unit, not set up extra transistor; Same array storage unit is shared same power circuit, so the influence of pairs of bit line load, operational effectiveness, layout area and total lock number (gate count) is all very little.In addition, because the present invention carries out supply voltage regulation and control according to the sequential of bit line data, thus do not need extra sequential control, but also resisting process, temperature and/or various circuit characteristics that voltage drift caused make a variation.
The above only is embodiments of the invention, is not the present invention is done any pro forma restriction; Though the present invention discloses as above with embodiment; Yet be not that any those skilled in the art are not in breaking away from technical scheme scope of the present invention in order to qualification the present invention; When the technology contents of above-mentioned announcement capable of using is made a little change or is modified to the equivalent embodiment of equivalent variations; In every case be not break away from technical scheme content of the present invention, to any simple modification, equivalent variations and modification that above embodiment did, all still belong in the scope of technical scheme of the present invention according to technical spirit of the present invention.
Claims (10)
1. RAS, it includes:
A plurality of storage unit that are arranged as row, each storage unit is provided with one first power end, one second power end and an end, and the position end of said a plurality of storage unit all is coupled to same bit line, and each storage unit includes:
One first phase inverter has a power end, an input end and an output terminal, couples this first power end, one second back end and one first back end respectively;
One second phase inverter has a power end, an input end and an output terminal, couples this second power end, this first back end and this second back end respectively; And
One gateway transistor, an end couples this end, and the other end couples one of them of this second back end and this first back end; And
One power circuit is provided with a feeder ear, couples first power end of said a plurality of storage unit; This power circuit includes:
Whether one power switch couples this bit line and this feeder ear, will be with this feeder ear conducting to a WV with the voltage decision according to this bit line.
2. RAS according to claim 1 is characterized in that: this power circuit includes in addition:
One electric power maintainer couples this feeder ear; When this power switch during not with this feeder ear conducting to this WV, this electric power maintainer provides an electric current in this feeder ear.
3. RAS according to claim 1 is characterized in that: this power switch includes:
One power transistor has a grid and two links, couples this bit line, this WV and this feeder ear respectively.
4. RAS according to claim 3 is characterized in that: this power switch includes in addition:
One logical circuit is coupled between this grid and this bit line; This logical circuit carries out logical operation with the voltage and a write control signal of this bit line, and this power transistor be according to the decision of the operation result of this logical circuit whether with this feeder ear conducting to this WV.
5. RAS according to claim 1; It is characterized in that: the gateway transistor in each storage unit is coupled between this first back end and this end; And each storage unit is provided with a "A" end of car in addition; And include one second gateway transistor in addition, be coupled between this second back end and this "A" end of car; The "A" end of car of said a plurality of storage unit all is coupled to one second bit line; This power circuit is provided with one second feeder ear in addition, couple second power end of said a plurality of storage unit, and this power circuit includes in addition:
Whether one second power switch couples this second bit line and this second feeder ear, will be with this second feeder ear conducting to this WV with the voltage decision according to this second bit line.
6. RAS according to claim 1 is characterized in that: each storage unit in said a plurality of storage unit is provided with one the 3rd power end and one the 4th power end in addition; First phase inverter in each storage unit is provided with a second source end in addition, couples the 3rd power end; Second phase inverter in each storage unit is provided with a second source end in addition, couples the 4th power end; And this RAS includes in addition:
One second source circuit is provided with a feeder ear, couples the 4th power end of said a plurality of storage unit;
And this second source circuit includes:
Whether one second power switch couples the feeder ear of this bit line and this second source circuit, will be with feeder ear conducting to one second WV of this second source circuit with the voltage decision according to this bit line; Wherein this second WV and this WV are different.
7. RAS according to claim 6 is characterized in that: this second source circuit includes in addition:
One second electric power maintainer is coupled to the feeder ear of this second source circuit; When this second power switch during not with feeder ear conducting to this second WV of second source circuit, this second electric power maintainer provides an electric current in the feeder ear of this second source circuit.
8. RAS according to claim 1; It is characterized in that: the gateway transistor in each storage unit is coupled between this first back end and this end; And each storage unit is provided with a "A" end of car, one the 3rd power end and one the 4th power end in addition; And include one second gateway transistor in addition, be coupled between this second back end and this "A" end of car; And first phase inverter in each storage unit is provided with a second source end in addition, couples the 3rd power end; Second phase inverter in each storage unit is provided with a second source end in addition, couples the 4th power end; The "A" end of car of said a plurality of storage unit all is coupled to one second bit line, and this RAS includes in addition:
One second source circuit is provided with a feeder ear, couples the 4th power end of said a plurality of storage unit;
And this second source circuit includes:
Whether one second power switch couples the feeder ear of this second bit line and this second source circuit, will be with feeder ear conducting to one second WV of this second source circuit with the voltage decision according to this second bit line; Wherein this second WV and this WV are different.
9. RAS according to claim 1; It is characterized in that: the gateway transistor in each storage unit is coupled between this first back end and this end; And each storage unit is provided with a "A" end of car and one second gateway transistor in addition, and this second gateway transistor is coupled between this first back end and this "A" end of car; The "A" end of car of said a plurality of storage unit all is coupled to one second bit line, and the power switch in this power circuit according to the voltage decision of the voltage of this bit line and this second bit line whether with this WV conducting to this feeder ear.
10. RAS according to claim 9 is characterized in that: include in this power switch:
One power transistor has a grid and two links, and this two link couples this WV and this feeder ear respectively;
One logical circuit is coupled between grid, this bit line and this second bit line of this power transistor; This logical circuit carries out logical operation with the voltage of this bit line and the voltage of this second bit line, and this power transistor be according to the decision of the operation result of this logical circuit whether with this feeder ear conducting to this WV.
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| CN109408423A (en) * | 2018-10-11 | 2019-03-01 | 珠海格力电器股份有限公司 | memory chip cascade expansion circuit and control circuit |
| CN112558669A (en) * | 2020-12-10 | 2021-03-26 | 无锡中微亿芯有限公司 | FPGA distributed power supply network with self-test adjustable function |
| CN115050406A (en) * | 2022-08-17 | 2022-09-13 | 安徽大学 | Bit line leakage current compensation circuit and module of SRAM (static random Access memory) and memory |
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| CN1790547A (en) * | 2004-11-22 | 2006-06-21 | 国际商业机器公司 | Sram with dynamically asymmetric cell |
| CN1979691A (en) * | 2005-12-07 | 2007-06-13 | 松下电器产业株式会社 | Semiconductor memory device |
| CN101599300A (en) * | 2008-06-05 | 2009-12-09 | 阿尔特拉公司 | Utilize the static random-access memory of boosted voltage |
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| CN1790547A (en) * | 2004-11-22 | 2006-06-21 | 国际商业机器公司 | Sram with dynamically asymmetric cell |
| CN1979691A (en) * | 2005-12-07 | 2007-06-13 | 松下电器产业株式会社 | Semiconductor memory device |
| CN101599300A (en) * | 2008-06-05 | 2009-12-09 | 阿尔特拉公司 | Utilize the static random-access memory of boosted voltage |
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| CN109408423A (en) * | 2018-10-11 | 2019-03-01 | 珠海格力电器股份有限公司 | memory chip cascade expansion circuit and control circuit |
| CN112558669A (en) * | 2020-12-10 | 2021-03-26 | 无锡中微亿芯有限公司 | FPGA distributed power supply network with self-test adjustable function |
| CN115050406A (en) * | 2022-08-17 | 2022-09-13 | 安徽大学 | Bit line leakage current compensation circuit and module of SRAM (static random Access memory) and memory |
| CN115050406B (en) * | 2022-08-17 | 2022-10-25 | 安徽大学 | Bit line leakage current compensation circuit and module of SRAM (static random Access memory) and memory |
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