CN102411344B - Clock synchronization method for distributed control system - Google Patents

Clock synchronization method for distributed control system Download PDF

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CN102411344B
CN102411344B CN2011101744176A CN201110174417A CN102411344B CN 102411344 B CN102411344 B CN 102411344B CN 2011101744176 A CN2011101744176 A CN 2011101744176A CN 201110174417 A CN201110174417 A CN 201110174417A CN 102411344 B CN102411344 B CN 102411344B
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clock
time
dcs
major
local
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CN102411344A (en
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陈智
张玉兰
马立杰
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6th Research Institute Of China Electronics Corp Intelligent System Co ltd
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Beijing Hitachi Control Systems Co Ltd
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
    • Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

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Abstract

The invention relates to a high-precision clock synchronization method for a distributed control system. The method comprises the following steps of: acquiring an initial real-time time with relatively low precision (due to network delay and processing discrete influence) from master clock equipment through a distributed control system network by a card in a simple communication mode, capturing a high-precision local clock count valve corresponding to a time pulse leading edge moment produced in a whole second moment period by synchronously utilizing an input capturing module of a microprocessor in the card through the clock so as to obtain a precise clock error; and regulating a local clock rate through a dynamic smooth correction algorithm, so that the local clock accurately tracks the master clock, monotonic increase of the clock can be guaranteed, and that an event time sequence of the distributed control system is acquired in an error-free mode is guaranteed. The microprocessor in the card also comprises an output comparison module, when the master clock fails, the output comparison module generates agent output time pulse, and high-precision synchronization of the local clocks of various cards is continuously kept.

Description

The method for synchronous of dcs clock
Technical field
The present invention relates to a kind of high-precise synchronization method of dcs clock, relate in particular to a kind of method of high-precise synchronization of the clock of regulating a plurality of fasteners by the Dynamic Closed Loop Control mode.
Background technology
Dcs has been widely used in various industrial process controls field at present, its distributed systems structure is when improving system reliability, also the information synchronization between each fastener has been proposed requirements at the higher level, clock then is the basis of satisfying information synchronization synchronously.The information record that with the time sequencing is principal character is the important evidence that industrial process is controlled operation in service, statistics, analysis and fault handling, and high precision clock is that the accuracy of information record has improved important assurance.But precision, the degree of stability of the clock source frequency of clock self can make the clock generating error, and the uncertainty that dcs network communication time-delay, software are handled time-delay and these time-delays can exert an influence to the synchronous precision of clock.
Existing general clock synchronizing method as shown in Figure 1, this dcs 100 ' comprises that dcs network 1 ', the major clock module 2 ' that links to each other with dcs network 1 ' and an end link to each other some fasteners 3 ' of the arrangement arranged side by side that the other end links to each other with the major clock module with dcs network 1 '.Major clock in the major clock module can whole second constantly send to the time pulse, fastener 3 ' by software to the time handle to clock correction and take error directly to eliminate (directly to time) mode, be difficult to reach the microsecond level like this with interior synchronization accuracy.Perhaps adopt professional chip, and the decentralized configuration demand of dcs has determined that fastener quantity is more, can cause cost to improve like this.The time one-way of this external clock is to guarantee dcs information record order basis accurately and reliably, need for this reason suitable correction algorithm replace directly to the time modification method.
Summary of the invention
At the deficiencies in the prior art, the technical matters that the present invention solves provides a kind of method that realizes the clock high-precise synchronization of a plurality of fasteners in the dcs.
For solving the problems of the technologies described above, technical scheme of the present invention is achieved in that a kind of clock synchronizing method of dcs, major clock module and an end of the band major clock that this dcs comprises the dcs network, link to each other with the dcs network link to each other with the dcs network, some fasteners of the arrangement arranged side by side that the other end links to each other with the major clock module, said method comprising the steps of 1) the initial real-time time of local clock that is provided with of fastener obtains from major clock with communication modes by the dcs network; 2) fastener is provided with microprocessor, this microprocessor comprise the input capture module be used for catching major clock to the time pulse signal, record local clock counter value obtains accurate clocking error; 3) use the Dynamic Closed Loop Control mode to regulate the local clock frequency, make local clock accurate tracking major clock.
Further, described microprocessor also comprises an output comparison module, when the major clock fault, the output comparison module produce agency's output to the time pulse, keep the local clock of each fastener synchronous.
Further, the maximum error of input capture module and output comparison module all can be controlled in a microprocessor dominant frequency within clock cycle.
Further, described each fastener is according to time priority principle competition attorneyship, and the fastener that arrived at first constantly in whole second preferentially obtains attorneyship, produce agency's output to the time pulse and shield other fastener and produce the agency.
Further, described agency output to the time pulse pulsewidth less than major clock to the time pulse pulsewidth.
Further, described major clock to the time pulse recover, agency's output to the time pulse withdraw from.
Further, have a two-way Shu Ru output circuit in the described fastener, with major clock to the time pulse be connected.
Further, described two-way Shu Ru output circuit is to draw on weak open collector to drive output, allow simultaneously a plurality of outputs drive to the time pulse, constitute line and relation.
Compared with prior art, the invention has the beneficial effects as follows: regulate local clock speed by the Dynamic Closed Loop Control mode, make local clock accurate tracking major clock, and can guarantee the monotone increasing of clock simultaneously, guarantee that the zero defect of dcs event time order obtains.
Description of drawings
Figure 1 shows that prior art dcs clock principle schematic;
Fig. 2 is dcs clock principle schematic of the present invention;
Fig. 3 be among Fig. 2 two-way input the output circuit principle schematic;
Fig. 4 is the algorithm control block diagram of dynamic smoothing correction.
Embodiment
Be described in detail below with reference to the clock synchronization control method of accompanying drawing to dcs of the present invention.
As shown in Figure 2, dcs 100 of the present invention (DCS) comprises that dcs network 1, the major clock module 2 that links to each other with dcs network 1 and an end link to each other some fasteners 3 of the arrangement arranged side by side that the other end links to each other with major clock module 2 with dcs network 1.Be provided with microprocessor (not shown) in the fastener 3, this microprocessor comprises input capture module and output comparison module, and the former can be used for accurately catching the generation moment of pulse edge, and the latter can accurately be implemented in to specify and export pulse constantly.Both maximum errors all can be controlled in a microprocessor dominant frequency within clock cycle.
Major clock module 2 comprises major clock, and each fastener 3 comprises the local clock synchronous with major clock.The local clock of each fastener 3 is by second integer counter Ts and second decimal counter T fConstitute, the Ts per second adds 1, T fWith the microprocessor dominant frequency f in the fastener MAs impulse source, f is not being considered in every meter zero clearing in full 1 second 1 time MDuring error, T fThe full N of the every meter of counter f=f MThe time zero clearing, N fBe called the zero clearing pre-value.Fastener 3 at first obtains initial real-time clock message by dcs network 1 from major clock, and in addition suitable compensation such as network delay back assignment brings into operation to local clock.Since synchronization accuracy mainly by subsequent step to the time pulse guarantee, can simply compensate as network delay with the network communication cycle here; Also can begin by sending claim frame to major clock, compensate as network delay to half that receives local clock interval till the acknowledgement frame.Can obtain the message clocking error thus, when the message clocking error is big (＞=± 0.5s, this situation usually only can take place when clock is just subsynchronous), with take directly to the time method correction local clock, simultaneity factor provides clock amendment record prompting local zone time and has saltus step.Message clocking error between local clock and major clock is (＜± 0.5s, under the normal condition) hour, not according to message clocking error correction local clock.
As shown in Figure 3, major clock each whole second constantly send one to the time pulse, its pulse width is defined as T B, impulse form is to draw on weak open collector to drive output (OC), corresponding whole second of its negative edge is constantly.Have in the fastener 3 a two-way input output (I/O) circuit, this two-way input output circuit link to each other with output comparison module and input capture module.The two-way Shu Ru output circuit of fastener 3 is to draw on weak open collector to drive output (OC), thus allow simultaneously a plurality of outputs drive to the time pulse, constitute line and relation.Wherein, two-way Shu Ru output circuit with to the time pulse be connected, under the normal condition output comparison module do not work, it is output as low level, output triode Q1 ends, do not influence to the time pulse level.To the time pulse send the input capture module of microprocessor after oppositely through level translation loop (triode Q2).
The impulse meter of input capture module and a second decimal counter T fShare same microprocessor counter, when the edge sense circuit of input capture module detect to the time rising edge of a pulse (because the acting in opposition of Q2 makes negative edge be transformed to rising edge), record current T at once fCount value N 0Because whole second should corresponding count value be 0 constantly, therefore can obtain the error of i moment second local clock and major clock (with T fThe umber of pulse of counter is unit) be:
Δ N (i)=0-N 0(i)=-N 0(i) N 0(i)＜N fO'clock (i-1)/2
Or Δ N (i)=N f(i-1)-N 0(i) N 0(i)＞=N fO'clock (i-1)/2
Error correction realizes by a tape speed type pi regulator closed loop control algorithm, i.e. a kind of Dynamic Closed Loop Control algorithm, and its control object is local clock, the control object model is single order integral element, as shown in Figure 4.The purpose of this algorithm is to realize that a kind of dynamic smoothing correction algorithm guarantees the unidirectional stable operation of local clock, prevents the clock saltus step.Its principle of work is: after error delta N (i) regulates calculating through the velocity profile pi regulator, and the umber of pulse Δ N that output need be revised f(i), use Δ N then f(i) revise the i zero clearing pre-value N of second f(i), namely revise back N f(i)=f M-Δ N f(i), represent the N that i comprises second f(i) individual count value.Less N f(i) corresponding short interval second, otherwise bigger N f(i) be equivalent to regulate the speed of local clock at interval corresponding long second, realized the clock correction.When reading clock, at first read T fCounter currency N L(i), then second fraction part can obtain by back formula conversion: N L(i)/N f(i).Regulate local clock speed by the Dynamic Closed Loop Control mode, make local clock accurate tracking major clock, and can guarantee the monotone increasing of clock simultaneously, guarantee that the zero defect of dcs event time order obtains.
The microprocessor of fastener 3 also dispose one to the time pulse time-out count device, when to the time pulse time-out count device when overflowing, expression to the time pulse lose, this moment fastener 3 will start the output comparison module local clock whole second constantly act on behalf of major clock export to the time pulse, the clock that continues to keep each fastener 3 is synchronous.Each fastener 3 is according to time priority principle competition attorneyship, the fastener 3 preferential attorneyships that obtain that namely arrived at first constantly in whole second, and by to the time pulse shield other fasteners 3 and produce the agency.Clock controller quits work and exports Δ N at this moment f(i) remain unchanged, namely keep last zero clearing pre-value N f(i)=f M-Δ N f(i) constant, with the local clock replacement major clock of this fastener 3.Set the output comparison module, make it at T fHigh level is exported in counter O reset constantly, drives triode Q1 saturation conduction, conversion level and oppositely, produce the agency to the time pulse negative edge.And then set the output comparison module, make the pulse width time-delay back that keeps regulation (may be prescribed as T B/ 2) output low level, triode Q1 ends, finish once to the time pulse agency output.Agency output to the time pulse (exporting comparison module output high level) during, forbid the input capture module, during output comparison module output low level, enable the input capture module.
Whenever the input capture module capture to the time pulse, all make the zero clearing of time-out count device, so T fCounter O reset constantly a little earlier fastener 3 will preferentially obtain to the time pulse attorneyship, T fCounter O reset moment fastener 3 after a while forbids producing the agency owing to the time-out count device is cleared.If to the time pulse agency during, major clock to the time pulse recover normal, because the pulse width of regulation major clock is greater than agency's pulse width, if agency output to the time pulse input that finishes to detect the input capture module in the back still be high level, can judge pulse output when having 3 pairs of major clock or other fasteners, zero clearing time-out count device is forbidden this fastener 3 agencies.
To those skilled in the art, obviously the invention is not restricted to the details of above-mentioned one exemplary embodiment, and under the situation that does not deviate from spirit of the present invention or essential characteristic, can realize the present invention with other concrete form.Therefore, no matter from which point, all should regard embodiment as exemplary, and be nonrestrictive, scope of the present invention is limited by claims rather than above-mentioned explanation, therefore is intended to include in the present invention dropping on the implication that is equal to important document of claim and all changes in the scope.Any Reference numeral in the claim should be considered as limit related claim.
In addition, be to be understood that, though this instructions is described according to embodiment, but be not that each embodiment only comprises an independently technical scheme, this narrating mode of instructions only is for clarity sake, those skilled in the art should make instructions as a whole, and the technical scheme among each embodiment also can form other embodiments that it will be appreciated by those skilled in the art that through appropriate combination.

Claims (1)

1. the method for synchronous of a dcs clock, major clock module and an end of the band major clock that this dcs comprises the dcs network, link to each other with the dcs network link to each other with the dcs network, some fasteners of the arrangement arranged side by side that the other end links to each other with the major clock module, it is characterized in that: said method comprising the steps of
1) the initial real-time time of local clock that is provided with of described fastener obtains from major clock with communication modes by the dcs network;
2) described fastener is provided with microprocessor, this microprocessor comprise the input capture module be used for catching major clock to the time pulse signal, record local clock counter value obtains clocking error;
3) use the Dynamic Closed Loop Control mode to regulate the local clock frequency, make local clock follow the tracks of major clock;
Described microprocessor also comprises an output comparison module, when the major clock fault, the output comparison module produce agency's output to the time pulse, keep the local clock of each fastener synchronous.
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CN103684728B (en) * 2012-09-04 2016-11-02 中国航空工业集团公司第六三一研究所 FC network clocking synchronous error compensation method
JP6334272B2 (en) * 2014-06-03 2018-05-30 株式会社日立製作所 Distributed control device
CN104078089B (en) * 2014-06-25 2016-06-15 中广核核电运营有限公司 A kind of dcs of nuclear power station unit and the method for clock synchronous thereof
CN104506888B (en) * 2014-12-31 2018-05-22 广东威创视讯科技股份有限公司 Clock synchronization apparatus, method and system
JP6400553B2 (en) * 2015-09-28 2018-10-03 ファナック株式会社 Numerical control system with synchronous control function between units
CN109283864B (en) * 2017-07-21 2020-05-05 北京智云芯科技有限公司 Time synchronization and calibration method and system for data sampling
CN109343325A (en) * 2018-11-15 2019-02-15 中国直升机设计研究所 A kind of helicopter analog machine clock synchronizing method and system
CN111181555B (en) * 2019-12-31 2023-09-12 瑞斯康达科技发展股份有限公司 PTP clock synchronization system and clock synchronization method
CN112540641B (en) * 2020-10-29 2024-04-12 珠海格力电器股份有限公司 Clock precision correction method, device and storage medium
CN115268570B (en) * 2022-08-05 2023-05-26 江苏云涌电子科技股份有限公司 IRIG-B code time setting system

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CN101227246A (en) * 2008-01-28 2008-07-23 中兴通讯股份有限公司 Method and apparatus for master-salve clock synchronization
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Effective date of registration: 20230426

Address after: No. 5, Lutuan Road, South District of Future Science City, Changping District, Beijing, 102209

Patentee after: THE 6TH RESEARCH INSTITUTE OF CHINA ELECTRONICS CORPORATION, INTELLIGENT SYSTEM CO.,LTD.

Address before: M7 Building, No.1 Jiuxianqiao East Road, Chaoyang District, Beijing, 100016

Patentee before: BEIJING HITACHI CONTROL SYSTEM Co.,Ltd.