CN102404261A - Blind separation device based on BPSK/QPSK/8QAM (binary phase shift keying/quaternary phase shift keying/8-quadrature amplitude modulation) modulation signal - Google Patents
Blind separation device based on BPSK/QPSK/8QAM (binary phase shift keying/quaternary phase shift keying/8-quadrature amplitude modulation) modulation signal Download PDFInfo
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Abstract
The invention discloses a blind separation device based on BPSK/QPSK/8QAM (binary phase shift keying/quaternary phase shift keying/8-quadrature amplitude modulation) modulation signals, wherein a radio frequency front-end processing unit 1 of the blind separation device is connected with a digital signal processor 3 via an input buffer 2; the digital signal processor 3 is connected with a field programmable gate array FPGA unit 5 and a signal output unit 6 via an output buffer 4 respectively; the field programmable gate array FPGA unit 5 is connected with a video output unit 7; the video output unit 7 is connected with an LCD liquid crystal display 8; and a timing and control unit 12 is connected with the radio frequency front-end processing unit 1, the input buffer 2, a first off-chip data memory 9a, a second off-chip data memory 9b, a FLASH memory 10, the output buffer 4, the field programmable gate array FPGA unit 5, the video output unit 7 and the digital signal processor 3 respectively. The device can eliminate interference signals, improve communication quality, and separate two paths of hybrid communication signals.
Description
Technical field
The present invention relates to a kind of blind separation device, belong to the blind signal separation technical field based on the BPSK/QPSK/8QAM modulation signal.
Background technology
Blind separation is under information source
condition of unknown, carries out the separation of separate source signal through the mixed signal
that receives.Signal of communication not only has interference signal in the reality, and can strengthen the difficulty of receiving system signal processing with the signal mixed transport of the identical or different modulation system of multichannel.Blind separation device in the blind signal separation field is just handled to the two-way audio mixed signal at present, does not but have to support the processing to two-way signal of communication and interference signal.
For example, the Chinese invention patent application discloses " a kind of continuous processing formula mixed audio blind separation device " (patent publication No. is CN101009950), and this device is is mainly connected and composed by casing and internal circuit board and Horn loudspeaker box jointly; Receive two kinds of mixed audio signals respectively by passage 1 and passage 2, through separated straight, filtering; Send into amplifier, carry out the encoding and decoding and the analog-to-digital conversion of mixed audio signal then, under the control of digital signal processor; Mixed audio signal is carried out separating treatment; Become two kinds of independently digital audio and video signals, finally, two kinds of simulated audio signals are exported from analog signal output through analog-to-digital conversion and Filtering Processing.But this device but can not carry out separate source signal separation to the mixed communication signal under two-way signal of communication and the band interference signals condition of mixing, and in other words, this device can not be isolated independently signal of communication in the removal interference signal.
Summary of the invention
The objective of the invention is to the deficiency that exists in the prior art; A kind of blind separation device based on the BPSK/QPSK/8QAM modulation signal is provided; This device carries out blind separating treatment with the mixed signal that receives; Can not only remove interference signal, improve communication quality, and can separate two-way mixed communication signal.
In order to reach above-mentioned goal of the invention, the present invention adopts following technical scheme:
A kind of blind separation device based on the BPSK/QPSK/8QAM modulation signal; It comprises the radio-frequency front-end processing unit 1 of gathering the mixed communication signal, digital signal processor 3, sequential and control unit 12, first outer data storage 9a, second outer data storage 9b, FLASH memory 10, output buffer 4, on-site programmable gate array FPGA unit 5, video output unit 7, LCD LCDs 8, signal output unit 6, jtag interface 11, input buffer 2; It is characterized in that the output of the radio-frequency front-end processing unit 1 of above-mentioned collection mixed communication signal links to each other with digital signal processor 3 through input buffer 2; The output of digital signal processor 3 links to each other with signal output unit 6 with on-site programmable gate array FPGA unit 5 respectively through output buffer 4, and the output of on-site programmable gate array FPGA unit 5 links to each other with video output unit 7; Video output unit 7 outputs link to each other with LCD liquid crystal display 8, digital signal processor 3 respectively with first outer data storage 9a, second jtag interface 11 that outer data storage 9b, FLASH memory 10 and device modulates are used; Sequential and control unit 12 are connected with radio-frequency front-end processing unit 1, input buffer 2, first outer data storage 9a, second outer data storage 9b, FLASH memory 10, output buffer 4, on-site programmable gate array FPGA unit 5, video output unit 7 and digital signal processor 3 respectively.
Above-mentioned radio-frequency front-end processing unit 1 comprises two antennas 101, band pass filter 102, radio frequency chip 103; Two antennas 101 are connected with band pass filter 102, and band pass filter 102 is connected with chip 103, and this radio-frequency front-end processing unit 1 is used to receive the filtering of signal; Mixing; Amplify, generate baseband signal after the analog-to-digital conversion, baseband signal from input buffer 2 through IO oral instructions to digital signal processor 3.
Above-mentioned sequential and control unit 12 are the EPM3128ATC100 chip, are used to produce clock and control signal.
Above-mentioned digital signal processor 3 is the processor of chip model TMS320DM642
,This digital signal processor 3 is used to receive the clock and the baseband signal of control radio-frequency front-end processing unit 1, the baseband signal of first outer data storage 9a, the baseband signal of second outer data storage 9b, the baseband signal of on-site programmable gate array FPGA unit 5, the baseband signal of FLASH memory 10 from sequential and control unit 12 generations, carries out denoising and with cluster mixed signal is carried out separating of signal.
Above-mentioned first outer data storage 9a, second outer data storage 9b are respectively MT48LC4M32B2 type memory, and two MT48LC4M32B2 type memories are that TMS320DM642 processor 3 links to each other with the chip model respectively.First outer data storage 9a, second outer data storage 9b are used to deposit baseband signal that receives and the data that obtain through digital signal processor 3 blind separating treatment.
Above-mentioned FLASH memory 10 is an AM29LV400 type memory, and this FLASH memory 10 is used to deposit the blind signal separation algorithm routine.
Above-mentioned on-site programmable gate array FPGA unit 5 is connected with video output unit 7, and on-site programmable gate array FPGA unit 5 is used for the demonstration of control of video and strengthens the definition of video image.
A kind of blind separation device based on the BPSK/QPSK/8QAM modulation signal of the present invention compared with prior art; Have following conspicuous substantive distinguishing features and remarkable advantage: the radio-frequency front-end processing unit 1 of this device is gathered mixed signal by two antennas of keeping at a distance; Change the mixed signal that receives into baseband signal; Utilize sequential and control unit that the signal Synchronization that receives is carried out denoising; Can carry out filtering to interference signal, then, give digital signal processor 3 with transfer of data through the IO mouth; Carry out the cluster of signal according to the characteristic of the various modulation systems of signal of communication, estimate the number in primary signal source in real time and separate two-way mixed communication signal.
Description of drawings
Fig. 1 is the schematic representation of apparatus of a kind of blind separation device embodiment based on the BPSK/QPSK/8QAM modulation signal of the present invention;
Fig. 2 is the circuit block diagram of radio-frequency front-end unit 1 among Fig. 1;
Fig. 3 is the circuit block diagram of sequential and control unit 12 among Fig. 1;
Fig. 4 is the circuit block diagram of digital signal processor 3 among Fig. 1;
Fig. 5 is the circuit block diagram of first outer data storage 9a, second outer data storage 9b among Fig. 1;
Fig. 6 is the circuit block diagram of on-site programmable gate array FPGA unit 5 among Fig. 1;
Fig. 7 is the circuit block diagram of video output unit 7 among Fig. 1.
Embodiment
Below in conjunction with accompanying drawing and embodiment the preferred embodiment of invention is done further explain.
As shown in Figure 1; A kind of blind separation device of the present invention based on the BPSK/QPSK/8QAM modulation signal; It comprises the radio-frequency front-end processing unit 1 of gathering the mixed communication signal, digital signal processor 3, sequential and control unit 12, first outer data storage 9a, second outer data storage 9b, FLASH memory 10, output buffer 4, on-site programmable gate array FPGA unit 5, video output unit 7, LCD LCDs 8, signal output unit 6, jtag interface 11, input buffer 2; It is characterized in that the output of the radio-frequency front-end processing unit 1 of above-mentioned collection mixed communication signal links to each other with digital signal processor 3 through input buffer 2; The output of digital signal processor 3 links to each other with signal output unit 6 with on-site programmable gate array FPGA unit 5 respectively through output buffer 4, and the output of on-site programmable gate array FPGA unit 5 links to each other with video output unit 7; Video output unit 7 outputs link to each other with LCD liquid crystal display 8, digital signal processor 3 respectively with first outer data storage 9a, second jtag interface 11 that outer data storage 9b, FLASH memory 10 and device modulates are used; Sequential and control unit 12 are connected with radio-frequency front-end processing unit 1, input buffer 2, first outer data storage 9a, second outer data storage 9b, FLASH memory 10, output buffer 4, on-site programmable gate array FPGA unit 5, video output unit 7 and digital signal processor 3 respectively.
Above-mentioned radio-frequency front-end processing unit 1 comprises that two antennas 101, band pass filter 102,103, two antennas 101 of radio frequency chip are connected with band pass filter 102, and band pass filter 102 is connected with chip 103.Above-mentioned radio-frequency front-end processing unit 1 is used to receive the filtering of signal, and mixing is amplified, and generates baseband signal after the analog-to-digital conversion, baseband signal from input buffer 2 through IO oral instructions to digital signal processor 3.The model of above-mentioned band pass filter 102 is FBPF420-120, and its centre frequency is 420MHz.The model of radio frequency chip 13 is nRF24LE1.
As shown in Figure 2, the model of band pass filter 102 is FBPF420-120, and its centre frequency is 420MHz.The model of radio frequency chip 13 is nRF24LE1, and its output links to each other with digital signal processor 3 through input buffer 2.
As shown in Figure 3, above-mentioned sequential and control unit 12 are the EPM3128ATC100 chip, are used to produce clock and control signal.
Above-mentioned digital signal processor 3 is the processor of chip model TMS320DM642, and this digital signal processor 3 is used to receive from sequential and control unit 12 clock that produces and the baseband signal of controlling radio-frequency front-end processing unit 1
,The baseband signal of the baseband signal of the baseband signal of the baseband signal of first outer data storage 9a, second outer data storage 9b, on-site programmable gate array FPGA unit 5, FLASH memory 10 is carried out denoising and with cluster mixed signal is carried out separating of signal.
As shown in Figure 4, the chip model of digital signal processor 3 is TMS320DM642, and its dominant frequency can reach 600MHz, and its address bus is TEA [0-31], and data/address bus is TED [0-63].The address bus TEA [3-22] of TMS320DM642 processor connects the EMIF interface of 64bit, and EMIF is the abbreviation of English External Memory Interface, and its Chinese translation is an external memory interface.The address bus EA [3-22] of EMIF interface; Data/address bus TED [0-63] is connected with the data/address bus ED [0-63] of EMIF interface; The address bus EA [3-22] of EMIF mouth and data/address bus TED [0-63] be the outer data storage 9a of brace respectively, the address wire of 9b and data wire.
Above-mentioned first outer data storage 9a, second outer data storage 9b are respectively MT48LC4M32B2 type memory, and two MT48LC4M32B2 type memories are that TMS320DM642 processor 3 links to each other with the chip model respectively.First outer data storage 9a, second outer data storage 9b are used to deposit baseband signal that receives and the data that obtain through digital signal processor 3 blind separating treatment.
Above-mentioned FLASH memory 10 is an AM29LV400 type memory, and this FLASH memory 10 is used to deposit the blind signal separation algorithm routine.
As shown in Figure 5, the chip model of FLASH memory 10 is AM29LV400, and it is digital signal processor 3 data wires of TMS320DM642 that its data/address bus PD [0-7] connects the chip model, and address bus PA [0-19] connects the address wire of TMS320DM642 processor 3.The data/address bus DQ [0-31] of two chip external memory 9a, 9b links to each other with the ED [0-63] of EMIF mouth, address bus A [0-11], and BA [0-1] is connected with the address wire EA [3-22] of EMIF mouth.When system program was downloaded, program code downloaded in the FLASH memory 10 through data/address bus PD [0-7] through address wire PA [0-19].
Above-mentioned on-site programmable gate array FPGA unit 5 is connected with video output unit 7, and on-site programmable gate array FPGA unit 5 is used for the demonstration of control of video and strengthens the definition of video image.
As shown in Figure 6, the model that on-site programmable gate array FPGA unit 5 adopts is XC2S300E-7TQ208C, and its address bus DC_A [3-22] links to each other with the address wire EA [3-22] of EMIF mouth.Data/address bus DC_D [0-31] is connected with the data wire ED [0-63] of EMIF mouth.The pin that connects video output unit 7 is BK2_1 [1-17].
Above-mentioned video output unit 7 links to each other with on-site programmable gate array FPGA unit 5.Video output unit 7 links to each other with peripheral video equipment, LCD LCDs 8.On-site programmable gate array FPGA unit 5 will the control of video output unit diffusing some distribution map of signal characteristic after the blind separation of 7 outputs.
As shown in Figure 7, video output unit 7 is the Video Decoder of SAA7105H type, and its pin PD [0-11] links to each other with the pin BK2_1 [1-17] of on-site programmable gate array FPGA unit 5.Through pin BLUE_CB_CVBS, GREEN_VBS_CVBS, RED_CR_CCVBS links to each other with LCD LCDs 8.
The jtag interface 11 that the said apparatus debugging is used is the contact pin interface of one 14 pin.Be used for digital signal processor 3 is carried out the emulation and the debugging of program.
With reference to Fig. 1～Fig. 7, the course of work of a kind of blind separation device based on the BPSK/QPSK/8QAM modulation signal of the present invention is:
Radio-frequency front-end processing unit 1 a wherein end links to each other with the wireless mixed signal input of two-way, and the other end links to each other with input buffer 2.Digital signal processor 3 respectively with the outer data storage 9a of sheet, 9b, FLASH memory 10, the jtag interface 11 that device modulates is used is connected with output buffer 4.The output of output buffer 4 links to each other with on-site programmable gate array FPGA unit 5 with signal output unit 6 respectively, and an end of video output unit 7 links to each other with on-site programmable gate array FPGA unit 5, and the other end links to each other with LCD LCDs 8.Sequential and control unit 12 and radio-frequency front-end processing unit 1, the outer data storage 9a of first, second sheet, 9b, FLASH memory 10, on-site programmable gate array FPGA unit 5, video output unit 7 links to each other.
Under the clock signal and control signal effect of sequential and control unit 12 generations; Mixed signal that two-way is wireless gets into radio-frequency front-end processing unit 1; Carry out filtering, amplification, down-conversion, analog-to-digital conversion process synchronously; Get into denoising, the estimation of independent source number, the cluster of signal and the separation of signal that digital signal processor 3 is realized signal through input buffer 2 then.Signal Separation will be input in the output buffer 4 after accomplishing.Then output buffer 4 can enter data into on-site programmable gate array FPGA unit 5 and signal output unit 6 respectively.Through on-site programmable gate array FPGA unit 5 control of video output units 7, the scatter diagram after the signal cluster is presented in the LCD LCDs 8.
Radio-frequency front-end processing unit 1 mainly is to change the mixed signal that receives into baseband signal, for the blind signal separation algorithm process of follow-up digital processing unit 3 is provided convenience.Digital signal processor 3 is to carry out the separation of mixed signal according to the characteristic of mixed signal different modulating mode.The outer data storage 9a of first, second sheet, 9b deposit the positional information of scatter diagram after intermediate data and the Signal Separation in the blind separation algorithm processing procedure that digital signal processor 3 sends.Sequential and control unit 12 are for digital signal processor 3 and other ancillary equipment provide clock and control signal, in order to make each unit collaborative work.On-site programmable gate array FPGA unit 5 main tasks are control of video output units 7.Video output unit 7 mainly is the decoding to vision signal.Power subsystem provides system required various power supply signals.The effect of jtag interface 11 is that the program of depositing in the FLASH memory 10 is carried out emulation and debugging.
Claims (8)
1. blind separation device based on the BPSK/QPSK/8QAM modulation signal; It comprises the radio-frequency front-end processing unit 1 of gathering the mixed communication signal, digital signal processor 3, sequential and control unit 12, first outer data storage 9a, second outer data storage 9b, FLASH memory 10, output buffer 4, on-site programmable gate array FPGA unit 5, video output unit 7, LCD LCDs 8, signal output unit 6, jtag interface 11, input buffer 2; It is characterized in that the output of the radio-frequency front-end processing unit 1 of above-mentioned collection mixed communication signal links to each other with digital signal processor 3 through input buffer 2; The output of digital signal processor 3 links to each other with signal output unit 6 with on-site programmable gate array FPGA unit 5 respectively through output buffer 4, and the output of on-site programmable gate array FPGA unit 5 links to each other with video output unit 7; Video output unit 7 outputs link to each other with LCD liquid crystal display 8, digital signal processor 3 respectively with first outer data storage 9a, second jtag interface 11 that outer data storage 9b, FLASH memory 10 and device modulates are used; Sequential and control unit 12 are connected with radio-frequency front-end processing unit 1, input buffer 2, first outer data storage 9a, second outer data storage 9b, FLASH memory 10, output buffer 4, on-site programmable gate array FPGA unit 5, video output unit 7 and digital signal processor 3 respectively.
2. a kind of blind separation device according to claim 1 based on the BPSK/QPSK/8QAM modulation signal; It is characterized in that above-mentioned radio-frequency front-end processing unit 1 comprises that two antennas 101, band pass filter 102,103, two antennas 101 of radio frequency chip are connected with band pass filter 102; Band pass filter 102 is connected with chip 103; This radio-frequency front-end processing unit 1 is used to receive the filtering of signal, and mixing is amplified; Generate baseband signal after the analog-to-digital conversion, baseband signal from input buffer 2 through IO oral instructions to digital signal processor 3.
3. a kind of blind separation device based on the BPSK/QPSK/8QAM modulation signal according to claim 1 is characterized in that, above-mentioned sequential and control unit 12 are the EPM3128ATC100 chip, are used to produce clock and control signal.
4. a kind of blind separation device according to claim 1 based on the BPSK/QPSK/8QAM modulation signal; It is characterized in that; Above-mentioned digital signal processor 3 is the processor of chip model TMS320DM642, and this digital signal processor 3 is used to receive from sequential and control unit 12 clock that produces and the baseband signal of controlling radio-frequency front-end processing unit 1
,The baseband signal of the baseband signal of the baseband signal of the baseband signal of first outer data storage 9a, second outer data storage 9b, on-site programmable gate array FPGA unit 5, FLASH memory 10 is carried out denoising and with cluster mixed signal is carried out separating of signal.
5. a kind of blind separation device according to claim 1 based on the BPSK/QPSK/8QAM modulation signal; It is characterized in that; Above-mentioned first outer data storage 9a, second outer data storage 9b are respectively MT48LC4M32B2 type memory; Two MT48LC4M32B2 type memories are that TMS320DM642 processor 3 links to each other with the chip model respectively, and first outer data storage 9a, second outer data storage 9b are used to deposit the data that the baseband signal that receives and digital signal processor 3 blind separating treatment obtain.
6. a kind of blind separation device based on the BPSK/QPSK/8QAM modulation signal according to claim 1 is characterized in that, above-mentioned FLASH memory 10 is an AM29LV400 type memory, and this FLASH memory 10 is used to deposit the blind signal separation algorithm routine.
7. a kind of blind separation device according to claim 1 based on the BPSK/QPSK/8QAM modulation signal; It is characterized in that; Above-mentioned on-site programmable gate array FPGA unit 5 is connected with video output unit 7, and on-site programmable gate array FPGA unit 5 is used for the demonstration of control of video and strengthens the definition of video image.
8. a kind of blind separation device according to claim 1 based on the BPSK/QPSK/8QAM modulation signal; It is characterized in that; Video output unit 7 in above-mentioned is the Video Decoder of SAA7105H type; Video output unit 7 links to each other with on-site programmable gate array FPGA unit 5, and video output unit 7 links to each other with peripheral video equipment, LCD LCDs 8.
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| CN1648995A (en) * | 2004-10-12 | 2005-08-03 | 上海大学 | Voice enhancing device based on blind signal separation |
| CN101009950A (en) * | 2006-12-30 | 2007-08-01 | 华南理工大学 | A continuous-processing blind separation device for the mixed audio |
| CN101237565A (en) * | 2007-09-28 | 2008-08-06 | 东南大学 | Built-in driveway deviation alarming system |
| CN101388733A (en) * | 2008-10-22 | 2009-03-18 | 华南理工大学 | Blind separation interference resistant base band processing device for communication system |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1648995A (en) * | 2004-10-12 | 2005-08-03 | 上海大学 | Voice enhancing device based on blind signal separation |
| CN101009950A (en) * | 2006-12-30 | 2007-08-01 | 华南理工大学 | A continuous-processing blind separation device for the mixed audio |
| CN101237565A (en) * | 2007-09-28 | 2008-08-06 | 东南大学 | Built-in driveway deviation alarming system |
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Application publication date: 20120404 |