CN102403352A - MOS (metal oxide semiconductor) transistor - Google Patents

MOS (metal oxide semiconductor) transistor Download PDF

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Publication number
CN102403352A
CN102403352A CN2010102800696A CN201010280069A CN102403352A CN 102403352 A CN102403352 A CN 102403352A CN 2010102800696 A CN2010102800696 A CN 2010102800696A CN 201010280069 A CN201010280069 A CN 201010280069A CN 102403352 A CN102403352 A CN 102403352A
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mos transistor
contact hole
type
metal
semiconductor
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王根毅
吴宗宪
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CSMC Technologies Fab1 Co Ltd
CSMC Technologies Fab2 Co Ltd
Wuxi CSMC Semiconductor Co Ltd
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Wuxi CSMC Semiconductor Co Ltd
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Priority to CN2010102800696A priority Critical patent/CN102403352A/en
Priority to PCT/CN2011/070949 priority patent/WO2012034371A1/en
Publication of CN102403352A publication Critical patent/CN102403352A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66727—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the source electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode

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  • Microelectronics & Electronic Packaging (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

The invention provides an MOS (metal oxide semiconductor) transistor, which is a trench vertical double-diffusion transistor. A metallic layer for leading a source electrode out is filled in a contact hole positioned between two adjacent source regions by means of a metallic plug, and a body contact area in heavy doping is formed below the contact hole. All metals in an MOS transistor structure pass through the metal plug filled in the contact hole to contact with a silicon body, the silicon body contacted by the side walls of the contact hole is a first semiconductor type doped source region, the silicon body contacted by the bottom of the contact hole is the second semiconductor type doped body contact area, and both the areas are heavy doped areas, so that various parasitic effects generated caused by contact of the metals with a light doped silicon body are prevented effectively, and the performance of the MOS transistor is improved. Simultaneously, by the aid of the metallic plug, the bore diameter of the contact hole is greatly reduced, the dimensions of devices are further decreased, and the integration level of the devices is improved.

Description

A kind of MOS transistor
Technical field
The present invention relates to transistor arrangement, be specifically related to a kind of groove-shaped vertical double-diffused transistor structure, belong to technical field of semiconductors.
Background technology
In semiconductor integrated circuit, be the circuit on basis with the bilateral diffusion MOS transistor, be called for short DMOS, utilize the sideways diffusion speed difference of two kinds of foreign atoms, form self aligned sub-micron raceway groove, can reach very high operating frequency and speed.
Compare with common MOS transistor, DMOS structurally has two main distinctions: the one, P type, N type impurity are spread through same oxidation layer window in order, and form very short raceway groove; The 2nd, between raceway groove and drain region, add a lightly doped N-drift region, its doping content is much smaller than channel region.Most of added drain voltage is born in this district, thereby short-channel effect is weakened, and improves drain breakdown voltage, the series of advantages that obtains thereby the realization short channel combines with high-breakdown-voltage.
The DMOS transistor can be divided into two kinds of lateral DMOS transistor (LDMOS) and vertical DMOS transistors (VDMOS) again.Wherein, vertical DMOS transistor is because its good performance and high integration obtain increasing application in the semiconductor integrated circuit field.
Shown in Figure 1 is traditional TDM OS transistor arrangement.
As shown in Figure 1; Traditional TDM OS transistor 100 comprises: a N+ Semiconductor substrate 101 and be positioned at its surperficial N-epitaxial loayer 102 and P type well region 103 successively; Polysilicon gate 130 is positioned at the groove that extends to epitaxial loayer 102; 111 in the source region that itself and N-epitaxial loayer 102, P type well region 103 and N+ mix has gate oxide 131 to separate; The drain electrode of this TDMOS transistor 100 is drawn by the drain metal layer 120 that N+ Semiconductor substrate 101 bottom surfaces cover, and its source electrode is drawn by the source metal 110 on 111 surfaces, source region that cover the N+ doping.Known that by shown in Figure 1 in this structure, source metal 110 is positioned at P type well region 103 surfaces, its part that contacts with the silicon tagma is lightly doped P type well region 103, and metal-semiconductor contact here is prone to cause various ghost effects, influences transistor performance.
Summary of the invention
The technical problem that the present invention will solve is, a kind of MOS transistor is provided, and improves the Metal Contact in the existing structure, prevents the generation of various ghost effects, further improves device performance.
For solving the problems of the technologies described above, MOS transistor provided by the invention comprises:
The Semiconductor substrate of first semiconductor type (201);
Be positioned at the epitaxial loayer (202) of first semiconductor type doping on Semiconductor substrate (201) surface;
Be positioned at well region (203) epitaxial loayer (202), that second semiconductor type mixes;
Some first grooves (210) that are positioned at well region (203), its gash depth extends in the epitaxial loayer (202) greater than well region (203) degree of depth, and this first groove (210) liner gate oxide (212) and fill polysilicon and form polysilicon gate (211);
And:
Some contact holes (220) that are positioned between adjacent two first grooves (210) of well region (203), its liner adhesive layer (232) also is filled with first metal (233) formation metal plug;
The body contact zone (204) that some second semiconductor types that are positioned at contact hole (220) below mix;
The source region (231) that some first semiconductor types that are positioned between well region (203) first grooves (210) and the contact hole (220) mix.
Further, the source region (231) that the Semiconductor substrate (201) and first semiconductor type mix is heavy doping, and source region (231) doping content is less than the doping content of Semiconductor substrate (201); Epitaxial loayer (202) is a light dope, and the doping content of epitaxial loayer (202) is less than the doping content of Semiconductor substrate (201) and source region (231).
Further, body contact zone (204) are heavy doping, and well region (203) is a light dope, that is: the doping content of body contact zone (204) is greater than the doping content of well region (203).
Further, contact hole (220) aperture is 0.2 μ m～0.5 μ m, and hole depth is 0.35 μ m～1 μ m, and the hole depth of this contact hole (220) is injected the degree of depth greater than the ion of source region (231) and much smaller than the gash depth of first groove (210).
Selectable, the adhesive layer (232) of contact hole (220) liner is the Ti/TiN lamination.
Selectable, first metal (233) of filling in the contact hole (220) is tungsten (W).
Further, the gate oxide (212) of first groove (210) liner extends out to and covers surface, source region (231).
Further, polysilicon gate (211) surface coverage has oxide layer (214).
Further, cover the gate oxide (212) on surface, source region (231) and oxide layer (214) surface on covering polysilicon gate (211) surface and all be coated with an insulating medium layer (213), this insulating medium layer (213) surface is fair with the first metal layer (233) surface.
Optional, the insulating medium layer (213) of gate oxide (212) and oxide layer (214) surface coverage is boron-phosphorosilicate glass (BPSG).
Further, insulating medium layer (213) and the first metal layer (233) surface coverage have second metal level (230).
Further, second metal level (230) is a laminated construction, comprising: adhesive layer (232) and the 3rd metal level (234).
Optional, adhesive layer (232) is the Ti/TiN lamination, the 3rd metal level (234) is the AlSiCu alloy.
As optimum implementation, first semiconductor type is doped to the N type and mixes, and second semiconductor type is doped to the P type and mixes.
As another embodiment, first semiconductor type is doped to the P type and mixes, and second semiconductor type is doped to the N type and mixes.
Technique effect of the present invention is; Adopt the mode of metal plug to be filled in the contact hole (220) that is positioned between adjacent two source regions (231) in order to draw the source metal layer of electrodes; In contact hole (220), form metal plug, and form a heavily doped body contact area (204), at this moment in contact hole (220) below; Metal all contacts with the silicon body with the first metal layer (233) (that is: metal plug) through the adhesive layer (232) of filling in the contact hole (220) in this mos transistor structure; The silicon body of contact hole (220) sidewall contact is the source region (231) that first semiconductor type mixes, and the silicon body of contact hole (220) bottom contact is the body contact zone (204) that second semiconductor type mixes, and the two is heavily doped region; That is: MOS transistor provided by the invention is actual is groove-shaped vertical double-diffused transistor (TDMOS) structure; Its source metal is heavily doped region with the zone that the silicon body contacts, and has prevented that effectively metal from contacting the various ghost effects that produce with the lightly-doped silicon body, improve transistor performance.Meanwhile, introduce metal plug and replace that traditional contact hole is metal filled to have dwindled the aperture of contact hole greatly to realize contacting of metal and source region, further reduce device size, raising device integrated level.
Description of drawings
Fig. 1 is existing vertical double-diffusion MOS transistor structure sketch map;
Fig. 2 is a mos transistor structure sketch map provided by the invention.
Embodiment
For making the object of the invention, technical scheme and advantage clearer, the present invention is made further detailed description below in conjunction with accompanying drawing.
Fig. 2 is a mos transistor structure sketch map provided by the invention.
As shown in Figure 2, this MOS transistor 200 is actual to be a groove-shaped vertical double-diffused transistor (TDMOS), and this TDMOS transistor 200 comprises:
The Semiconductor substrate 201 of first semiconductor type;
Be positioned at the epitaxial loayer 202 of first semiconductor type doping on Semiconductor substrate 201 surfaces;
Be positioned at well region 203 epitaxial loayer 202, that second semiconductor type mixes;
Some first grooves 210 that are positioned at well region 203, its gash depth extends in the epitaxial loayer 202 greater than well region 203 degree of depth, and this first groove, 210 liner gate oxides 212 and fill polysilicon and form polysilicon gate 211;
And:
Some in well region 203 contact hole 220 between adjacent two first grooves 210, its liner adhesive layer 232 also is filled with first metal 233 and forms metal plugs;
The body contact zone 204 that some second semiconductor types that are positioned at contact hole 220 belows mix, this body contact zone 204 is positioned at well region 203;
Some source regions 231 that first semiconductor type between first groove 210 and the contact hole 220 mixes in well region 203.
In TDMOS transistor 200 structures that this embodiment provides; Semiconductor substrate 201 is heavy doping with source region 231; And source region 231 doping contents are less than the doping content of Semiconductor substrate 201; Epitaxial loayer 202 is a light dope, and the doping content of epitaxial loayer is less than the doping content in Semiconductor substrate 201 and source region 231; Body contact zone 204 is heavy doping, and well region 203 is a light dope, that is: the doping content of body contact zone 204 is greater than the doping content of well region 203.
In TDMOS transistor 200 structures that this embodiment provides; Contact hole 220 apertures are 0.2 μ m～0.5 μ m; Hole depth is 0.35 μ m～1 μ m, the hole depth of this contact hole 220 greater than the ion in source region 231 inject the degree of depth, much smaller than the gash depth of first groove 210.
As most preferred embodiment; Contact hole 220 apertures are 0.4 μ m; Hole depth is 0.6 μ m; The adhesive layer 232 of contact hole 220 liners is the Ti/TiN lamination, in order to form Metal Contact at active area (i.e. the source region 231 of first semiconductor type doping), to serve as first metal 233 is limited in adhesive and diffusion impervious layer in the contact hole.
As most preferred embodiment, first metal 233 of filling in the contact hole 220 is tungsten (W), in contact hole 220, forms the tungsten connector that is:.
In TDMOS transistor 200 structures that this embodiment provides, the gate oxide 212 of first groove, 210 liners stretches out and covers 231 surfaces, source region, and polysilicon gate 211 upper surfaces are coated with oxide layer 214.
As another embodiment, source region 231 all is coated with skim oxide layer 214 with polysilicon gate 211 surfaces.
In TDMOS transistor 200 structures that this embodiment provides; Gate oxide 212 surfaces that cover 231 surfaces, source region all are coated with an insulating medium layer 213 with oxide layer 214 surfaces that cover polysilicon gate 211 upper surfaces, and insulating medium layer 213 surfaces maintain an equal level with the metal plug surface that the first metal layer 233 forms.
As most preferred embodiment, the insulating medium layer 213 of gate oxide 212 and oxide layer 214 surface coverage is boron-phosphorosilicate glass (BPSG).
In TDMOS transistor 200 structures that this embodiment provides, insulating medium layer 213 surfaces and the first metal layer (W) 233 surface coverage have second metal level 230.In this embodiment, second metal level 230 is a laminated construction, comprises adhesive layer 232 and the 3rd metal level 234.
As most preferred embodiment; Adhesive layer 232 is the Ti/TiN lamination, the metal plug of the first metal layer (W) 233 formation and the good bonding between next metal level (that is: the 3rd metal level 234) is provided, simultaneously; Because Ti/TiN has good filling capacity; And and binding ability is stronger between the silicon body, combines with insulating medium layer 213 closely can improve the stability of metal structure greatly; The 3rd metal level 234 is the AlSiCu alloy, as the source electrode metal layer, in order to connect external source electrode.
As optimum implementation; First semiconductor type is doped to the N type and mixes, and second semiconductor type is doped to the P type and mixes, that is: the Semiconductor substrate 201 that is adopted is N type substrate; The drain region of serving as TDMOS transistor 200; The epitaxial loayers 202 that are positioned at Semiconductor substrate 201 surface also are the N type, and its doping content is less than the doping content of Semiconductor substrate 201, and source dopant region 231 is a N type heavily doped region; This TDMOS transistor 200 is the NPN transistor of a vertical stratification, and its channel region is the P type lightly doped zone of 231 belows, source region to the N type epitaxial loayer 202 of N+ doping along groove 210 sidewalls.During 200 work of TDMOS transistor, its drain electrode is drawn by the metal level that is positioned at Semiconductor substrate 201 bottom surfaces, adds malleation V between grid 211 and the source region 231 GSDuring＞threshold voltage vt, P type raceway groove transoid becomes the N type to become inversion layer, and the structure between source region 231 and drain region (that is: Semiconductor substrate 201) is by N +-P-N +Become N +-N-N +, at V DSEffect under, the electronics in N type source region arrives the drain region through channel region, forms by the drain-source current of leakage current to the source.Obviously, V GSNumerical value big more, the electron density of surface is big more, relative channel resistance is more little, at same V DSEffect under, drain-source current is big more.Electron stream changes vertical direction into behind raceway groove, flowed out by Semiconductor substrate 201.
As another embodiment; First semiconductor type is doped to the P type and mixes, and second semiconductor type is doped to the N type and mixes, that is: the Semiconductor substrate 201 that is adopted is P type substrate; The drain region of serving as TDMOS transistor 200; The epitaxial loayers 202 that are positioned at Semiconductor substrate 201 surface also are the P type, and its doping content is less than the doping content of Semiconductor substrate 201, and source dopant region 231 is a P type heavily doped region; This TDMOS transistor 200 is the PNP transistor of a vertical stratification, and its channel region is the N type lightly doped zone of 231 belows, source region to the P type epitaxial loayer 202 of P+ doping along groove 210 sidewalls.During 200 work of TDMOS transistor, its drain electrode is drawn by the metal level that is positioned at Semiconductor substrate 201 bottom surfaces, adds negative pressure V between grid 211 and the source region 231 GS, when | V GS|＞threshold voltage | during Vt|, N type raceway groove transoid becomes the P type to become inversion layer, and the structure between source region 231 and drain region (that is: Semiconductor substrate 201) is by P +-N-P +Become P +-P-P +, under with respect to the effect of source electrode tip for negative drain-source voltage, the positive charge hole of source end arrives drain terminal through the P type raceway groove of conducting, forms from the source to the source-drain current that leaks, V GSNegative more (absolute value is big more), the conducting resistance of raceway groove is more little, and the numerical value of electric current is big more.
In TDMOS transistor 200 structures that this embodiment provides; Adopt the mode of metal plug to be filled in the contact hole 220 between adjacent two source regions 231 in order to draw the source metal layer of electrodes; In contact hole 220, fill the first metal layer (W) 233 and form metal plug (being the tungsten plug in the most preferred embodiment); And below contact hole 220, form a heavily doped body contact area 204; At this moment, metal all contacts with the silicon body through the metal plug (tungsten plug) of filling the first metal layer (W) 233 formation in the contact hole 220 in these TDMOS transistor 200 structures, and the silicon body of contact hole 220 sidewalls contact is the source region 231 that first semiconductor type mixes; The silicon body of contact hole 220 bottoms contact is the body contact zone 204 that second semiconductor type mixes; The two is heavily doped region, that is: in TDMOS transistor 200 structures that this embodiment provides, metal is heavily doped region with the zone that the silicon body contacts; Prevented that effectively metal from contacting the various ghost effects that produce with the lightly-doped silicon body, improve the TDMOS transistor performance.Meanwhile, the aperture of contact hole 220 has been dwindled in the introducing of metal plug greatly, further reduces device size, improves the device integrated level.
Under situation without departing from the spirit and scope of the present invention, can also constitute many very embodiment of big difference that have.Should be appreciated that except like enclosed claim limited, the invention is not restricted at the specific embodiment described in the specification.

Claims (15)

1. MOS transistor comprises:
The Semiconductor substrate of first semiconductor type;
The epitaxial loayer that first semiconductor type mixes is positioned at said semiconductor substrate surface;
The well region that second semiconductor type mixes is positioned at said epitaxial loayer;
Some first grooves, its liner thin gate oxide also is filled with polysilicon formation polysilicon gate;
It is characterized in that this groove-shaped vertical double-diffused transistor structure also comprises:
Some contact holes, between adjacent two said first grooves, its liner adhesive layer also is filled with first metal formation metal plug in said well region;
The body contact area that some second semiconductor types mix is positioned at said contact hole below;
The source region that some first semiconductor types mix is in said well region between first groove and the contact hole.
2. MOS transistor according to claim 1; It is characterized in that; Said aperture of contact hole is 0.2 μ m～0.5 μ m, and hole depth is 0.35 μ m～1 μ m, the hole depth of said contact hole greater than the ion in said source region inject the degree of depth, much smaller than the gash depth of said first groove.
3. MOS transistor according to claim 1 is characterized in that, said body contact zone doping content is greater than the doping content of said well region.
4. MOS transistor according to claim 1 is characterized in that, said adhesive layer is the Ti/TiN lamination.
5. MOS transistor according to claim 1 is characterized in that, said first metal is a tungsten.
6. MOS transistor according to claim 1 is characterized in that, the gate oxide of the said first groove liner extends out to and covers surface, said source region.
7. MOS transistor according to claim 6 is characterized in that, said polysilicon gate upper surface is coated with oxide layer.
8. MOS transistor according to claim 7 is characterized in that, the oxide layer surface that covers the polycrystalline silicon gate surface on surface, said source region and cover said polycrystalline silicon gate surface all covers an insulating medium layer.
9. MOS transistor according to claim 8 is characterized in that, said dielectric laminar surface and said the first metal layer surface maintain an equal level.
10. MOS transistor according to claim 8 is characterized in that, said insulating medium layer is the boron-phosphorosilicate glass layer.
11. MOS transistor according to claim 9 is characterized in that, said insulating medium layer and said the first metal layer surface coverage second metal level.
12. MOS transistor according to claim 11 is characterized in that, said second metal level is a laminated construction, comprises said adhesive layer and the 3rd metal level.
13. MOS transistor according to claim 12 is characterized in that, said the 3rd metal level is the AlSiCu alloy.
14., it is characterized in that said first semiconductor type is doped to the N type and mixes according to any described MOS transistor in the claim 1～13, second semiconductor type is doped to the P type and mixes.
15., it is characterized in that said first semiconductor type is doped to the P type and mixes according to any described MOS transistor in the claim 1～13, second semiconductor type is doped to the N type and mixes.
CN2010102800696A 2010-09-14 2010-09-14 MOS (metal oxide semiconductor) transistor Pending CN102403352A (en)

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PCT/CN2011/070949 WO2012034371A1 (en) 2010-09-14 2011-02-12 Mos transistor

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CN104241268A (en) * 2013-06-21 2014-12-24 竹懋科技股份有限公司 Trench-vertical DMOS transistor structure and method for fabricating the same
CN107785365A (en) * 2016-08-31 2018-03-09 无锡华润上华科技有限公司 It is integrated with the device and its manufacture method of junction field effect transistor
CN113130660A (en) * 2021-03-26 2021-07-16 先之科半导体科技(东莞)有限公司 Vertically arranged MOSFET (Metal-oxide-semiconductor field Effect transistor)
CN113224164A (en) * 2021-04-21 2021-08-06 电子科技大学 Super junction MOS device

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