CN102403295A - Semiconductor packaging through metallic bonding and method for same - Google Patents

Semiconductor packaging through metallic bonding and method for same Download PDF

Info

Publication number
CN102403295A
CN102403295A CN2010102821989A CN201010282198A CN102403295A CN 102403295 A CN102403295 A CN 102403295A CN 2010102821989 A CN2010102821989 A CN 2010102821989A CN 201010282198 A CN201010282198 A CN 201010282198A CN 102403295 A CN102403295 A CN 102403295A
Authority
CN
China
Prior art keywords
chip
pin
base
installation area
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN2010102821989A
Other languages
Chinese (zh)
Other versions
CN102403295B (en
Inventor
薛彦迅
安荷·叭剌
鲁军
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Chongqing Wanguo Semiconductor Technology Co ltd
Alpha and Omega Semiconductor Ltd
Original Assignee
Alpha and Omega Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alpha and Omega Semiconductor Inc filed Critical Alpha and Omega Semiconductor Inc
Priority to CN201010282198.9A priority Critical patent/CN102403295B/en
Publication of CN102403295A publication Critical patent/CN102403295A/en
Application granted granted Critical
Publication of CN102403295B publication Critical patent/CN102403295B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/37099—Material
    • H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/4005—Shape
    • H01L2224/4009—Loop shape
    • H01L2224/40095—Kinked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73221—Strap and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/8438—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/84385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848—Bonding techniques
    • H01L2224/84801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Packaging Frangible Articles (AREA)

Abstract

The invention discloses a method for semiconductor packaging through metallic bonding, which is characterized in that the method includes the steps of firstly, providing a lead frame which comprises a chip substrate and pins, wherein the upper surface of the chip substrate is provided with at least one substrate groove which divides the whole chip substrate into a plurality of chip mounting areas, secondly, providing a plurality of chips which are all mounted in the corresponding chip mounting areas of the chip substrate through bonding, thirdly, providing at least one metallic sheet for connecting the chips, fourthly, providing leads for connecting the chips with the pins, fifthly, providing a plastic package body for packaging the structure, and sixthly, cutting off bottoms of the substrate grooves after packaging, so that the chip mounting areas in mutual connection are divided into disconnected chip mounting areas. The packaging method is capable of effectively preventing contamination caused by bonding overflowing during mounting of the chips to chip mounting equipment, the utilization ratio of the chips inside the package body is increased, and packaging cost is reduced.

Description

The semiconductor packages of metal keyed jointing and method thereof
Technical field
The present invention relates to a kind of semiconductor packages and method thereof, relate in particular to a kind of semiconductor packages and method thereof of metal keyed jointing.
Background technology
Encapsulation is most important for chip, and it not only plays protection chip and increased thermal conductivity ability, but also is the bridge of linking up the chip internal world and external circuit.The continuous expansion of chip manufacturing scale at present, and the terminal electronic application market of huge and quick growth have promoted the growth of whole semiconductor packages industry greatly.For satisfying the demand that product is light, thin, short, little and system tentatively integrates, the encapsulating structure of each pattern is weeded out the old and bring forth the new.Wherein can meet the compact wafer-level packaging that requires with high density comes into one's own gradually.
As shown in Figure 1, existing encapsulation comprises pin 1, chip base 2, binding 3, chip 4, lead-in wire 5 and plastic-sealed body 6.Wherein, in the incipient stage of Chip Packaging, chip base 2 is what break off with pin 1, leaves the space between chip base 2 and the pin 1.In the encapsulation process of chip, chip base 2 and pin 1 are placed on the chip mounting apparatus, then binding 3 is coated on the chip base 2, then chip 4 is arranged on the binding 3.This moment has been because the squeezing action of 4 pairs of bindings 3 of chip has been aggravated binding 3 overflowing around chip base 2, and binding 3 even can from the space between chip base 3 and the pin 1, flow on the chip mounting apparatus causes the pollution of chip mounting apparatus.
In the prior art; The incipient stage of Chip Packaging between chip base and pin, breaking off, also is off-state between chip base and the chip base; Also there is the gap between chip base and the chip base; As shown in Figure 2, be the schematic cross-section of the semiconductor packages of metal keyed jointing in the prior art, this structure comprises pin 1 ', chip base 2 ', binding 3 ', chip 4 ' and brace 5 '.Shown in the first row figure of Fig. 2, leave space d1 between chip base 2 ' and the chip base 2 ', also leave space d2 between chip base 2 ' and the pin 1 '.Shown in the second row figure of Fig. 2,, chip 4 ' following binding 3 ' is overflowed to the edge of chip base 2 ' when when onesize chip base 2 ' is gone up the area that increases chip 4 '.Shown in the third line figure of Fig. 2, binding 3 ' even can flow in the space and the space between chip base 2 ' and the pin 1 ' between chip base 2 ' and the chip base 2 ', to the pollution of chip mounting apparatus.Thereby in the technology of reality is made; For fear of the pollution that chip mounting apparatus is caused of overflowing of above-mentioned binding,, stipulated the mounting distance requirement based on different bindings; Promptly under the prerequisite of having stipulated package dimension; Reduce area of chip, perhaps stipulated under the prerequisite of chip area, increase package dimension.And this measure greatly reduces the utilance of chip in the semiconductor package body.
Summary of the invention
The method for packing that the purpose of this invention is to provide a kind of sheet metal keyed jointing; Binding overflowed the pollution to chip mounting apparatus that is caused when this method for packing can prevent effectively that chip from installing; And increased the utilance of chip in the packaging body greatly; Reduced packaging cost, and this method for packing is simple, easy to operate.
In order to achieve the above object, the semiconductor packages of a kind of metal keyed jointing that the present invention proposes comprises:
One lead frame, said lead frame comprises chip base and pin, and said chip base upper surface is provided with at least one base recess, and said base recess is divided into a plurality of chip installation areas territory with the entire chip basal seat area, and said pin is arranged near the chip base;
A plurality of chips, said a plurality of chips are arranged on each chip installation area territory of chip base through the binding correspondence, and said chip comprises a plurality of top electrodes;
At least one sheet metal is used for the connection between the chip;
One plastic-sealed body, the said chip base of plastic packaging, pin, chip and sheet metal.
The semiconductor packages of above-mentioned a kind of metal keyed jointing, the base recess bottom is broken off a plurality of chip installation areas territory on the chip base is divided into discrete chip installation area territory, and bottom portion of groove breaks off width less than recess width.
The semiconductor packages of above-mentioned a kind of metal keyed jointing; Said a plurality of chip comprises first chip and second chip; Said a plurality of chip installation areas territory comprises the first chip installation area territory and the second chip installation area territory; Said first chip is arranged on the first chip installation area territory, and said second chip is arranged on the second chip installation area territory, and said second chip comprises bottom electrode and is electrically connected to the second chip installation area territory.
The semiconductor packages of above-mentioned a kind of metal keyed jointing, an end of said sheet metal is electrically connected the top electrodes of first chip, and its other end is arranged on the interior position near the second chip installation area territory of base recess.
The semiconductor packages of above-mentioned a kind of metal keyed jointing, said base recess bottom is broken off the said first chip installation area territory and the second chip installation area territory is divided into discrete chip installation area territory, and bottom portion of groove breaks off width less than recess width.
The semiconductor packages of above-mentioned a kind of metal keyed jointing, said binding spills into the bottom corner near the base recess in the first chip installation area territory from the first chip installation area territory.
The semiconductor packages of above-mentioned a kind of metal keyed jointing, said binding are the conductive adhesion thing.
The present invention provides the semiconductor packages of other a kind of metal keyed jointing, comprising:
One lead frame; Said lead frame comprises chip base and pin; Said pin is arranged near the chip base, and is provided with groove between pedestal and pin between said pin and the said chip base, and bottom portion of groove breaks off chip base and pin are divided into discrete chip base and pin between said pedestal and pin; Bottom portion of groove breaks off width less than recess width, and said chip base is provided with the chip installation area territory;
One is arranged on the chip on the chip installation area territory through adhesive, and said chip comprises several top electrodes;
One metal connects top electrodes and the pin that is used to connect chip;
One plastic-sealed body connects in order to plastic packaging chip base, pin, chip and metal.
The semiconductor packages of above-mentioned a kind of metal keyed jointing; Said metal connects and comprises a sheet metal; One end of said sheet metal connects the top electrodes of chip, and the other end is arranged on the interior position near pin of groove between said pedestal and pin, is used for the top electrodes of chip and being connected of pin.
The semiconductor packages of above-mentioned a kind of metal keyed jointing, said adhesive spill into the bottom corner near groove between the pedestal in chip installation area territory and pin from the chip installation area territory.
The present invention also provides a kind of semiconductor packages of metal keyed jointing, comprising:
One lead frame; Said lead frame comprises chip base and pin; Said chip base is provided with at least one base recess, and said base recess is divided into a plurality of chip installation areas territory with chip base, and the base recess bottom is broken off a plurality of chip installation areas territory on the chip base is divided into discrete chip installation area territory; Said pin be arranged on chip base near; And be provided with groove between pedestal and pin between said pin and the said chip base, bottom portion of groove breaks off pedestal and pin is divided into discrete chip base and pin between said pedestal and pin, and bottom portion of groove breaks off width less than recess width;
A plurality of chips, said chip is arranged on its corresponding chip installation area territory through adhesive;
A plurality of metals connect being connected between the connection that is used between the chip and chip and the pin;
One plastic-sealed body connects in order to plastic packaging chip base, pin, chip and metal.
The semiconductor packages of above-mentioned a kind of metal keyed jointing, said adhesive spill into the bottom corner near groove between the pedestal in chip base district and pin from the chip base district.
The semiconductor packages of above-mentioned a kind of metal keyed jointing, said metal connect and comprise that a sheet metal, described sheet metal one end are arranged on the interior position near pin of groove between said pedestal and pin, are used for the top electrodes of chip and being connected of pin.
The method for packaging semiconductor of a kind of metal keyed jointing of the present invention may further comprise the steps:
Step 1 a: lead frame is provided; Said lead frame comprises chip base and pin; At said chip base upper surface at least one base recess is set, said base recess is divided into a plurality of chip installation areas territory with the entire chip basal seat area, said pin be arranged on chip base near;
Step 2: a plurality of chips are provided, through binding said a plurality of chips are installed in each chip installation area territory of corresponding chip base, said chip comprises a plurality of top electrodes;
Step 3: provide at least one metal to connect, be used to connect the top electrodes of chip;
Step 4: a plastic-sealed body is provided, and the said chip base of plastic packaging, pin, chip and metal connect;
Step 5: the base recess bottom is broken off, thereby interconnective chip installation area territory is divided into discrete each chip installation area territory, bottom portion of groove breaks off width less than recess width.
The method for packaging semiconductor of above-mentioned a kind of metal keyed jointing; In step 2; First chip is installed on the first chip installation area territory through first binding; Said first binding spills into the bottom corner near the base recess in the first chip installation area territory from the first chip installation area territory; Second chip is installed on the second chip installation area territory through second binding, second chip comprises that a bottom electrode is connected with the second chip installation area territory electricity, and said second binding spills into the bottom corner near the base recess in the second chip installation area territory from the second chip installation area territory.
The method for packaging semiconductor of above-mentioned a kind of metal keyed jointing; In step 3; Said provide at least one metal to connect to comprise first sheet metal is provided; The one of which end connects a top electrodes of first chip, and its other end is arranged on the interior position near second chip installation area of base recess, is connected with the bottom electrode electricity of second chip.
The method for packaging semiconductor of above-mentioned a kind of metal keyed jointing in step 1, is provided with groove between pedestal and pin between said pin and the said chip base.
The method for packaging semiconductor of above-mentioned a kind of metal keyed jointing in step 5, also comprises from the plastic-sealed body bottom bottom of groove between pedestal and pin is broken off, to cut apart chip base and pin.
The method for packaging semiconductor of above-mentioned a kind of metal keyed jointing, in step 3, a top electrodes that provides second sheet metal, one end to connect second chip, its other end are arranged between pedestal and pin that the position near pin is connected with pin electricity in the groove.
The method for packaging semiconductor of a kind of metal keyed jointing of the present invention may further comprise the steps:
Step 1 a: lead frame is provided; Said lead frame comprises chip base and pin; Said pin be arranged on chip base near; Said pin and said chip base link together, and are provided with groove between pedestal and pin between said pin and the said chip base, and said chip base is provided with the chip installation area territory;
Step 2: at least one chip is provided, through adhesive said chip is arranged on the chip installation area territory, said chip comprises several top electrodes;
Step 3: provide metal to connect to connect the top electrodes and the pin of chip;
Step 4 a: plastic-sealed body is provided, connects in order to plastic packaging chip base, pin, chip and metal;
Step 5: from the plastic-sealed body bottom bottom of groove between pedestal and pin is broken off, to cut apart chip base and pin.
The method for packaging semiconductor of above-mentioned a kind of metal keyed jointing in step 2, is installed said chip on chip base through binding, and said binding spills into the bottom corner near groove between the pedestal of chip base and pin from the pedestal.
The method for packaging semiconductor of above-mentioned a kind of metal keyed jointing; In step 3; Saidly provide metal to connect to comprise a top electrodes that provides first sheet metal, one end to connect first chip, its other end to be arranged between pedestal and pin in the groove, be connected with pin electricity near the position of pin.
The method for packaging semiconductor of above-mentioned a kind of metal keyed jointing, in step 1, said chip base is provided with at least one base recess, and said base recess is divided into a plurality of chip installation areas territory with chip base.
The method for packaging semiconductor of above-mentioned a kind of metal keyed jointing in step 5, also comprises from the plastic-sealed body bottom bottom of groove between pedestal and pin is broken off, to cut apart chip base and pin.
The method for packaging semiconductor of a kind of metal keyed jointing of the present invention may further comprise the steps:
Step 1 a: lead frame is provided; Said lead frame comprises chip base and pin, and said chip base is provided with at least one base recess, and said base recess is divided into a plurality of chip installation areas territory with chip base; Said pin be arranged on chip base around; Said pin and said chip base link together, and are provided with groove between pedestal and pin between said pin and the said chip base, and groove is in order to distinguish said pin and said chip base between said pedestal and pin;
Step 2: at least one chip is provided, and said chip is arranged on its corresponding chip installation area territory through adhesive, and said chip comprises bottom electrode and a plurality of top electrodes;
Step 3: a plurality of sheet metals are provided; Said sheet metal one end is connected with the chip top electrodes; Its other end is arranged in the base recess, is used for the connection between the chip, and said sheet metal one end is connected with the chip top electrodes; Its other end is arranged between pedestal and pin in the groove, is used for being connected between chip and the pin;
Step 4: lead-in wire is provided, and said lead-in wire connects the top electrodes and the pin of chip;
Step 5: a plastic-sealed body, in order to plastic packaging chip base, pin, a plurality of chip and sheet metal;
Step 6: cut off from the bottom of plastic-sealed body bottom,, cut off from the bottom of plastic-sealed body bottom, to cut apart chip base and pin with groove between pedestal and pin chip base is divided into discrete chip installation area territory with base recess.
The method for packing of sheet metal keyed jointing of the present invention makes it compared with prior art owing to adopt technique scheme, has the following advantages and good effect:
1, the method for packing of sheet metal keyed jointing of the present invention is owing to the incipient stage in Chip Packaging; Make between the chip base and chip base and pin between link together; There is not the space to be exposed on the chip mounting apparatus between the chip base and between chip base and the pin; Therefore when having avoided chip to install, binding overflow pollution to chip mounting apparatus.
2, the method for packing of sheet metal keyed jointing of the present invention is owing to be provided with groove between the chip base and the position that is connected between chip base and the pin, prevented excessive the overflowing of binding and piles up to pollute the surface of chip.
3, the method for packing of sheet metal keyed jointing of the present invention is simple to operation, and cost of manufacture is low.
Description of drawings
With reference to appended accompanying drawing, to describe embodiments of the invention more fully.Yet appended accompanying drawing only is used for explanation and sets forth, and does not constitute limitation of the scope of the invention.
Fig. 1 is the viewgraph of cross-section of existing semiconductor package.
Fig. 2 is for explaining the viewgraph of cross-section of the existing semiconductor package that binding overflows with three width of cloth figure.
Fig. 3 is the method for packaging semiconductor flow chart of the metal keyed jointing of embodiment one.
Fig. 4 is the vertical view and the viewgraph of cross-section of the lead frame that provided among the embodiment one.
Fig. 5 is arranged on vertical view and viewgraph of cross-section lead frame on chip through binding among the embodiment one.
Fig. 6 is with the vertical view and the viewgraph of cross-section of sheet metal keyed jointing chip electrode and pin among the embodiment one.
Fig. 7 is vertical view and a viewgraph of cross-section of using lead-in wire connection-core plate electrode and pin among the embodiment one.
Fig. 8 is with the vertical view and the viewgraph of cross-section of plastic-sealed body plastic packaging among the embodiment one.
Fig. 9 cuts the vertical view and the viewgraph of cross-section of base recess bottom surface in the plastic-sealed body bottom among the embodiment one.
Figure 10 is the method for packaging semiconductor flow chart of the metal keyed jointing of embodiment two.
Figure 11 is the vertical view and the viewgraph of cross-section of the lead frame that provides among the embodiment two.
Figure 12 is arranged on vertical view and viewgraph of cross-section on the lead frame among the embodiment two with chip.
Figure 13 is with the vertical view and the viewgraph of cross-section of sheet metal keyed jointing chip electrode and pin among the embodiment two.
Figure 14 is vertical view and a viewgraph of cross-section of using lead-in wire connection-core plate electrode and pin among the embodiment two.
Figure 15 is the vertical view and the viewgraph of cross-section of plastic-sealed body plastic packaging among the embodiment two.
Figure 16 is the vertical view and the viewgraph of cross-section of groove floor between pedestal and the pin of cutting plastic-sealed body bottom among the embodiment two.
Figure 17 is the viewgraph of cross-section of semiconductor package of the metal keyed jointing of embodiment three.
Embodiment
Embodiment one: the present invention provides a kind of method for packing of sheet metal keyed jointing; The encapsulating structure of this method for packing comprises lead frame 110, binding 120, chip 130,140, sheet metal 150, lead-in wire 160 and plastic-sealed body 170; The semiconductor packages flow chart of this sheet metal keyed jointing is as shown in Figure 3, and its concrete encapsulation process is following:
As shown in Figure 4, a lead frame 110 at first is provided, lead frame 110 comprises chip base 115 and a plurality of pin.A last width of cloth figure is the vertical view of lead frame among Fig. 4, and its next width of cloth figure is the sectional view along dotted line position in the last width of cloth figure.Chip base 115 comprises the first chip installation area territory 1151, the second chip installation area territory 1152 and base recess 1153, and base recess 1153 is arranged between the chip installation area territory, can distinguish each chip installation area territory.In the application of reality, a plurality of chip installation areas territory can be set on the chip base, and a plurality of base recess can be set distinguish.Present embodiment is only to be provided with two chip installation area territories and a base recess is an example on lead frame.As shown in Figure 4, a plurality of pins also comprise pin 111, pin 112, pin 113 and pin 114, and wherein pin 111 is connected with chip base 1151, and promptly pin 111 is connected with the chip bottom electrodes conduct; Pin 112,113 and 144 breaks off the both sides that a spacing is arranged on chip base 115 respectively, and these pins respectively should with the electrode pair of chip.
As shown in Figure 5, owing on the lead frame two chip installation area territories only are set in the present embodiment, therefore two chips are provided.It is example with high-end mos field effect transistor (HS MOSFET) and low side mos field effect transistor (LS MOSFET) respectively that two chips are respectively first chip 130 and second chip, 140, the first chips 130 and second chip 140.HS MOSFET and LS MOSFET comprise top source electrode, grid and bottom drain respectively.Through binding 120 first chip 130 and second chip 140 are separately positioned on the first chip installation area territory 1151 and the second chip installation area territory 1152, binding 120 plays the conduction bonding.Preferably, this binding 120 is a conductive silver paste.In concrete technological operation, at first conductive silver paste is coated on the chip installation area territory, then chip is arranged on the conductive silver paste.Generally, conductive silver paste can overflow on the chip installation area territory, and after especially chip was placed on the conductive silver paste, the gravity of chip can aggravate overflowing of conductive silver paste.In the present embodiment, as shown in Figure 5, conductive silver paste will slowly overflow and flow in the base recess 1153.From and the binding that overflow in a chip installation area territory 1151 is accumulated in the bottom corner of base recess near the first chip installation area territory, the binding that overflows from the second chip installation area territory 1152 is accumulated in the bottom corner of base recess near the second chip installation area territory.In the prior art; Owing to be what break off between the chip installation area territory; Conductive silver paste can overflow from the chip installation area territory and through the space between the installation region, and then pollutes the chip mounting apparatus that is arranged on below the lead frame, therefore when carrying out Chip Packaging; Consider the spacing at chip and edge, chip installation area territory, thereby limited the size of Chip Packaging.In the present embodiment; Base recess structure between the chip installation area territory has been collected the binding that overflows; Prevent that it from flowing into chip mounting apparatus; Chip edge generally gets final product greater than 3mils to the distance at edge, chip installation area territory, and traditional chip edge generally need be greater than 8～10mils to the distance at edge, chip installation area territory.Therefore the utilance of the interior chip of packaging body is significantly improved among the present invention.
As shown in Figure 6, after chip is arranged on the chip installation area territory, a sheet metal 150 is provided, an end 1501 of sheet metal 150 is arranged on the top source electrode of first chip 130, and its other end 1502 is arranged on base recess 153 interior positions near second chip 140.In existing encapsulation technology, because base recess is not set, an end 1502 and second chip 140 of sheet metal 150 are co-located on the second chip installation area territory 1152.For producing to overflow, piles up the binding of the binding of an end 1502 bottoms that prevent sheet metal 150 and second chip, 140 bottoms; Even cause the climbing of binding and influence the circuit performance of chip surface, have certain needs that distance is set between an end 1502 of sheet metal 150 and second chip 140.And in the present embodiment; One end 1502 of sheet metal 150 is arranged in the base recess 1153; Base recess 1153 has certain height; Add the thickness of second chip 140 itself, the binding of an end 1502 bottoms of sheet metal and second chip, 140 bottoms overflowing the possibility reduction that produces climbing to second chip, 140 surfaces and influence circuit performance.Therefore an end 1502 of sheet metal and the distance between second chip 140 can shorten, and the distance between first chip 1501 and second chip 1502 also can shorten.In the present embodiment; Chip edge can be fit to encapsulation to the distance of chip edge greater than 5mils; And in traditional encapsulation, chip edge needs to this shows greater than 20mils to the distance of chip edge; Groove structure in the present embodiment has improved the utilance of packaging body chips, has practiced thrift cost.Sheet metal 150 also can be substituted by lead-in wire or banded connecting line in addition.
Connection as shown in Figure 7, as to provide lead-in wire 160 to be used for chip electrode, first chip 130 is connected with pin 111 conductions; The top grid of first chip 130 is connected with pin 113 through lead-in wire 160; The top source electrode of second chip 140 is connected with pin 112 through lead-in wire 160; The top grid of second chip 140 is connected with pin 114 through lead-in wire 160.
As shown in Figure 8, after lead-in wire connects end, adopt 170 pairs of these encapsulating structures of plastic-sealed body to encapsulate.
As shown in Figure 9, after plastic packaging finishes, cut off the bottom of base recess 1153 from the bottom of plastic-sealed body 170, thereby cut apart the first chip installation area territory 1151 and the second chip installation area territory 1152, to accomplish the encapsulation of chip.Bottom portion of groove breaks off width should admit a terminal of sheet metal 150 to keep enough bottoms less than recess width.
In the present embodiment, first chip 130 and second chip 140 are respectively the MOSFET chip.First chip 130 and second chip 140 also can be respectively an integrated circuit control chip and a MOSFET chip, or the combination of other IC chip.Electrode can be established in the bottom of chip also can not establish electrode, can select different conductions or insulation binding for use according to different chips simultaneously.First chip can be selected first binding for use, and second chip can be selected second binding for use.First binding and second binding can be the same or different.
Embodiment two, the present invention provide a kind of method for packing of sheet metal keyed jointing; This encapsulating structure comprises lead frame 210, binding 220, chip 230, sheet metal 240, lead-in wire 250 and plastic-sealed body 260; Method for packaging semiconductor flow chart of the present invention is shown in figure 10, and its concrete encapsulation step is following:
Shown in figure 11, a lead frame 210 is provided, lead frame 210 comprises pin and chip base 211.Pin comprises the pin 212, pin 213 on two groups of chip base 211 both sides that link together with chip base 211 and be separately positioned on and breaks off the pin 214 that is provided with chip base 211.As shown in Figure 1, also be provided with groove 215 between a pedestal and pin between chip base 211 and the pin 213, groove 215 is with making a distinction between chip base 211 and the pin 213 between pedestal and pin.
Shown in figure 12; One chip 230 is provided; Chip 230 is arranged on the chip base 211 through binding 220, and the binding 220 that overflows can flow into groove 215 between pedestal and pin, and is accumulated between pedestal and pin groove near the bottom corner of pedestal; Thereby avoided connection to chip mounting apparatus, the edge of chip 230 also can be as much as possible near the edge of chip base 211.Can select different conductions or insulation binding for use according to different chips simultaneously.
Shown in figure 13; The top electrodes and the pin that connect chip with sheet metal 240; Chip is example with the power metal-oxide semiconductor, and this top electrodes is a source electrode, and an end 2401 of sheet metal 240 is arranged on the top source electrode of chip; The other end 2401 of sheet metal 240 is arranged on the interior position near pin of groove, is connected with the pin conduction.Sheet metal 240 also can be substituted by lead-in wire or banded connecting line in addition.
Shown in figure 14, with the top grid and the pin 214 of lead-in wire 250 connection chips 230.Shown in figure 15, then with plastic-sealed body 260 plastic packaging lead frames, chip, sheet metal and pin.After plastic packaging finishes, shown in figure 16, in plastic-sealed body bottom, cut off the base of groove 215 between pedestal and pin, thereby break off being connected between chip base 211 and the pin 213, to accomplish whole packaging technology.Bottom portion of groove breaks off width should be less than recess width, to keep enough bottoms to admit the terminal 2401 of sheet metal 240.In the present embodiment; Before the plastic packaging chip base and pin are linked together; And through groove differentiation between pedestal and pin; Groove protection chip mounting apparatus does not receive the pollution of binding between pedestal and pin, thereby allows to reduce the distance between chip base and the pin, has improved the utilance of encapsulation chips.In the present embodiment, chip 230 can be MOSFET chip or other any IC chip.Electrode can be established in the bottom of chip also can not establish electrode, can select different conductions or insulation binding for use according to different chips simultaneously.
Embodiment three, the foregoing description one are that encapsulating structure linked together each the chip installation area territory on the chip base before plastic packaging, distinguish with base recess, and plastic packaging cuts to accomplish whole encapsulation process base recess after finishing.Embodiment two is that encapsulating structure linked together chip base and pin before plastic packaging, distinguishes with groove between pedestal and pin, and plastic packaging cuts to accomplish whole encapsulation process groove between pedestal and pin after finishing.In concrete encapsulation process, can embodiment one and embodiment two be combined.Shown in figure 17; Replace lead-in wire connection-core plate electrode and pin with sheet metal; All link together between the chip base 311 in the lead frame 310 and between chip base 311 and the pin 312; And distinguish with groove between base recess 313, pedestal and pin 314 respectively, install and after the plastic-sealed body plastic packaging finishes, again groove between base recess 313, pedestal and pin 314 is cut off to accomplish whole encapsulation at chip.Bottom portion of groove breaks off width should be less than recess width.
In the chip installation process of this embodiment; Avoid causing the pollution of chip mounting apparatus equally by overflowing of binding; And improved the area of chip that can encapsulate in the packaging body to a greater extent, perhaps reduced the package dimension of chip to a greater extent, reduced packaging cost.
Certainly, must recognize that above-mentioned introduction is the explanation of the relevant preferred embodiment of the present invention, only otherwise depart from spirit and the scope that accompanying claims showed subsequently, the present invention also exists many modifications.
The present invention only is confined to above-mentioned explanation or details and method that accompanying drawing showed anything but.The present invention can have other embodiment, and can adopt multiple mode to implement.In addition, everybody must recognize that also employed wording and term and digest be the purpose in order to realize introducing just, only is confined to this anything but here.
Just because of this, one skilled in the art will appreciate that the present invention based on viewpoint can be used as several kinds of targets of embodiment of the present invention at any time and design other structure, method and system.So, it is essential that appended claim will be regarded as the construction that has comprised that all these are of equal value, as long as they are without departing from the spirit and scope of the present invention.

Claims (25)

1. the semiconductor packages of a metal keyed jointing is characterized in that, comprising:
One lead frame, said lead frame comprises chip base and pin, and said chip base upper surface is provided with at least one base recess, and said base recess is divided into a plurality of chip installation areas territory with the entire chip basal seat area, and said pin is arranged near the chip base;
A plurality of chips, said a plurality of chips are arranged on each chip installation area territory of chip base through the binding correspondence, and said chip comprises a plurality of top electrodes;
At least one sheet metal is used for the connection between the chip;
One plastic-sealed body, the said chip base of plastic packaging, pin, chip and sheet metal.
2. the semiconductor packages of a kind of metal keyed jointing as claimed in claim 1; It is characterized in that; The base recess bottom is broken off a plurality of chip installation areas territory on the chip base is divided into discrete chip installation area territory, and bottom portion of groove breaks off width less than recess width.
3. the semiconductor packages of a kind of metal keyed jointing as claimed in claim 1; It is characterized in that; Said a plurality of chip comprises first chip and second chip, and said a plurality of chip installation areas territory comprises the first chip installation area territory and the second chip installation area territory, and said first chip is arranged on the first chip installation area territory; Said second chip is arranged on the second chip installation area territory, and said second chip comprises bottom electrode and is electrically connected to the second chip installation area territory.
4. the semiconductor packages of a kind of metal keyed jointing as claimed in claim 3 is characterized in that, an end of said sheet metal is electrically connected the top electrodes of first chip, and its other end is arranged on the interior position near the second chip installation area territory of base recess.
5. the semiconductor packages of a kind of metal keyed jointing as claimed in claim 4; It is characterized in that; Said base recess bottom is broken off the said first chip installation area territory and the second chip installation area territory is divided into discrete chip installation area territory, and bottom portion of groove breaks off width less than recess width.
6. the semiconductor packages of a kind of metal keyed jointing as claimed in claim 3 is characterized in that, said binding spills into the bottom corner near the base recess in the first chip installation area territory from the first chip installation area territory.
7. the semiconductor packages of a kind of metal keyed jointing as claimed in claim 6 is characterized in that, said binding is the conductive adhesion thing.
8. the semiconductor packages of a metal keyed jointing is characterized in that, comprising:
One lead frame; Said lead frame comprises chip base and pin; Said pin is arranged near the chip base, and is provided with groove between pedestal and pin between said pin and the said chip base, and bottom portion of groove breaks off chip base and pin are divided into discrete chip base and pin between said pedestal and pin; Bottom portion of groove breaks off width less than recess width, and said chip base is provided with the chip installation area territory;
One is arranged on the chip on the chip installation area territory through adhesive, and said chip comprises several top electrodes;
One metal connects top electrodes and the pin that is used to connect chip;
One plastic-sealed body connects in order to plastic packaging chip base, pin, chip and metal.
9. the semiconductor packages of a kind of metal keyed jointing as claimed in claim 8; It is characterized in that; Said metal connects and comprises a sheet metal; One end of said sheet metal connects the top electrodes of chip, and the other end is arranged on the interior position near pin of groove between said pedestal and pin, is used for the top electrodes of chip and being connected of pin.
10. the semiconductor packages of a kind of metal keyed jointing as claimed in claim 8 is characterized in that, said adhesive spills into the bottom corner near groove between the pedestal in chip installation area territory and pin from the chip installation area territory.
11. the semiconductor packages of a metal keyed jointing is characterized in that, comprising:
One lead frame; Said lead frame comprises chip base and pin; Said chip base is provided with at least one base recess, and said base recess is divided into a plurality of chip installation areas territory with chip base, and the base recess bottom is broken off a plurality of chip installation areas territory on the chip base is divided into discrete chip installation area territory; Said pin be arranged on chip base near; And be provided with groove between pedestal and pin between said pin and the said chip base, bottom portion of groove breaks off pedestal and pin is divided into discrete chip base and pin between said pedestal and pin, and bottom portion of groove breaks off width less than recess width;
A plurality of chips, said chip is arranged on its corresponding chip installation area territory through adhesive;
A plurality of metals connect being connected between the connection that is used between the chip and chip and the pin;
One plastic-sealed body connects in order to plastic packaging chip base, pin, chip and metal.
12. the semiconductor packages of a kind of metal keyed jointing as claimed in claim 11 is characterized in that, said adhesive spills into the bottom corner near groove between the pedestal in chip base district and pin from the chip base district.
13. the semiconductor packages of a kind of metal keyed jointing as claimed in claim 11; It is characterized in that; Said metal connects and comprises that a sheet metal, described sheet metal one end are arranged on the interior position near pin of groove between said pedestal and pin, are used for the top electrodes of chip and being connected of pin.
14. the method for packaging semiconductor of a metal keyed jointing is characterized in that, may further comprise the steps:
Step 1 a: lead frame is provided; Said lead frame comprises chip base and pin; At said chip base upper surface at least one base recess is set, said base recess is divided into a plurality of chip installation areas territory with the entire chip basal seat area, said pin be arranged on chip base near;
Step 2: a plurality of chips are provided, through binding said a plurality of chips are installed in each chip installation area territory of corresponding chip base, said chip comprises a plurality of top electrodes;
Step 3: provide at least one metal to connect, be used to connect the top electrodes of chip;
Step 4: a plastic-sealed body is provided, and the said chip base of plastic packaging, pin, chip and metal connect;
Step 5: the base recess bottom is broken off, thereby interconnective chip installation area territory is divided into discrete each chip installation area territory, bottom portion of groove breaks off width less than recess width.
15. the method for packaging semiconductor of a kind of metal keyed jointing as claimed in claim 14; It is characterized in that; In step 2; First chip is installed on the first chip installation area territory through first binding, said first binding spills into the bottom corner near the base recess in the first chip installation area territory from the first chip installation area territory, second chip is installed on the second chip installation area territory through second binding; Second chip comprises that a bottom electrode is connected with the second chip installation area territory electricity, and said second binding spills into the bottom corner near the base recess in the second chip installation area territory from the second chip installation area territory.
16. the method for packaging semiconductor of a kind of metal keyed jointing as claimed in claim 15; It is characterized in that; In step 3, saidly provide at least one metal to connect to comprise a top electrodes that provides first sheet metal, one of which end to connect first chip; Its other end is arranged on the interior position near second chip installation area of base recess, is connected with the bottom electrode electricity of second chip.
17. the method for packaging semiconductor of a kind of metal keyed jointing as claimed in claim 16 is characterized in that, in step 1, is provided with groove between pedestal and pin between said pin and the said chip base.
18. the method for packaging semiconductor of a kind of metal keyed jointing as claimed in claim 17 is characterized in that, in step 5, also comprises from the plastic-sealed body bottom bottom of groove between pedestal and pin is broken off, to cut apart chip base and pin.
19. the method for packaging semiconductor of a kind of metal keyed jointing as claimed in claim 17; It is characterized in that; In step 3, a top electrodes that provides second sheet metal, one end to connect second chip, its other end are arranged between pedestal and pin that the position near pin is connected with pin electricity in the groove.
20. the method for packaging semiconductor of a metal keyed jointing is characterized in that, may further comprise the steps:
Step 1 a: lead frame is provided; Said lead frame comprises chip base and pin; Said pin be arranged on chip base near; Said pin and said chip base link together, and are provided with groove between pedestal and pin between said pin and the said chip base, and said chip base is provided with the chip installation area territory;
Step 2: at least one chip is provided, through adhesive said chip is arranged on the chip installation area territory, said chip comprises several top electrodes;
Step 3: provide metal to connect to connect the top electrodes and the pin of chip;
Step 4 a: plastic-sealed body is provided, connects in order to plastic packaging chip base, pin, chip and metal;
Step 5: from the plastic-sealed body bottom bottom of groove between pedestal and pin is broken off, to cut apart chip base and pin.
21. the method for packaging semiconductor of a kind of metal keyed jointing as claimed in claim 20; It is characterized in that; In step 2, said chip is installed on chip base through binding, said binding spills into the bottom corner near groove between the pedestal of chip base and pin from the pedestal.
22. the method for packaging semiconductor of a kind of metal keyed jointing as claimed in claim 20; It is characterized in that; In step 3; Saidly provide metal to connect to comprise a top electrodes that provides first sheet metal, one end to connect first chip, its other end to be arranged between pedestal and pin in the groove, be connected with pin electricity near the position of pin.
23. the method for packaging semiconductor of a kind of metal keyed jointing as claimed in claim 22 is characterized in that, in step 1, said chip base is provided with at least one base recess, and said base recess is divided into a plurality of chip installation areas territory with chip base.
24. the method for packaging semiconductor of a kind of metal keyed jointing as claimed in claim 23 is characterized in that, in step 5, also comprises from the plastic-sealed body bottom bottom of groove between pedestal and pin is broken off, to cut apart chip base and pin.
25. the method for packaging semiconductor of a metal keyed jointing is characterized in that, may further comprise the steps:
Step 1 a: lead frame is provided; Said lead frame comprises chip base and pin, and said chip base is provided with at least one base recess, and said base recess is divided into a plurality of chip installation areas territory with chip base; Said pin be arranged on chip base around; Said pin and said chip base link together, and are provided with groove between pedestal and pin between said pin and the said chip base, and groove is in order to distinguish said pin and said chip base between said pedestal and pin;
Step 2: at least one chip is provided, and said chip is arranged on its corresponding chip installation area territory through adhesive, and said chip comprises bottom electrode and a plurality of top electrodes;
Step 3: a plurality of sheet metals are provided; Said sheet metal one end is connected with the chip top electrodes; Its other end is arranged in the base recess, is used for the connection between the chip, and said sheet metal one end is connected with the chip top electrodes; Its other end is arranged between pedestal and pin in the groove, is used for being connected between chip and the pin;
Step 4: lead-in wire is provided, and said lead-in wire connects the top electrodes and the pin of chip;
Step 5: a plastic-sealed body, in order to plastic packaging chip base, pin, a plurality of chip and sheet metal;
Step 6: cut off from the bottom of plastic-sealed body bottom,, cut off from the bottom of plastic-sealed body bottom, to cut apart chip base and pin with groove between pedestal and pin chip base is divided into discrete chip installation area territory with base recess.
CN201010282198.9A 2010-09-07 2010-09-07 Semiconductor packaging through metallic bonding and method for same Active CN102403295B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201010282198.9A CN102403295B (en) 2010-09-07 2010-09-07 Semiconductor packaging through metallic bonding and method for same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201010282198.9A CN102403295B (en) 2010-09-07 2010-09-07 Semiconductor packaging through metallic bonding and method for same

Publications (2)

Publication Number Publication Date
CN102403295A true CN102403295A (en) 2012-04-04
CN102403295B CN102403295B (en) 2014-08-06

Family

ID=45885352

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201010282198.9A Active CN102403295B (en) 2010-09-07 2010-09-07 Semiconductor packaging through metallic bonding and method for same

Country Status (1)

Country Link
CN (1) CN102403295B (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103474410A (en) * 2013-09-11 2013-12-25 杰群电子科技（东莞）有限公司 Power semiconductor packaging piece and wire bonding method thereof
CN104465423A (en) * 2014-12-08 2015-03-25 杰群电子科技（东莞）有限公司 Double-lead-frame overlap design semiconductor device package method
CN104716117A (en) * 2013-12-17 2015-06-17 万国半导体股份有限公司 Multi-chip device and encapsulation method thereof
WO2017114411A1 (en) * 2015-12-31 2017-07-06 无锡华润安盛科技有限公司 Chip packaging method
CN111403296A (en) * 2020-03-30 2020-07-10 捷捷微电(上海)科技有限公司 Semiconductor packaging piece and manufacturing method thereof
CN112652600A (en) * 2019-10-10 2021-04-13 上海凯虹科技电子有限公司 Metal member for multi-chip laminated packaging structure, mounting method thereof and packaging body
CN113130455A (en) * 2021-04-20 2021-07-16 黄山学院 Multi-unit power integrated module with high thermal reliability and processing technology thereof

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6713849B2 (en) * 2000-12-28 2004-03-30 Hitachi, Ltd. Semiconductor utilizing grooves in lead and tab portions of lead frame to prevent peel off between the lead frame and the resin
US7235876B2 (en) * 2005-09-12 2007-06-26 Denso Corporation Semiconductor device having metallic plate with groove
US20070228534A1 (en) * 2006-03-28 2007-10-04 Tomoaki Uno Semiconductor device and manufacturing method of the same
US20070267726A1 (en) * 2006-05-19 2007-11-22 Noquil Jonathan A Dual side cooling integrated power device module and methods of manufacture
CN101697348A (en) * 2009-10-11 2010-04-21 天水华天科技股份有限公司 Small-carrier flat-four-side pin-less packaging part and preparation method thereof

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6713849B2 (en) * 2000-12-28 2004-03-30 Hitachi, Ltd. Semiconductor utilizing grooves in lead and tab portions of lead frame to prevent peel off between the lead frame and the resin
US7235876B2 (en) * 2005-09-12 2007-06-26 Denso Corporation Semiconductor device having metallic plate with groove
US20070228534A1 (en) * 2006-03-28 2007-10-04 Tomoaki Uno Semiconductor device and manufacturing method of the same
US20070267726A1 (en) * 2006-05-19 2007-11-22 Noquil Jonathan A Dual side cooling integrated power device module and methods of manufacture
CN101697348A (en) * 2009-10-11 2010-04-21 天水华天科技股份有限公司 Small-carrier flat-four-side pin-less packaging part and preparation method thereof

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103474410B (en) * 2013-09-11 2017-10-27 杰群电子科技（东莞）有限公司 A kind of power semiconductor package part and its wire soldering method
CN103474410A (en) * 2013-09-11 2013-12-25 杰群电子科技（东莞）有限公司 Power semiconductor packaging piece and wire bonding method thereof
CN104716117A (en) * 2013-12-17 2015-06-17 万国半导体股份有限公司 Multi-chip device and encapsulation method thereof
CN104716117B (en) * 2013-12-17 2017-10-24 万国半导体股份有限公司 Multichip device and its method for packing
CN104465423A (en) * 2014-12-08 2015-03-25 杰群电子科技（东莞）有限公司 Double-lead-frame overlap design semiconductor device package method
CN104465423B (en) * 2014-12-08 2017-08-22 杰群电子科技（东莞）有限公司 A kind of Double-lead-frame overlaps designing semiconductor device method for packing
WO2017114411A1 (en) * 2015-12-31 2017-07-06 无锡华润安盛科技有限公司 Chip packaging method
CN112652600A (en) * 2019-10-10 2021-04-13 上海凯虹科技电子有限公司 Metal member for multi-chip laminated packaging structure, mounting method thereof and packaging body
CN112652600B (en) * 2019-10-10 2023-03-17 上海凯虹科技电子有限公司 Metal member for multi-chip laminated packaging structure, mounting method thereof and packaging body
CN111403296A (en) * 2020-03-30 2020-07-10 捷捷微电(上海)科技有限公司 Semiconductor packaging piece and manufacturing method thereof
CN111403296B (en) * 2020-03-30 2022-03-25 捷捷微电(上海)科技有限公司 Semiconductor packaging piece and manufacturing method thereof
CN113130455A (en) * 2021-04-20 2021-07-16 黄山学院 Multi-unit power integrated module with high thermal reliability and processing technology thereof
CN113130455B (en) * 2021-04-20 2023-09-12 黄山学院 Multi-unit power integrated module with high thermal reliability and processing technology thereof

Also Published As

Publication number Publication date
CN102403295B (en) 2014-08-06

Similar Documents

Publication Publication Date Title
CN102403295B (en) Semiconductor packaging through metallic bonding and method for same
US8519525B2 (en) Semiconductor encapsulation and method thereof
CN102194806B (en) Stacked dual chip package and method of fabrication
CN102842666B (en) LED (Light Emitting Diode) flip chip structure and manufacturing method thereof
CN102132403B (en) Molded ultra thin semiconductor die packages, systems using same, and methods of making same
US20190259735A1 (en) QFN Surface-Mounted RGB LED Packaging Module and Preparing Method Thereof
CN103779235A (en) Fan-out wafer level package structure
CN103946976A (en) Two level leadframe with upset ball bonding surface and device package
CN102593108A (en) Power semiconductor packaging structure and manufacturing method thereof
CN105981170A (en) Dc-dc converter having terminals of semiconductor chips
CN103608917A (en) Ultra-thin power transistor and synchronous buck converter having customized footprint
CN102403296A (en) Semiconductor module and method for production thereof
EP3557615A1 (en) Integrated-type rgb-led display screen
CN102237343A (en) Semiconductor package realizing connection by connecting sheets and manufacturing method for semiconductor package
KR102047899B1 (en) Method for producing a substrate adapter, substrate adapter and method for contacting a semiconductor element
DE212018000073U1 (en) Semiconductor device
CN107636828A (en) Integrated fixture and lead and the method for making circuit
JP6534677B2 (en) Converter with partially thinned lead frame with stacked chips and interposer
CN202487568U (en) Semiconductor module
CN105118818A (en) Power module of square flat pin-free packaging structure
CN105489580B (en) Semiconductor substrate and semiconductor package
CN102222627B (en) Packaging method possessing wafer dimension plaster
TWI459528B (en) A method of package with clip bonding
CN104332465B (en) 3D packaging structure and technological method thereof
CN104795363A (en) Copper-clad substrate with barrier structure and manufacturing method thereof

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C41 Transfer of patent application or patent right or utility model
TR01 Transfer of patent right

Effective date of registration: 20160914

Address after: 400700 Chongqing city Beibei district and high tech Industrial Park the road No. 5 of 407

Patentee after: Chongqing Wanguo Semiconductor Technology Co.,Ltd.

Address before: Bermuda Hamilton Church 2 Cola Lunden House Street

Patentee before: ALPHA & OMEGA SEMICONDUCTOR, Ltd.

Effective date of registration: 20160914

Address after: Bermuda Hamilton Church 2 Cola Lunden House Street

Patentee after: ALPHA & OMEGA SEMICONDUCTOR, Ltd.

Address before: No. 475 California Sunnyvale, oak Mead Avenue

Patentee before: ALPHA & OMEGA SEMICONDUCTOR, Ltd.

PE01 Entry into force of the registration of the contract for pledge of patent right

Denomination of invention: Semiconductor packaging through metallic bonding and method for same

Effective date of registration: 20191210

Granted publication date: 20140806

Pledgee: Chongqing Branch of China Development Bank

Pledgor: Chongqing Wanguo Semiconductor Technology Co.,Ltd.

Registration number: Y2019500000007

PE01 Entry into force of the registration of the contract for pledge of patent right
PC01 Cancellation of the registration of the contract for pledge of patent right

Granted publication date: 20140806

Pledgee: Chongqing Branch of China Development Bank

Pledgor: Chongqing Wanguo Semiconductor Technology Co.,Ltd.

Registration number: Y2019500000007

PC01 Cancellation of the registration of the contract for pledge of patent right