CN102394638B

CN102394638B - Ternary adiabatic JKL flip-flop and adiabatic novenary asynchronous counter

Info

Publication number: CN102394638B
Application number: CN201110311268.3A
Authority: CN
Inventors: 汪鹏君; 梅凤娜
Original assignee: Ningbo University
Current assignee: Hangzhou Maen Science & Technology Co ltd
Priority date: 2011-10-14
Filing date: 2011-10-14
Publication date: 2014-07-16
Anticipated expiration: 2031-10-14
Also published as: CN102394638A

Abstract

The invention discloses a ternary adiabatic JKL flip-flop comprising a ternary adiabatic JKL fundamental circuit and a DTCTGAL buffer, wherein the signal input end of the ternary adiabatic JKL fundamental circuit is connected with the signal output end of the DTCTGAL buffer, the signal output end of the ternary adiabatic JKL fundamental circuit is connected with the signal input end of the DTCTGAL buffer; the complementary signal output end of the ternary adiabatic JKL fundamental circuit is connected with the complementary signal input end of the DTCTGAL buffer; both the ternary adiabatic JKL fundamental circuit and the DTCTGAL buffer are connected with a power clock signal of an amplitude level corresponding logic 1, a first clock pulse signal of an amplitude level corresponding logic 2 and a second clock pulse signal of the amplitude level corresponding logic 2; and the delay time of the DTCTGAL buffer is the same as that of the ternary adiabatic JKL fundamental circuit, and is half a clock period. The ternary adiabatic JKL flip-flop disclosed by the invention has the advantages that the circuit has very low power consumption, ternary input and output of the adiabatic circuit are realized while an energy recovery characteristic is provided, and the circuit has a higher information density and high operational reliability.

Description

A kind of tri-valued, thermal-insulating JKL trigger and adiabatic novenary asynchronous counter

Technical field

The present invention relates to a kind of JKL trigger, especially relate to a kind of tri-valued, thermal-insulating JKL trigger and adiabatic novenary asynchronous counter.

Background technology

Along with the develop rapidly of high information density integrated circuit, there is the trigger of memory function, energy storing digital information as a kind of sequential logical circuit, be the important component part that forms modern high performance digital integrated circuit.MULTI-VALUED LOGIC CIRCUIT has the feature of high information density, and for the line reducing between Circuits System, saving chip area, improves the tools such as circuit space and time availability and be of great significance, and in some application, has significant advantage than two-valued function circuit.Existing research at present launches for the low-power consumption of multiple value flip-flop, as adopt the Novel current type CMOS tetra-of current threshold control technology design to be worth edge triggered flip flop, effectively utilize clock edge to produce burst pulse and realize sampling evaluation, greatly reduce the DC power of circuit; Adopt three values of low-swing clock Technology design bilateral along the new D-flip flop of low-power consumption, utilize the saltus step of the responsive inhibition of the two edge transition of clock signal redundancy, reduce frequency and the amplitude of oscillation of clock signal, thereby reduce the system power dissipation of whole trigger.But due to the energy in above-mentioned these circuit be by power supply to signal node again to the disposable consumption of mode on ground, its power consumption is very huge, and adopts traditional cmos circuit to reduce the method for power consumption, the energy consumption of saving is very limited.

Adiabatic circuits adopts AC pulse power supply to carry out drive circuit, utilize the LC oscillation circuit in circuit, energy is transformed mutually with the form of electric energy and magnetic energy, break through the limitation of traditional circuit Conversion of Energy mode, effectively reclaim the energy that is stored in circuit node, reduce the irreversible energy loss causing because of dissipative cell resistance etc., realize energy recovery, thereby significantly reduce the power consumption of circuit.In view of this, utilize the low power design technique design multiple value flip-flop of adiabatic circuits to there is realistic meaning.

Summary of the invention

Technical problem to be solved by this invention is to provide and a kind ofly can effectively reduces power consumption ensureing to have under correct logic function prerequisite, improves tri-valued, thermal-insulating JKL trigger and the adiabatic novenary asynchronous counter of integrated circuit functional reliability.

The present invention solves the problems of the technologies described above adopted technical scheme: a kind of tri-valued, thermal-insulating JKL trigger, comprise tri-valued, thermal-insulating JKL basic circuit and DTCTGAL buffer, the signal input part of described tri-valued, thermal-insulating JKL basic circuit is connected with the signal output part of described DTCTGAL buffer, the signal output part of described tri-valued, thermal-insulating JKL basic circuit is connected with the signal input part of described DTCTGAL buffer, the complementary signal output of described tri-valued, thermal-insulating JKL basic circuit is connected with the complementary signal input of described DTCTGAL buffer, described tri-valued, thermal-insulating JKL basic circuit accesses respectively the first power clock signal of amplitude level counterlogic 1, the first clock pulse signal of amplitude level counterlogic 2 and the second clock pulse signal of amplitude level counterlogic 2, described DTCTGAL buffer accesses respectively the second power clock signal of amplitude level counterlogic 1, the first clock pulse signal of amplitude level counterlogic 2 and the second clock pulse signal of amplitude level counterlogic 2,180 ° of the phase phasic differences of the phase place of the first described power clock signal and described the second power clock signal, 180 ° of the phase phasic differences of the phase place of the first described clock pulse signal and described second clock pulse signal, the time of delay of described DTCTGAL buffer is identical with the time of delay of described tri-valued, thermal-insulating JKL basic circuit, be the clock cycle half.

Described tri-valued, thermal-insulating JKL basic circuit comprises signal sample circuit, complementary signal sample circuit, the one NMOS pipe group, the 2nd NMOS pipe group, the 3rd NMOS pipe group, the 4th NMOS pipe group, the 5th NMOS pipe group, the 6th NMOS pipe group, the 7th NMOS pipe group, the 8th NMOS pipe group, the 9th NMOS pipe group, the tenth NMOS pipe group, the 11 NMOS pipe group, the 12 NMOS pipe group and interleaved circuit unit, described signal sample circuit and described complementary signal sample circuit form by eight NMOS pipes, the grid of eight NMOS pipes in the grid of eight NMOS pipes in described signal sample circuit and described complementary signal sample circuit is connected to the first clock pulse signal input, the first clock pulse signal of the first described clock pulse signal input access amplitude level counterlogic 2, the source electrode of second NMOS pipe in the source electrode of first NMOS pipe in described signal sample circuit and described signal sample circuit is connected to the first sampled signal input, the source electrode of the four NMOS pipe in the source electrode of the 3rd NMOS pipe in described signal sample circuit and described signal sample circuit is connected to the second sampled signal input, the source electrode of the 6th NMOS pipe in the source electrode of the 5th NMOS pipe in described signal sample circuit and described signal sample circuit is connected to the 3rd sampled signal input, the source electrode of the 8th NMOS pipe in the source electrode of the 7th NMOS pipe in described signal sample circuit and described signal sample circuit is connected to the signal input part of described tri-valued, thermal-insulating JKL basic circuit, the source electrode of second NMOS pipe in the source electrode of first NMOS pipe in described complementary signal sample circuit and described complementary signal sample circuit is connected to the first complementary sampled signal input, the source electrode of the four NMOS pipe in the source electrode of the 3rd NMOS pipe in described complementary signal sample circuit and described complementary signal sample circuit is connected to the second complementary sampled signal input, the source electrode of the 6th NMOS pipe in the source electrode of the 5th NMOS pipe in described complementary signal sample circuit and described complementary signal sample circuit is connected to the 3rd complementary sampled signal input, the source electrode of the 8th NMOS pipe in the source electrode of the 7th NMOS pipe in described complementary signal sample circuit and described complementary signal sample circuit is connected to the complementary signal input of described tri-valued, thermal-insulating JKL basic circuit, a described NMOS pipe group is mainly made up of three NMOS pipes, and the source electrode of three NMOS pipes and drain electrode head and the tail serial connection, the 2nd described NMOS pipe group is mainly made up of three NMOS pipes, and the source electrode of three NMOS pipes and drain electrode head and the tail serial connection, the 3rd described NMOS pipe group is mainly made up of two NMOS pipes, and the source electrode of two NMOS pipes and drain electrode head and the tail serial connection, the 4th described NMOS pipe group is mainly made up of two NMOS pipes, and the source electrode of two NMOS pipes and drain electrode head and the tail serial connection, the 5th described NMOS pipe group is mainly made up of four NMOS pipe,And the source electrode of four NMOS pipe and drain electrode head and the tail serial connection, the 6th described NMOS pipe group is mainly made up of two NMOS pipes, and the source electrode of two NMOS pipes and drain electrode head and the tail serial connection, the 7th described NMOS pipe group is mainly made up of three NMOS pipes, and the source electrode of three NMOS pipes and drain electrode head and the tail serial connection, the 8th described NMOS pipe group is mainly made up of three NMOS pipes, and the source electrode of three NMOS pipes and drain electrode head and the tail serial connection, the 9th described NMOS pipe group is mainly made up of two NMOS pipes, and the source electrode of two NMOS pipes and drain electrode head and the tail serial connection, the tenth described NMOS pipe group is mainly made up of two NMOS pipes, and the source electrode of two NMOS pipes and drain electrode head and the tail serial connection, the 11 described NMOS pipe group is mainly made up of three NMOS pipes, and the source electrode of three NMOS pipes and drain electrode head and the tail serial connection, the 12 described NMOS pipe group is mainly made up of three NMOS pipes, and the source electrode of three NMOS pipes and drain electrode head and the tail serial connection, described interleaved circuit unit is mainly made up of two PMOS pipes and two NMOS pipes, the source grounding of two NMOS pipes in described interleaved circuit unit, the drain electrode of first PMOS pipe in described interleaved circuit unit, the drain electrode of first NMOS pipe in described interleaved circuit unit, the grid of second PMOS pipe in described interleaved circuit unit, the grid of second NMOS pipe in described interleaved circuit unit, the source electrode of last the NMOS pipe in a described NMOS pipe group, the source electrode of last the NMOS pipe in the 2nd described NMOS pipe group, the source electrode of last the NMOS pipe in the 3rd described NMOS pipe group, the source electrode of last the NMOS pipe in the 4th described NMOS pipe group, the source electrode of last the NMOS pipe in the source electrode of last the NMOS pipe in the 5th described NMOS pipe group and the 6th described NMOS pipe group is connected to the signal output part of described tri-valued, thermal-insulating JKL basic circuit, the drain electrode of second PMOS pipe in described interleaved circuit unit, the drain electrode of second NMOS pipe in described interleaved circuit unit, the grid of first PMOS pipe in described interleaved circuit unit, the grid of first NMOS pipe in described interleaved circuit unit, the source electrode of last the NMOS pipe in the 7th described NMOS pipe group, the source electrode of last the NMOS pipe in the 8th described NMOS pipe group, the source electrode of last the NMOS pipe in the 9th described NMOS pipe group, the source electrode of last the NMOS pipe in the tenth described NMOS pipe group, the source electrode of last the NMOS pipe in the source electrode of last the NMOS pipe in the 11 described NMOS pipe group and the 12 described NMOS pipe group is connected to the complementary signal output of described tri-valued, thermal-insulating JKL basic circuit, the drain electrode of first NMOS pipe in a described NMOS pipe group, the drain electrode of first NMOS pipe in the 2nd described NMOS pipe group,The drain electrode of first NMOS pipe in the 3rd described NMOS pipe group, the drain electrode of first NMOS pipe in the 7th described NMOS pipe group, the drain electrode of first NMOS pipe in the drain electrode of first NMOS pipe in the 8th described NMOS pipe group and the 9th described NMOS pipe group is connected to the first power clock signal of the first power clock signal input part and access amplitude level counterlogic 1, the drain electrode of first NMOS pipe in the 4th described NMOS pipe group, the drain electrode of first NMOS pipe in the 5th described NMOS pipe group, the drain electrode of first NMOS pipe in the 6th described NMOS pipe group, the drain electrode of first NMOS pipe in the tenth described NMOS pipe group, the drain electrode of first NMOS pipe in the 11 described NMOS pipe group, the drain electrode of first NMOS pipe in the 12 described NMOS pipe group, the source electrode of second PMOS pipe in the source electrode of first PMOS pipe in described interleaved circuit unit and described interleaved circuit unit is connected to the second clock pulse signal of second clock pulse signal input terminal and access amplitude level counterlogic 2, the drain electrode of first NMOS pipe in described signal sample circuit, the grid of second NMOS pipe in a described NMOS pipe group is connected with the grid of last NMOS pipe in the 4th described NMOS pipe group, the drain electrode of second NMOS pipe in described signal sample circuit is connected with the grid of second NMOS pipe in described the 7th NMOS pipe group, the drain electrode of the 3rd NMOS pipe in described signal sample circuit is connected with the grid of the 3rd NMOS pipe in described the 5th NMOS pipe group, the drain electrode of the four NMOS pipe in described signal sample circuit is connected with the grid of last the NMOS pipe in described the 11 NMOS pipe group, the drain electrode of the 5th NMOS pipe in described signal sample circuit is connected with the grid of last the NMOS pipe in described the 3rd NMOS pipe group, the drain electrode of the 6th NMOS pipe in described signal sample circuit, the grid of last the NMOS pipe in the 9th described NMOS pipe group is connected with the grid of second NMOS pipe in the 12 described NMOS pipe group, the drain electrode of the 7th NMOS pipe in described signal sample circuit, the grid of first NMOS pipe in the 2nd described NMOS pipe group, the grid of first NMOS pipe in the 3rd described NMOS pipe group, the grid of first NMOS pipe in the 5th described NMOS pipe group is connected with the grid of first NMOS pipe in the 6th described NMOS pipe group, the drain electrode of the 8th NMOS pipe in described signal sample circuit, the grid of first NMOS pipe in the 8th described NMOS pipe group, the grid of first NMOS pipe in the 9th described NMOS pipe group, the grid of first NMOS pipe in the 11 described NMOS pipe group is connected with the grid of first NMOS pipe in the 12 described NMOS pipe groupThe drain electrode of first NMOS pipe in described complementary signal sample circuit is connected with the grid of last the NMOS pipe in a described NMOS pipe group, the drain electrode of second NMOS pipe in described complementary signal sample circuit, the grid of last the NMOS pipe in the 7th described NMOS pipe group is connected with the grid of last the NMOS pipe in the tenth described NMOS pipe group, the drain electrode of the 3rd NMOS pipe in described complementary signal sample circuit, the grid of last the NMOS pipe in the 2nd described NMOS pipe group is connected with the grid of last the NMOS pipe in the 5th described NMOS pipe group, the drain electrode of the four NMOS pipe in described complementary signal sample circuit is connected with the grid of last the NMOS pipe in described the 8th NMOS pipe group, the drain electrode of the 5th NMOS pipe in described complementary signal sample circuit is connected with the grid of last the NMOS pipe in described the 6th NMOS pipe group, the drain electrode of the 6th NMOS pipe in described complementary signal sample circuit is connected with the grid of last the NMOS pipe in the 12 described NMOS pipe group, the drain electrode of the 7th NMOS pipe in described complementary signal sample circuit, the grid of first NMOS pipe in a described NMOS pipe group, the grid of second NMOS pipe in the 2nd described NMOS pipe group, the grid of first NMOS pipe in the 4th described NMOS pipe group is connected with the grid of second NMOS pipe in the 5th described NMOS pipe group, the drain electrode of the 8th NMOS pipe in described complementary signal sample circuit, the grid of first NMOS pipe in the 7th described NMOS pipe group, the grid of second NMOS pipe in the 8th described NMOS pipe group, the grid of first NMOS pipe in the tenth described NMOS pipe group is connected with the grid of second NMOS pipe in the 11 described NMOS pipe group.

Described DTCTGAL buffer is the buffer that input signal is identical with output signal, and the input signal of the DTCTGAL buffer described in the output signal ratio of described DTCTGAL buffer postpones the clock cycle half.

A kind of adiabatic novenary asynchronous counter, comprise the first tri-valued, thermal-insulating JKL trigger, the second tri-valued, thermal-insulating JKL trigger and tri-valued, thermal-insulating literal circuit, the circuit structure of the first described tri-valued, thermal-insulating JKL trigger is identical with the circuit structure of the second described tri-valued, thermal-insulating JKL trigger, the first described tri-valued, thermal-insulating JKL trigger comprises tri-valued, thermal-insulating JKL basic circuit and DTCTGAL buffer, the signal input part of described tri-valued, thermal-insulating JKL basic circuit is connected with the signal output part of described DTCTGAL buffer, the signal output part of described tri-valued, thermal-insulating JKL basic circuit is connected with the signal input part of described DTCTGAL buffer, the complementary signal output of described tri-valued, thermal-insulating JKL basic circuit is connected with the complementary signal input of described DTCTGAL buffer, described tri-valued, thermal-insulating JKL basic circuit accesses respectively the first power clock signal of amplitude level counterlogic 1, the first clock pulse signal of amplitude level counterlogic 2 and the second clock pulse signal of amplitude level counterlogic 2, described DTCTGAL buffer accesses respectively the second power clock signal of amplitude level counterlogic 1, the first clock pulse signal of amplitude level counterlogic 2 and the second clock pulse signal of amplitude level counterlogic 2,180 ° of the phase phasic differences of the phase place of the first described power clock signal and described the second power clock signal, 180 ° of the phase phasic differences of the phase place of the first described clock pulse signal and described second clock pulse signal, the time of delay of described DTCTGAL buffer is identical with the time of delay of described tri-valued, thermal-insulating JKL basic circuit, be the clock cycle half, the signal output part of the first described tri-valued, thermal-insulating JKL trigger is connected with the first signal input of described tri-valued, thermal-insulating literal circuit, the complementary signal output of the first described tri-valued, thermal-insulating JKL trigger is connected with the secondary signal input of described tri-valued, thermal-insulating literal circuit, the signal output part of described tri-valued, thermal-insulating literal circuit is connected with the second clock pulse signal input terminal of described the second tri-valued, thermal-insulating JKL trigger, the carry signal of the signal output part output of described tri-valued, thermal-insulating literal circuit is as the clock pulse of the second described tri-valued, thermal-insulating JKL trigger.

Compared with prior art, the invention has the advantages that: by adopting double-power clock, break through traditional circuit energy by electric energy to the irreversible transform mode of heat energy, utilize the bootstrap effect of NMOS pipe and the storage type structure of intersecting to realize energy injection and the recovery to output node, effectively reclaim the electric charge being housed on circuit node electric capacity, make circuit there is extremely low power consumption, and in thering is energy recovery characteristics, three value input and output of adiabatic circuits are realized, and circuit has higher information density, and functional reliability is high.

Brief description of the drawings

Fig. 1 a is the circuit diagram of tri-valued, thermal-insulating JKL basic circuit of the present invention;

Fig. 1 b is the circuit symbol figure of tri-valued, thermal-insulating JKL basic circuit of the present invention;

Fig. 2 a is the circuit diagram of a kind of tri-valued, thermal-insulating JKL trigger of the present invention;

Fig. 2 b is the circuit symbol figure of a kind of tri-valued, thermal-insulating JKL trigger of the present invention;

Fig. 3 is the circuit diagram of a kind of adiabatic novenary asynchronous counter of the present invention;

Fig. 4 is the analog waveform figure of a kind of tri-valued, thermal-insulating JKL trigger of the present invention;

Fig. 5 is the analog waveform figure of a kind of adiabatic novenary asynchronous counter of the present invention;

Fig. 6 is the transient state energy consumption comparison diagram of a kind of tri-valued, thermal-insulating JKL trigger of the present invention and three value JKL triggers;

Fig. 7 is the transient state energy consumption comparison diagram of a kind of adiabatic novenary asynchronous counter of the present invention and novenary asynchronous counter.

Embodiment

Below in conjunction with accompanying drawing, embodiment is described in further detail the present invention.

A kind of tri-valued, thermal-insulating JKL trigger of the present invention, its circuit diagram as shown in Figure 2 a, circuit symbol figure as shown in Figure 2 b, it comprises tri-valued, thermal-insulating JKL basic circuit F and DTCTGAL buffer, the signal input part of tri-valued, thermal-insulating JKL basic circuit F is connected with the signal output part of DTCTGAL buffer, the signal output part of tri-valued, thermal-insulating JKL basic circuit is connected with the signal input part of DTCTGAL buffer, the complementary signal output of tri-valued, thermal-insulating JKL basic circuit is connected with the complementary signal input of DTCTGAL buffer, tri-valued, thermal-insulating JKL basic circuit accesses respectively the first power clock signal Phi of amplitude level counterlogic 1 ₁, amplitude level counterlogic 2 the first clock pulse signal with the second clock pulse signal Φ of amplitude level counterlogic 2, DTCTGAL buffer accesses respectively the second power clock signal of amplitude level counterlogic 1 the first clock pulse signal of amplitude level counterlogic 2 with the second clock pulse signal Φ of amplitude level counterlogic 2, the first power clock signal Phi ₁phase place and the second power clock signal 180 ° of phase phasic differences, the first clock pulse signal phase place and 180 ° of the phase phasic differences of second clock pulse signal Φ, the time of delay of DTCTGAL buffer is identical with the time of delay of tri-valued, thermal-insulating JKL basic circuit, is the clock cycle half.

The design process of a kind of tri-valued, thermal-insulating JKL trigger in the present invention is: first utilize DTCTGAL(double-power clock three-value clock control transmission gate adiabatic logic) design philosophy of circuit, according to the truth table design tri-valued, thermal-insulating JKL basic circuit of three value JKL triggers, table one is the truth table of three value JKL triggers.

The truth table of table one three value JKL triggers

In table one, J, K, L are input signal, Q ⁿfor existing state, Q ⁿ⁺¹for next state, d is the { arbitrary value in 0,1,2}.According to Three Essential Circuit Elements theory, associative list one, can derive and obtain the circuit diagram of tri-valued, thermal-insulating JKL basic circuit by Karnaugh map abbreviation method, wherein the first clock pulse signal with second clock pulse signal Φ under circuit different operating state or as power clock or as clock clock, its concrete operations are divided into two-stage: (1) is at clock clock under control, utilize NMOS pipe to complete the sampling to each input signal; (2) at power clock Φ, Φ ₁under control, assignment and energy that the nmos circuit module that utilization is built by sampled value and CMOS-latch structure complete output loading reclaim; Wherein, Φ ₁, Φ phase place identical, and with 180 ° of phase differences; But Φ ₁with Φ, amplitude level difference, is respectively V _dD/ 2, V _dD, represent logical one, 2.

Tri-valued, thermal-insulating JKL basic circuit, its circuit diagram as shown in Figure 1a, circuit symbol figure as shown in Figure 1 b, it comprises signal sample circuit, complementary signal sample circuit, the one NMOS pipe group M1, the 2nd NMOS pipe group M2, the 3rd NMOS pipe group M3, the 4th NMOS pipe group M4, the 5th NMOS pipe group M5, the 6th NMOS pipe group M6, the 7th NMOS pipe group M7, the 8th NMOS pipe group M8, the 9th NMOS pipe group M9, the tenth NMOS pipe group M10, the 11 NMOS pipe group M11, the 12 NMOS pipe group M12 and interleaved circuit unit, signal sample circuit and complementary signal sample circuit are by eight NMOS pipe compositions, the grid of eight NMOS pipes in grid and the complementary signal sample circuit of eight NMOS pipes in signal sample circuit is connected to the first clock pulse signal input, the first clock pulse signal of the first clock pulse signal input access amplitude level counterlogic 2 the source electrode of second NMOS pipe N2 in source electrode and the signal sample circuit of first NMOS pipe N1 in signal sample circuit is connected to the first sampled signal input, the source electrode of four NMOS pipe N4 in source electrode and the signal sample circuit of the 3rd NMOS pipe N3 in signal sample circuit is connected to the second sampled signal input, the source electrode of the 6th NMOS pipe N6 in source electrode and the signal sample circuit of the 5th NMOS pipe N5 in signal sample circuit is connected to the 3rd sampled signal input, the source electrode of the 8th NMOS pipe N8 in source electrode and the signal sample circuit of the 7th NMOS pipe N7 in signal sample circuit is connected to the signal input part of tri-valued, thermal-insulating JKL basic circuit, the source electrode of second NMOS pipe N10 in source electrode and the complementary signal sample circuit of first NMOS pipe N9 in complementary signal sample circuit is connected to the first complementary sampled signal input, the source electrode of four NMOS pipe N12 in source electrode and the complementary signal sample circuit of the 3rd NMOS pipe N11 in complementary signal sample circuit is connected to the second complementary sampled signal input, the source electrode of the 6th NMOS pipe N14 in source electrode and the complementary signal sample circuit of the 5th NMOS pipe N13 in complementary signal sample circuit is connected to the 3rd complementary sampled signal input, the source electrode of the 8th NMOS pipe N16 in source electrode and the complementary signal sample circuit of the 7th NMOS pipe N15 in complementary signal sample circuit is connected to the complementary signal input of tri-valued, thermal-insulating JKL basic circuit, the one NMOS pipe group M1 is mainly made up of three NMOS pipes, and the source electrode of three NMOS pipes and drain electrode head and the tail serial connectionThe 2nd NMOS pipe group M2 is mainly made up of three NMOS pipes, and the source electrode of three NMOS pipes and drain electrode head and the tail serial connection, the 3rd NMOS pipe group M3 is mainly made up of two NMOS pipes, and the source electrode of two NMOS pipes and drain electrode head and the tail serial connection, the 4th NMOS pipe group M4 is mainly made up of two NMOS pipes, and the source electrode of two NMOS pipes and drain electrode head and the tail serial connection, the 5th NMOS pipe group M5 is mainly made up of four NMOS pipe, and the source electrode of four NMOS pipe and drain electrode head and the tail serial connection, the 6th NMOS pipe group M6 is mainly made up of two NMOS pipes, and the source electrode of two NMOS pipes and drain electrode head and the tail serial connection, the 7th NMOS pipe group M7 is mainly made up of three NMOS pipes, and the source electrode of three NMOS pipes and drain electrode head and the tail serial connection, the 8th NMOS pipe group M8 is mainly made up of three NMOS pipes, and the source electrode of three NMOS pipes and drain electrode head and the tail serial connection, the 9th NMOS pipe group M9 is mainly made up of two NMOS pipes, and the source electrode of two NMOS pipes and drain electrode head and the tail serial connection, the tenth NMOS pipe group M10 is mainly made up of two NMOS pipes, and the source electrode of two NMOS pipes and drain electrode head and the tail serial connection, the 11 NMOS pipe group M11 is mainly made up of three NMOS pipes, and the source electrode of three NMOS pipes and drain electrode head and the tail serial connection, the 12 NMOS pipe group M12 is mainly made up of three NMOS pipes, and the source electrode of three NMOS pipes and drain electrode head and the tail serial connection, interleaved circuit unit is mainly made up of two PMOS pipes and two NMOS pipes, the source grounding of two NMOS pipes in interleaved circuit unit, the drain electrode of first PMOS pipe P1 in interleaved circuit unit, the drain electrode of first NMOS pipe N33 in interleaved circuit unit, the grid of second PMOS pipe P2 in interleaved circuit unit, the grid of second NMOS pipe N34 in interleaved circuit unit, the source electrode of last NMOS pipe N19 in the one NMOS pipe group M1, the source electrode of last NMOS pipe N22 in the 2nd NMOS pipe group M2, the source electrode of last NMOS pipe N24 in the 3rd NMOS pipe group M3, the source electrode of last NMOS pipe N26 in the 4th NMOS pipe group M4, the source electrode of last NMOS pipe N32 in source electrode and the 6th NMOS pipe group M6 of last NMOS pipe N30 in the 5th NMOS pipe group M5 is connected to the signal output part of tri-valued, thermal-insulating JKL basic circuit, the drain electrode of second PMOS pipe P2 in interleaved circuit unit, the drain electrode of second NMOS pipe N34 in interleaved circuit unit, the grid of first PMOS pipe P1 in interleaved circuit unit, the grid of first NMOS pipe N33 in interleaved circuit unit, the source electrode of last NMOS pipe N37 in the 7th NMOS pipe group M7, the source electrode of last NMOS pipe N40 in the 8th NMOS pipe group M8, the source electrode of last NMOS pipe N42 in the 9th NMOS pipe group M9,The source electrode of last NMOS pipe N44 in the tenth NMOS pipe group M10, the source electrode of last NMOS pipe N50 in source electrode and the 12 NMOS pipe group M12 of last NMOS pipe N47 in the 11 NMOS pipe group M11 is connected to the complementary signal output of tri-valued, thermal-insulating JKL basic circuit, the drain electrode of first NMOS pipe N17 in the one NMOS pipe group M1, the drain electrode of first NMOS pipe N20 in the 2nd NMOS pipe group M2, the drain electrode of first NMOS pipe N23 in the 3rd NMOS pipe group M3, the drain electrode of first NMOS pipe N35 in the 7th NMOS pipe group M7, the drain electrode of first NMOS pipe N41 in drain electrode and the 9th NMOS pipe group M9 of first NMOS pipe N38 in the 8th NMOS pipe group M8 is connected to the first power clock signal Phi of the first power clock signal input part and access amplitude level counterlogic 1 ₁the drain electrode of first NMOS pipe N25 in the 4th NMOS pipe group M4, the drain electrode of first NMOS pipe N27 in the 5th NMOS pipe group M5, the drain electrode of first NMOS pipe N31 in the 6th NMOS pipe group M6, the drain electrode of first NMOS pipe N43 in the tenth NMOS pipe group M10, the drain electrode of first NMOS pipe N45 in the 11 NMOS pipe group M11, the drain electrode of first NMOS pipe N48 in the 12 NMOS pipe group M12, the source electrode of second PMOS pipe P2 in source electrode and the interleaved circuit unit of first PMOS pipe P1 in interleaved circuit unit is connected to the second clock pulse signal Φ of second clock pulse signal input terminal and access amplitude level counterlogic 2, the drain electrode of first NMOS pipe N1 in signal sample circuit, the grid of second NMOS pipe N18 in the one NMOS pipe group M1 is connected with the grid of last NMOS pipe N26 in the 4th NMOS pipe group M4, the drain electrode of second NMOS pipe N2 in signal sample circuit is connected with the grid of second NMOS pipe N36 in the 7th NMOS pipe group M7, the drain electrode of the 3rd NMOS pipe N3 in signal sample circuit is connected with the grid of the 3rd NMOS pipe N29 in the 5th NMOS pipe group M5, the drain electrode of four NMOS pipe N4 in signal sample circuit is connected with the grid of last the NMOS pipe N47 in the 11 NMOS pipe group M11, the drain electrode of the 5th NMOS pipe N5 in signal sample circuit is connected with the grid of last the NMOS pipe N24 in the 3rd NMOS pipe group M3, the drain electrode of the 6th NMOS pipe N6 in signal sample circuit, the grid of last NMOS pipe N42 in the 9th NMOS pipe group M9 is connected with the grid of second NMOS pipe N49 in the 12 NMOS pipe group M12, the drain electrode of the 7th NMOS pipe N7 in signal sample circuit,The grid of first NMOS pipe N20 in the 2nd NMOS pipe group M2, the grid of first NMOS pipe N23 in the 3rd NMOS pipe group M3, the grid of first NMOS pipe N27 in the 5th NMOS pipe group M5 is connected with the grid of first NMOS pipe N31 in the 6th NMOS pipe group M6, the drain electrode of the 8th NMOS pipe N8 in signal sample circuit, the grid of first NMOS pipe N38 in the 8th NMOS pipe group M8, the grid of first NMOS pipe N41 in the 9th NMOS pipe group M9, the grid of first NMOS pipe N45 in the 11 NMOS pipe group M11 is connected with the grid of first NMOS pipe N48 in the 12 NMOS pipe group M12, the drain electrode of first NMOS pipe N9 in complementary signal sample circuit is connected with the grid of last the NMOS pipe N19 in a NMOS pipe group M1, the drain electrode of second NMOS pipe N10 in complementary signal sample circuit, the grid of last NMOS pipe N37 in the 7th NMOS pipe group M7 is connected with the grid of last the NMOS pipe N44 in the tenth NMOS pipe group M10, the drain electrode of the 3rd NMOS pipe N11 in complementary signal sample circuit, the grid of last NMOS pipe N22 in the 2nd NMOS pipe group M2 is connected with the grid of last the NMOS pipe N30 in the 5th NMOS pipe group M5, the drain electrode of four NMOS pipe N12 in complementary signal sample circuit is connected with the grid of last the NMOS pipe N40 in the 8th NMOS pipe group M8, the drain electrode of the 5th NMOS pipe 13 in complementary signal sample circuit is connected with the grid of last the NMOS pipe N32 in the 6th NMOS pipe group M6, the drain electrode of the 6th NMOS pipe N14 in complementary signal sample circuit is connected with the grid of last the NMOS pipe N50 in the 12 NMOS pipe group M12, the drain electrode of the 7th NMOS pipe N15 in complementary signal sample circuit, the grid of first NMOS pipe N17 in the one NMOS pipe group M1, the grid of second NMOS pipe N21 in the 2nd NMOS pipe group M2, the grid of first NMOS pipe N25 in the 4th NMOS pipe group M4 is connected with the grid of second NMOS pipe N27 in the 5th NMOS pipe group M5, the drain electrode of the 8th NMOS pipe N16 in complementary signal sample circuit, the grid of first NMOS pipe N35 in the 7th NMOS pipe group M7, the grid of second NMOS pipe N39 in the 8th NMOS pipe group M8, the grid of first NMOS pipe N43 in the tenth NMOS pipe group M10 is connected with the grid of second NMOS pipe N46 in the 11 NMOS pipe group M11.

DTCTGAL buffer is the buffer that input signal is identical with output signal, and the input signal of the output signal ratio DTCTGAL buffer of DTCTGAL buffer postpones the clock cycle half.

The adiabatic novenary asynchronous counter of one of the present invention, its circuit diagram as shown in Figure 3, comprise the first tri-valued, thermal-insulating JKL trigger, the second tri-valued, thermal-insulating JKL trigger and tri-valued, thermal-insulating literal circuit, the circuit structure of the first tri-valued, thermal-insulating JKL trigger is identical with the circuit structure of the second tri-valued, thermal-insulating JKL trigger, the first tri-valued, thermal-insulating JKL trigger comprises tri-valued, thermal-insulating JKL basic circuit and DTCTGAL buffer, the signal input part of tri-valued, thermal-insulating JKL basic circuit is connected with the signal output part of DTCTGAL buffer, the signal output part of tri-valued, thermal-insulating JKL basic circuit is connected with the signal input part of DTCTGAL buffer, the complementary signal output of tri-valued, thermal-insulating JKL basic circuit is connected with the complementary signal input of DTCTGAL buffer, tri-valued, thermal-insulating JKL basic circuit accesses respectively the first power clock signal Phi of amplitude level counterlogic 1 ₁, amplitude level counterlogic 2 the first clock pulse signal with the second clock pulse signal Φ of amplitude level counterlogic 2, DTCTGAL buffer accesses respectively the second power clock signal of amplitude level counterlogic 1 the first clock pulse signal of amplitude level counterlogic 2 with the second clock pulse signal Φ of amplitude level counterlogic 2, the first power clock signal Phi ₁phase place and the second power clock signal 180 ° of phase phasic differences, the first clock pulse signal phase place and 180 ° of the phase phasic differences of second clock pulse signal Φ, the time of delay of DTCTGAL buffer is identical with the time of delay of tri-valued, thermal-insulating JKL basic circuit, be the clock cycle half, first signal output part of tri-valued, thermal-insulating JKL trigger and the first signal input of tri-valued, thermal-insulating literal circuit are connected, the first complementary signal output of tri-valued, thermal-insulating JKL trigger and the secondary signal input of tri-valued, thermal-insulating literal circuit are connected, the signal output part of tri-valued, thermal-insulating literal circuit is connected with the second clock pulse signal input terminal of the second tri-valued, thermal-insulating JKL trigger, the carry signal of the signal output part output of tri-valued, thermal-insulating literal circuit is as the clock pulse of the second tri-valued, thermal-insulating JKL trigger.

Adopting in TSMC0.25 μ mCMOS technique device parameters situation, the adiabatic novenary asynchronous counter of the one shown in a kind of tri-valued, thermal-insulating JKL trigger shown in Fig. 2 a and Fig. 3 is carried out to HSPICE emulation.Wherein, clock pulse Φ power clock Φ 1 amplitude voltage be respectively 2.5V, 1.25V, clock frequency is 16.7MHz, load capacitance is 10fF.As shown in Figure 4, wherein J, K, L are input signal to the analog waveform of tri-valued, thermal-insulating JKL trigger, and Q is output signal.Analysis chart 4 can find, output signal ratio input signal postpones a clock cycle, meets the sequential feature of tri-valued, thermal-insulating JKL trigger.Work as J=0, K=2, L=2, Q ⁿ=0 o'clock, Q ⁿ⁺¹=0; Work as J=1, K=0, L=0, Q ⁿ=0 o'clock, Q ⁿ⁺¹=1; Work as J=0, K=1, L=2, Q ⁿ=1 o'clock, Q ⁿ⁺¹=2; ...; All the other can be analyzed and obtain successively, and its Output rusults is consistent with table one, thereby have verified the correctness of tri-valued, thermal-insulating JKL trigger logic function; The analog waveform of adiabatic novenary asynchronous counter as shown in Figure 5, wherein, J ₀, K ₀, L ₀, J ₁, K ₁, L ₁for the input signal of counter, Q ₀, Q ₁for the output signal of counter; Can find by analysis, the output signal ratio input signal of adiabatic novenary asynchronous counter postpones a clock cycle, and designed circuit has correct logic function, output waveform ideal.

Adopting in TSMC0.25 μ mCMOS technique device parameters situation clock pulse Φ power clock Φ ₁ amplitude voltage be respectively 2.5V, 1.25V, clock frequency is 16.7MHz, load capacitance is 10fF, the transient state energy consumption comparison diagram of tri-valued, thermal-insulating JKL trigger and three value JKL triggers as shown in Figure 6, analysis chart 6 is known, and within the 600ns time, the energy consumption of tri-valued, thermal-insulating JKL trigger is 1.503pj, and the energy consumption of three value JKL triggers is 10.613pj, energy consumption saves approximately 85.8%.

Adopting in TSMC0.25 μ mCMOS technique device parameters situation clock pulse Φ power clock Φ ₁ amplitude voltage be respectively 2.5V, 1.25V, clock frequency is 16.7MHz, load capacitance is 10fF, the transient state energy consumption comparison diagram of adiabatic novenary asynchronous counter and novenary asynchronous counter as shown in Figure 7, analysis chart 7 is known, within the 600ns time, the energy consumption of adiabatic novenary asynchronous counter is 4.031pj, and the energy consumption of novenary asynchronous counter is 16.438pj, energy consumption saves approximately 75.5%, as can be seen here, tri-valued, thermal-insulating JKL trigger and adiabatic novenary counter have good energy recovery characteristics, and energy consumption is saved significantly.

Claims

1. a tri-valued, thermal-insulating JKL trigger, it is characterized in that comprising tri-valued, thermal-insulating JKL basic circuit and DTCTGAL buffer, the signal input part of described tri-valued, thermal-insulating JKL basic circuit is connected with the signal output part of described DTCTGAL buffer, the signal output part of described tri-valued, thermal-insulating JKL basic circuit is connected with the signal input part of described DTCTGAL buffer, the complementary signal output of described tri-valued, thermal-insulating JKL basic circuit is connected with the complementary signal input of described DTCTGAL buffer, described tri-valued, thermal-insulating JKL basic circuit accesses respectively the first power clock signal of amplitude level counterlogic 1, the first clock pulse signal of amplitude level counterlogic 2 and the second clock pulse signal of amplitude level counterlogic 2, described DTCTGAL buffer accesses respectively the second power clock signal of amplitude level counterlogic 1, the first clock pulse signal of amplitude level counterlogic 2 and the second clock pulse signal of amplitude level counterlogic 2, 180 ° of the phase phasic differences of the phase place of the first described power clock signal and described the second power clock signal, 180 ° of the phase phasic differences of the phase place of the first described clock pulse signal and described second clock pulse signal, the time delay of described DTCTGAL buffer is identical with the time delay of described tri-valued, thermal-insulating JKL basic circuit, be the clock cycle half, described tri-valued, thermal-insulating JKL basic circuit comprises signal sample circuit, complementary signal sample circuit, the one NMOS pipe group, the 2nd NMOS pipe group, the 3rd NMOS pipe group, the 4th NMOS pipe group, the 5th NMOS pipe group, the 6th NMOS pipe group, the 7th NMOS pipe group, the 8th NMOS pipe group, the 9th NMOS pipe group, the tenth NMOS pipe group, the 11 NMOS pipe group, the 12 NMOS pipe group and interleaved circuit unit, described signal sample circuit and described complementary signal sample circuit form by eight NMOS pipes, the grid of eight NMOS pipes in the grid of eight NMOS pipes in described signal sample circuit and described complementary signal sample circuit is connected to the first clock pulse signal input, the first clock pulse signal of the first described clock pulse signal input access amplitude level counterlogic 2, the source electrode of second NMOS pipe in the source electrode of first NMOS pipe in described signal sample circuit and described signal sample circuit is connected to the first sampled signal input, the source electrode of the four NMOS pipe in the source electrode of the 3rd NMOS pipe in described signal sample circuit and described signal sample circuit is connected to the second sampled signal input, the source electrode of the 6th NMOS pipe in the source electrode of the 5th NMOS pipe in described signal sample circuit and described signal sample circuit is connected to the 3rd sampled signal input, the source electrode of the 8th NMOS pipe in the source electrode of the 7th NMOS pipe in described signal sample circuit and described signal sample circuit is connected to the signal input part of described tri-valued, thermal-insulating JKL basic circuit,The source electrode of second NMOS pipe in the source electrode of first NMOS pipe in described complementary signal sample circuit and described complementary signal sample circuit is connected to the first complementary sampled signal input, the source electrode of the four NMOS pipe in the source electrode of the 3rd NMOS pipe in described complementary signal sample circuit and described complementary signal sample circuit is connected to the second complementary sampled signal input, the source electrode of the 6th NMOS pipe in the source electrode of the 5th NMOS pipe in described complementary signal sample circuit and described complementary signal sample circuit is connected to the 3rd complementary sampled signal input, the source electrode of the 8th NMOS pipe in the source electrode of the 7th NMOS pipe in described complementary signal sample circuit and described complementary signal sample circuit is connected to the complementary signal input of described tri-valued, thermal-insulating JKL basic circuit, a described NMOS pipe group is mainly made up of three NMOS pipes, and the source electrode of three NMOS pipes and drain electrode head and the tail serial connection, the 2nd described NMOS pipe group is mainly made up of three NMOS pipes, and the source electrode of three NMOS pipes and drain electrode head and the tail serial connection, the 3rd described NMOS pipe group is mainly made up of two NMOS pipes, and the source electrode of two NMOS pipes and drain electrode head and the tail serial connection, the 4th described NMOS pipe group is mainly made up of two NMOS pipes, and the source electrode of two NMOS pipes and drain electrode head and the tail serial connection, the 5th described NMOS pipe group is mainly made up of four NMOS pipe, and the source electrode of four NMOS pipe and drain electrode head and the tail serial connection, the 6th described NMOS pipe group is mainly made up of two NMOS pipes, and the source electrode of two NMOS pipes and drain electrode head and the tail serial connection, the 7th described NMOS pipe group is mainly made up of three NMOS pipes, and the source electrode of three NMOS pipes and drain electrode head and the tail serial connection, the 8th described NMOS pipe group is mainly made up of three NMOS pipes, and the source electrode of three NMOS pipes and drain electrode head and the tail serial connection, the 9th described NMOS pipe group is mainly made up of two NMOS pipes, and the source electrode of two NMOS pipes and drain electrode head and the tail serial connection, the tenth described NMOS pipe group is mainly made up of two NMOS pipes, and the source electrode of two NMOS pipes and drain electrode head and the tail serial connection, the 11 described NMOS pipe group is mainly made up of three NMOS pipes, and the source electrode of three NMOS pipes and drain electrode head and the tail serial connection, the 12 described NMOS pipe group is mainly made up of three NMOS pipes, and the source electrode of three NMOS pipes and drain electrode head and the tail serial connection, described interleaved circuit unit is mainly made up of two PMOS pipes and two NMOS pipes, the source grounding of two NMOS pipes in described interleaved circuit unit, the drain electrode of first PMOS pipe in described interleaved circuit unit, the drain electrode of first NMOS pipe in described interleaved circuit unit, the grid of second PMOS pipe in described interleaved circuit unit, the grid of second NMOS pipe in described interleaved circuit unit, the source electrode of last the NMOS pipe in a described NMOS pipe group, the source electrode of last the NMOS pipe in the 2nd described NMOS pipe group,The source electrode of last the NMOS pipe in the 3rd described NMOS pipe group, the source electrode of last the NMOS pipe in the 4th described NMOS pipe group, the source electrode of last the NMOS pipe in the source electrode of last the NMOS pipe in the 5th described NMOS pipe group and the 6th described NMOS pipe group is connected to the signal output part of described tri-valued, thermal-insulating JKL basic circuit, the drain electrode of second PMOS pipe in described interleaved circuit unit, the drain electrode of second NMOS pipe in described interleaved circuit unit, the grid of first PMOS pipe in described interleaved circuit unit, the grid of first NMOS pipe in described interleaved circuit unit, the source electrode of last the NMOS pipe in the 7th described NMOS pipe group, the source electrode of last the NMOS pipe in the 8th described NMOS pipe group, the source electrode of last the NMOS pipe in the 9th described NMOS pipe group, the source electrode of last the NMOS pipe in the tenth described NMOS pipe group, the source electrode of last the NMOS pipe in the source electrode of last the NMOS pipe in the 11 described NMOS pipe group and the 12 described NMOS pipe group is connected to the complementary signal output of described tri-valued, thermal-insulating JKL basic circuit, the drain electrode of first NMOS pipe in a described NMOS pipe group, the drain electrode of first NMOS pipe in the 2nd described NMOS pipe group, the drain electrode of first NMOS pipe in the 3rd described NMOS pipe group, the drain electrode of first NMOS pipe in the 7th described NMOS pipe group, the drain electrode of first NMOS pipe in the drain electrode of first NMOS pipe in the 8th described NMOS pipe group and the 9th described NMOS pipe group is connected to the first power clock signal of the first power clock signal input part and access amplitude level counterlogic 1, the drain electrode of first NMOS pipe in the 4th described NMOS pipe group, the drain electrode of first NMOS pipe in the 5th described NMOS pipe group, the drain electrode of first NMOS pipe in the 6th described NMOS pipe group, the drain electrode of first NMOS pipe in the tenth described NMOS pipe group, the drain electrode of first NMOS pipe in the 11 described NMOS pipe group, the drain electrode of first NMOS pipe in the 12 described NMOS pipe group, the source electrode of second PMOS pipe in the source electrode of first PMOS pipe in described interleaved circuit unit and described interleaved circuit unit is connected to the second clock pulse signal of second clock pulse signal input terminal and access amplitude level counterlogic 2, the drain electrode of first NMOS pipe in described signal sample circuit, the grid of second NMOS pipe in a described NMOS pipe group is connected with the grid of last NMOS pipe in the 4th described NMOS pipe group, the drain electrode of second NMOS pipe in described signal sample circuit is connected with the grid of second NMOS pipe in described the 7th NMOS pipe groupThe drain electrode of the 3rd NMOS pipe in described signal sample circuit is connected with the grid of the 3rd NMOS pipe in described the 5th NMOS pipe group, the drain electrode of the four NMOS pipe in described signal sample circuit is connected with the grid of last the NMOS pipe in described the 11 NMOS pipe group, the drain electrode of the 5th NMOS pipe in described signal sample circuit is connected with the grid of last the NMOS pipe in described the 3rd NMOS pipe group, the drain electrode of the 6th NMOS pipe in described signal sample circuit, the grid of last the NMOS pipe in the 9th described NMOS pipe group is connected with the grid of second NMOS pipe in the 12 described NMOS pipe group, the drain electrode of the 7th NMOS pipe in described signal sample circuit, the grid of first NMOS pipe in the 2nd described NMOS pipe group, the grid of first NMOS pipe in the 3rd described NMOS pipe group, the grid of first NMOS pipe in the 5th described NMOS pipe group is connected with the grid of first NMOS pipe in the 6th described NMOS pipe group, the drain electrode of the 8th NMOS pipe in described signal sample circuit, the grid of first NMOS pipe in the 8th described NMOS pipe group, the grid of first NMOS pipe in the 9th described NMOS pipe group, the grid of first NMOS pipe in the 11 described NMOS pipe group is connected with the grid of first NMOS pipe in the 12 described NMOS pipe group, the drain electrode of first NMOS pipe in described complementary signal sample circuit is connected with the grid of last the NMOS pipe in a described NMOS pipe group, the drain electrode of second NMOS pipe in described complementary signal sample circuit, the grid of last the NMOS pipe in the 7th described NMOS pipe group is connected with the grid of last the NMOS pipe in the tenth described NMOS pipe group, the drain electrode of the 3rd NMOS pipe in described complementary signal sample circuit, the grid of last the NMOS pipe in the 2nd described NMOS pipe group is connected with the grid of last the NMOS pipe in the 5th described NMOS pipe group, the drain electrode of the four NMOS pipe in described complementary signal sample circuit is connected with the grid of last the NMOS pipe in described the 8th NMOS pipe group, the drain electrode of the 5th NMOS pipe in described complementary signal sample circuit is connected with the grid of last the NMOS pipe in described the 6th NMOS pipe group, the drain electrode of the 6th NMOS pipe in described complementary signal sample circuit is connected with the grid of last the NMOS pipe in the 12 described NMOS pipe group, the drain electrode of the 7th NMOS pipe in described complementary signal sample circuit, the grid of first NMOS pipe in a described NMOS pipe group, the grid of second NMOS pipe in the 2nd described NMOS pipe group, the grid of first NMOS pipe in the 4th described NMOS pipe group is connected with the grid of second NMOS pipe in the 5th described NMOS pipe groupThe grid of first NMOS pipe in the grid of second NMOS pipe in the grid of first NMOS pipe in the drain electrode of the 8th NMOS pipe in described complementary signal sample circuit, the 7th described NMOS pipe group, the 8th described NMOS pipe group, the tenth described NMOS pipe group is connected with the grid of second NMOS pipe in the 11 described NMOS pipe group.

2. a kind of tri-valued, thermal-insulating JKL trigger according to claim 1, it is characterized in that described DTCTGAL buffer is the buffer that input signal is identical with output signal, the input signal of the DTCTGAL buffer described in the output signal ratio of described DTCTGAL buffer postpones the clock cycle half.

3. an adiabatic novenary asynchronous counter, comprise the first tri-valued, thermal-insulating JKL trigger, the second tri-valued, thermal-insulating JKL trigger and tri-valued, thermal-insulating literal circuit, the circuit structure of the first described tri-valued, thermal-insulating JKL trigger is identical with the circuit structure of the second described tri-valued, thermal-insulating JKL trigger, it is characterized in that the first described tri-valued, thermal-insulating JKL trigger comprises tri-valued, thermal-insulating JKL basic circuit and DTCTGAL buffer, the signal input part of described tri-valued, thermal-insulating JKL basic circuit is connected with the signal output part of described DTCTGAL buffer, the signal output part of described tri-valued, thermal-insulating JKL basic circuit is connected with the signal input part of described DTCTGAL buffer, the complementary signal output of described tri-valued, thermal-insulating JKL basic circuit is connected with the complementary signal input of described DTCTGAL buffer, described tri-valued, thermal-insulating JKL basic circuit accesses respectively the first power clock signal of amplitude level counterlogic 1, the first clock pulse signal of amplitude level counterlogic 2 and the second clock pulse signal of amplitude level counterlogic 2, described DTCTGAL buffer accesses respectively the second power clock signal of amplitude level counterlogic 1, the first clock pulse signal of amplitude level counterlogic 2 and the second clock pulse signal of amplitude level counterlogic 2, 180 ° of the phase phasic differences of the phase place of the first described power clock signal and described the second power clock signal, 180 ° of the phase phasic differences of the phase place of the first described clock pulse signal and described second clock pulse signal, the time delay of described DTCTGAL buffer is identical with the time delay of described tri-valued, thermal-insulating JKL basic circuit, be the clock cycle half, the signal output part of the first described tri-valued, thermal-insulating JKL trigger is connected with the first signal input of described tri-valued, thermal-insulating literal circuit, the complementary signal output of the first described tri-valued, thermal-insulating JKL trigger is connected with the secondary signal input of described tri-valued, thermal-insulating literal circuit, the signal output part of described tri-valued, thermal-insulating literal circuit is connected with the second clock pulse signal input terminal of described the second tri-valued, thermal-insulating JKL trigger, the carry signal of the signal output part output of described tri-valued, thermal-insulating literal circuit is as the clock pulses of the second described tri-valued, thermal-insulating JKL trigger, described tri-valued, thermal-insulating JKL basic circuit comprises signal sample circuit, complementary signal sample circuit, the one NMOS pipe group, the 2nd NMOS pipe group, the 3rd NMOS pipe group, the 4th NMOS pipe group, the 5th NMOS pipe group, the 6th NMOS pipe group, the 7th NMOS pipe group, the 8th NMOS pipe group, the 9th NMOS pipe group, the tenth NMOS pipe group, the 11 NMOS pipe group, the 12 NMOS pipe group and interleaved circuit unit, described signal sample circuit and described complementary signal sample circuit form by eight NMOS pipes, the grid of eight NMOS pipes in the grid of eight NMOS pipes in described signal sample circuit and described complementary signal sample circuit is connected to the first clock pulse signal input,The first clock pulse signal of the first described clock pulse signal input access amplitude level counterlogic 2, the source electrode of second NMOS pipe in the source electrode of first NMOS pipe in described signal sample circuit and described signal sample circuit is connected to the first sampled signal input, the source electrode of the four NMOS pipe in the source electrode of the 3rd NMOS pipe in described signal sample circuit and described signal sample circuit is connected to the second sampled signal input, the source electrode of the 6th NMOS pipe in the source electrode of the 5th NMOS pipe in described signal sample circuit and described signal sample circuit is connected to the 3rd sampled signal input, the source electrode of the 8th NMOS pipe in the source electrode of the 7th NMOS pipe in described signal sample circuit and described signal sample circuit is connected to the signal input part of described tri-valued, thermal-insulating JKL basic circuit, the source electrode of second NMOS pipe in the source electrode of first NMOS pipe in described complementary signal sample circuit and described complementary signal sample circuit is connected to the first complementary sampled signal input, the source electrode of the four NMOS pipe in the source electrode of the 3rd NMOS pipe in described complementary signal sample circuit and described complementary signal sample circuit is connected to the second complementary sampled signal input, the source electrode of the 6th NMOS pipe in the source electrode of the 5th NMOS pipe in described complementary signal sample circuit and described complementary signal sample circuit is connected to the 3rd complementary sampled signal input, the source electrode of the 8th NMOS pipe in the source electrode of the 7th NMOS pipe in described complementary signal sample circuit and described complementary signal sample circuit is connected to the complementary signal input of described tri-valued, thermal-insulating JKL basic circuit, a described NMOS pipe group is mainly made up of three NMOS pipes, and the source electrode of three NMOS pipes and drain electrode head and the tail serial connection, the 2nd described NMOS pipe group is mainly made up of three NMOS pipes, and the source electrode of three NMOS pipes and drain electrode head and the tail serial connection, the 3rd described NMOS pipe group is mainly made up of two NMOS pipes, and the source electrode of two NMOS pipes and drain electrode head and the tail serial connection, the 4th described NMOS pipe group is mainly made up of two NMOS pipes, and the source electrode of two NMOS pipes and drain electrode head and the tail serial connection, the 5th described NMOS pipe group is mainly made up of four NMOS pipe, and the source electrode of four NMOS pipe and drain electrode head and the tail serial connection, the 6th described NMOS pipe group is mainly made up of two NMOS pipes, and the source electrode of two NMOS pipes and drain electrode head and the tail serial connection, the 7th described NMOS pipe group is mainly made up of three NMOS pipes, and the source electrode of three NMOS pipes and drain electrode head and the tail serial connection, the 8th described NMOS pipe group is mainly made up of three NMOS pipes, and the source electrode of three NMOS pipes and drain electrode head and the tail serial connection, the 9th described NMOS pipe group is mainly made up of two NMOS pipes, and the source electrode of two NMOS pipes and drain electrode head and the tail serial connection, the tenth described NMOS pipe group is mainly made up of two NMOS pipes, and the source electrode of two NMOS pipes and drain electrode head and the tail serial connection, the 11 described NMOS pipe group is mainly made up of three NMOS pipes,And the source electrode of three NMOS pipes and drain electrode head and the tail serial connection, the 12 described NMOS pipe group is mainly made up of three NMOS pipes, and the source electrode of three NMOS pipes and drain electrode head and the tail serial connection, described interleaved circuit unit is mainly made up of two PMOS pipes and two NMOS pipes, the source grounding of two NMOS pipes in described interleaved circuit unit, the drain electrode of first PMOS pipe in described interleaved circuit unit, the drain electrode of first NMOS pipe in described interleaved circuit unit, the grid of second PMOS pipe in described interleaved circuit unit, the grid of second NMOS pipe in described interleaved circuit unit, the source electrode of last the NMOS pipe in a described NMOS pipe group, the source electrode of last the NMOS pipe in the 2nd described NMOS pipe group, the source electrode of last the NMOS pipe in the 3rd described NMOS pipe group, the source electrode of last the NMOS pipe in the 4th described NMOS pipe group, the source electrode of last the NMOS pipe in the source electrode of last the NMOS pipe in the 5th described NMOS pipe group and the 6th described NMOS pipe group is connected to the signal output part of described tri-valued, thermal-insulating JKL basic circuit, the drain electrode of second PMOS pipe in described interleaved circuit unit, the drain electrode of second NMOS pipe in described interleaved circuit unit, the grid of first PMOS pipe in described interleaved circuit unit, the grid of first NMOS pipe in described interleaved circuit unit, the source electrode of last the NMOS pipe in the 7th described NMOS pipe group, the source electrode of last the NMOS pipe in the 8th described NMOS pipe group, the source electrode of last the NMOS pipe in the 9th described NMOS pipe group, the source electrode of last the NMOS pipe in the tenth described NMOS pipe group, the source electrode of last the NMOS pipe in the source electrode of last the NMOS pipe in the 11 described NMOS pipe group and the 12 described NMOS pipe group is connected to the complementary signal output of described tri-valued, thermal-insulating JKL basic circuit, the drain electrode of first NMOS pipe in a described NMOS pipe group, the drain electrode of first NMOS pipe in the 2nd described NMOS pipe group, the drain electrode of first NMOS pipe in the 3rd described NMOS pipe group, the drain electrode of first NMOS pipe in the 7th described NMOS pipe group, the drain electrode of first NMOS pipe in the drain electrode of first NMOS pipe in the 8th described NMOS pipe group and the 9th described NMOS pipe group is connected to the first power clock signal of the first power clock signal input part and access amplitude level counterlogic 1, the drain electrode of first NMOS pipe in the 4th described NMOS pipe group, the drain electrode of first NMOS pipe in the 5th described NMOS pipe group, the drain electrode of first NMOS pipe in the 6th described NMOS pipe group, the drain electrode of first NMOS pipe in the tenth described NMOS pipe group, the drain electrode of first NMOS pipe in the 11 described NMOS pipe group,The drain electrode of first NMOS pipe in the 12 described NMOS pipe group, the source electrode of second PMOS pipe in the source electrode of first PMOS pipe in described interleaved circuit unit and described interleaved circuit unit is connected to the second clock pulse signal of second clock pulse signal input terminal and access amplitude level counterlogic 2, the drain electrode of first NMOS pipe in described signal sample circuit, the grid of second NMOS pipe in a described NMOS pipe group is connected with the grid of last NMOS pipe in the 4th described NMOS pipe group, the drain electrode of second NMOS pipe in described signal sample circuit is connected with the grid of second NMOS pipe in described the 7th NMOS pipe group, the drain electrode of the 3rd NMOS pipe in described signal sample circuit is connected with the grid of the 3rd NMOS pipe in described the 5th NMOS pipe group, the drain electrode of the four NMOS pipe in described signal sample circuit is connected with the grid of last the NMOS pipe in described the 11 NMOS pipe group, the drain electrode of the 5th NMOS pipe in described signal sample circuit is connected with the grid of last the NMOS pipe in described the 3rd NMOS pipe group, the drain electrode of the 6th NMOS pipe in described signal sample circuit, the grid of last the NMOS pipe in the 9th described NMOS pipe group is connected with the grid of second NMOS pipe in the 12 described NMOS pipe group, the drain electrode of the 7th NMOS pipe in described signal sample circuit, the grid of first NMOS pipe in the 2nd described NMOS pipe group, the grid of first NMOS pipe in the 3rd described NMOS pipe group, the grid of first NMOS pipe in the 5th described NMOS pipe group is connected with the grid of first NMOS pipe in the 6th described NMOS pipe group, the drain electrode of the 8th NMOS pipe in described signal sample circuit, the grid of first NMOS pipe in the 8th described NMOS pipe group, the grid of first NMOS pipe in the 9th described NMOS pipe group, the grid of first NMOS pipe in the 11 described NMOS pipe group is connected with the grid of first NMOS pipe in the 12 described NMOS pipe group, the drain electrode of first NMOS pipe in described complementary signal sample circuit is connected with the grid of last the NMOS pipe in a described NMOS pipe group, the drain electrode of second NMOS pipe in described complementary signal sample circuit, the grid of last the NMOS pipe in the 7th described NMOS pipe group is connected with the grid of last the NMOS pipe in the tenth described NMOS pipe group, the drain electrode of the 3rd NMOS pipe in described complementary signal sample circuit, the grid of last the NMOS pipe in the 2nd described NMOS pipe group is connected with the grid of last the NMOS pipe in the 5th described NMOS pipe group, the drain electrode of the four NMOS pipe in described complementary signal sample circuit is connected with the grid of last the NMOS pipe in described the 8th NMOS pipe groupThe drain electrode of the 5th NMOS pipe in described complementary signal sample circuit is connected with the grid of last the NMOS pipe in described the 6th NMOS pipe group, the drain electrode of the 6th NMOS pipe in described complementary signal sample circuit is connected with the grid of last the NMOS pipe in the 12 described NMOS pipe group, the drain electrode of the 7th NMOS pipe in described complementary signal sample circuit, the grid of first NMOS pipe in a described NMOS pipe group, the grid of second NMOS pipe in the 2nd described NMOS pipe group, the grid of first NMOS pipe in the 4th described NMOS pipe group is connected with the grid of second NMOS pipe in the 5th described NMOS pipe group, the drain electrode of the 8th NMOS pipe in described complementary signal sample circuit, the grid of first NMOS pipe in the 7th described NMOS pipe group, the grid of second NMOS pipe in the 8th described NMOS pipe group, the grid of first NMOS pipe in the tenth described NMOS pipe group is connected with the grid of second NMOS pipe in the 11 described NMOS pipe group.

4. the adiabatic novenary asynchronous counter of one according to claim 3, it is characterized in that described DTCTGAL buffer is the buffer that input signal is identical with output signal, the input signal of the DTCTGAL buffer described in the output signal ratio of described DTCTGAL buffer postpones the clock cycle half.