CN102386865A - Operational amplification circuit and system - Google Patents
Operational amplification circuit and system Download PDFInfo
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- CN102386865A CN102386865A CN2011102824375A CN201110282437A CN102386865A CN 102386865 A CN102386865 A CN 102386865A CN 2011102824375 A CN2011102824375 A CN 2011102824375A CN 201110282437 A CN201110282437 A CN 201110282437A CN 102386865 A CN102386865 A CN 102386865A
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Abstract
The invention relates to an operational amplification circuit, which comprises a first input end, a second input end, a first output end, a second output end, a control circuit, an adjusting circuit connected with the control circuit and a bias circuit connected with the control circuit and the adjusting circuit; the control circuit comprises a first field effect tube, a second field effect tube, a third field effect tube, a first resistor and a second resistor; the adjusting circuit comprises a comparator, a first adjustable current source connected with the comparator, a second adjustable current source connected with the comparator and the first adjustable current source, a third resistor connected with the comparator and a fourth resistor connected with the comparator; and the bias circuit comprises a bias current source, a fifth resistor connected with the bias current, a fourth field effect tube connected with the fifth resistor and a fifth field effect tube connected with the fourth field effect tube. The invention also provides an operational amplification system. The common-mode rejection ratio is increased.
Description
Technical field
The present invention relates to a kind of operational amplifier, refer to a kind of operational amplification circuit and system especially with high cmrr of low supply voltage.
Background technology
Operational amplification circuit is to have the very circuit unit of high-amplification-factor.In order to explain that operational amplification circuit suppresses the ability of common-mode signal; Common-mode rejection ratio commonly used is weighed as a technical indicator; It is defined as amplifying circuit to the voltage amplification factor of difference mode signal and ratio to the voltage amplification factor of common-mode signal, is called common-mode rejection ratio.
The difference mode signal voltage amplification factor is big more, and the common-mode signal voltage amplification factor is more little, and then common-mode rejection ratio is high more.The ability of operational amplification circuit inhibition this moment common-mode signal is strong more, and the performance of operational amplification circuit is good more.
And in existing operational amplification circuit; In order to obtain high cmrr; The tail current of operational amplification circuit often adopts the structure of cascade; Need under high pressure work, can't therefore be necessary to provide a kind of operational amplification circuit and system at operation at low power supply voltage with high cmrr of low supply voltage.
Summary of the invention
In view of above content, be necessary to provide a kind of operational amplification circuit and system with high cmrr of low supply voltage.
A kind of operational amplification circuit; Comprise a first input end, one second input, one first output and one second output; Said operational amplification circuit comprises that also link to each other with the said control circuit regulating circuit and of the electric current that is used to regulate said control circuit of the control circuit, that links to each other with said first input end, said second input, said first output and said second output links to each other with said control circuit and said regulating circuit and is used for providing the biasing circuit of proper operation electric current to said operational amplification circuit; Said control circuit comprises second resistance that first resistance and one that the 3rd FET, that second FET, that first FET, that links to each other with said first input end links to each other with said second input links to each other with said first FET and said second FET links to each other with said first FET links to each other with said second FET; Said regulating circuit comprises the 4th resistance that the 3rd resistance and one that second adjustable current source, that first adjustable current source, that a comparator, links to each other with said comparator links to each other with said comparator and said first adjustable current source links to each other with said comparator links to each other with said comparator, and said biasing circuit comprises the 5th FET that the 4th FET and that the 5th resistance, one that a bias current sources, links to each other with said bias current sources links to each other with said the 5th resistance links to each other with said the 4th FET.
A kind of computing amplification system; Comprise a first input end, one second input, one first output and one second output, said operational amplification circuit comprises that also link to each other with the said control circuit regulating circuit and that is used to regulate the electric current of said control circuit and compensates the raceway groove mudulation effect of said computing amplification system tail current of the control circuit, that links to each other with said first input end, said second input, said first output and said second output links to each other with said control circuit and said regulating circuit and is used for providing the biasing circuit of proper operation electric current to said computing amplification system.
Relative prior art; Operational amplification circuit of the present invention and system have effectively suppressed the raceway groove mudulation effect of the tail current of operational amplification circuit and system; To guarantee that the electric current sum that when input common-mode VCM changes, flows through the electric current of this first FET M1 and flow through this second FET M2 equals to flow through the electric current of the 4th FET M4; Thereby suppressed common-mode gain, improved common-mode rejection ratio.
Description of drawings
Fig. 1 is the system block diagram of computing amplification system preferred embodiments of the present invention.
Fig. 2 is the circuit block diagram of computing amplification system preferred embodiments of the present invention.
Fig. 3 is the circuit diagram of operational amplification circuit preferred embodiments of the present invention.
Embodiment
See also Fig. 1, computing amplification system preferred embodiments of the present invention comprises that a first input end VIN+, one second input VIN-, one first output VOUT+, one second output VOUT-, are used for link to each other with this control circuit regulating circuit and of the electric current that is used to regulate this control circuit of control circuit, that the differential signal with this first input end VIN+ and this second input VIN-input amplifies and link to each other with this control circuit and this regulating circuit and be used for providing the biasing circuit of suitable operating current to this computing amplification system.The a pair of differential signal of the common reception of this first input end VIN+ and this second input VIN-, this first output VOUT+ and this second output VOUT-export a pair of differential signal after the amplification jointly.
Please consult Fig. 2 simultaneously, Fig. 2 is the circuit block diagram of computing amplification system preferred embodiments of the present invention.Wherein, This control circuit comprises one first FET M1, one second FET M2, one the 3rd FET M3, one first resistance R D1 and one second resistance R D2; This regulating circuit comprises a comparator C MP, one first adjustable current source IP, one second adjustable current source IN, one the 3rd resistance R D3 and one the 4th resistance R D4, and this biasing circuit comprises a bias current sources I1, one the 5th resistance R D5, one the 4th FET M4 and one the 5th FET M5.
The annexation of computing amplification system preferred embodiments of the present invention is following: the grid of this first FET M1 links to each other with the end of this first input end VIN+ and the 3rd resistance R D3; The drain electrode of this first FET M1 links to each other with an end and this second output VOUT-of this first resistance R D1; The grid of this second FET M2 links to each other with the end of this second input VIN-and the 4th resistance R D4, and the drain electrode of this second FET M2 links to each other with an end and this first output VOUT+ of this second resistance R D2.The end of the source class of the source class of this first FET M1, this second FET M2, the drain electrode of the 3rd FET M3, this first adjustable current source IP and the end of this second adjustable current source IN connect jointly; The grid of the 3rd FET M3 links to each other with the end of the 5th resistance R D5, the drain electrode of the 4th FET M4 and the grid of the 5th FET M5, and the source class of the 4th FET M4 links to each other with the drain electrode of the 5th FET M5.The normal phase input end of this comparator C MP links to each other with the end of this bias current sources I1, the other end of the 5th resistance R D5 and the grid of the 4th FET M4; And receive a reference voltage VREF; The inverting input of this comparator C MP links to each other with the other end of the other end of the 3rd resistance R D3 and the 4th resistance R D4; And receive the common-mode voltage VCM of other end output of the other end and the 4th resistance R D4 of the 3rd resistance R D3; The positive output end of this comparator C MP links to each other with the control end of this first adjustable current source IP; And export the control end of a voltage VN to this first adjustable current source IP, the reversed-phase output of this comparator C MP links to each other with the control end of this second adjustable current source IN, and exports the control end of a voltage VP to this second adjustable current source IN.The common power end VDD that connects of the other end of the other end of the other end of the other end of this bias current sources I1, this first resistance R D1, this second resistance R D2 and this first adjustable current source IP, the common earth terminal GND that connects of the other end of the source class of the source class of the 5th FET M5, the 3rd FET M3 and this second adjustable current source IN.
Please consult Fig. 2 and Fig. 3 simultaneously, Fig. 3 is the physical circuit figure of operational amplification circuit preferred embodiments of the present invention.Wherein, This first adjustable current source IP is one the 6th FET M6; This second adjustable current source IN is one the 7th FET M7, and this comparator C MP comprises one the 8th FET M8, one the 9th FET M9,1 the tenth FET M10,1 the 11 FET M11,1 the 12 FET M12,1 the 13 FET M13 and 1 the 14 FET M14.
The physical circuit annexation of operational amplification circuit preferred embodiments of the present invention is following: the grid of this first FET M1 links to each other with the end of this first input end VIN+ and the 3rd resistance R D3; The drain electrode of this first FET M1 links to each other with an end and this second output VOUT-of this first resistance R D1; The grid of this second FET M2 links to each other with the end of this second input VIN-and the 4th resistance R D4, and the drain electrode of this second FET M2 links to each other with an end and this first output VOUT+ of this second resistance R D2.The source class of the source class of this first FET M1, this second FET M2, the drain electrode of the 3rd FET M3, the drain electrode of the 6th FET M6 and the drain electrode of the 7th FET M7 connect jointly; The grid of the 3rd FET M3 links to each other with the end of the 5th resistance R D5, the drain electrode of the 4th FET M4, the grid of the 5th FET M5 and the grid of the 12 FET M12, and the source class of the 4th FET M4 links to each other with the drain electrode of the 5th FET M5.The grid of the 6th FET M6 links to each other with the drain electrode of grid, drain electrode and the tenth FET M10 of the 8th FET M8, and the grid of the 7th FET M7 links to each other with the drain electrode of grid, drain electrode and the 13 FET M13 of the 14 FET M14.The grid of the 9th FET M9, drain electrode link to each other with the drain electrode of the 11 FET M11 and the grid of the 13 FET M13; The grid of the tenth FET M10 links to each other with the other end of the 3rd resistance R D3 and the other end of the 4th resistance R D4; The source class of the tenth FET M10 and the source class of the 11 FET M11 are connected the drain electrode of the 12 FET M12 jointly, the common reference voltage end VREF that connects of the grid of the end of the grid of the 11 FET M11, this bias current sources I1, the other end of the 5th resistance R D5 and the 4th FET M4.The other end of the other end of the other end of this bias current sources I1, this first resistance R D1, this second resistance R D2, the source class of the 6th FET M6, the source class of the 8th FET M8, the source class of the 9th FET M9 and the source class of the 13 FET M13 connect power end VDD jointly, and the source class of the source class of the 5th FET M5, the 3rd FET M3, the source class of the 7th FET M7, the source class of the 12 FET M12 and the source class of the 14 FET M14 connect earth terminal GND jointly.
The operation principle of operational amplification circuit of the present invention and system is described below: a pair of differential signal of the common reception of this first input end VIN+ and this second input VIN-; Through after control circuit amplifies, export the differential signal after a pair of amplification by this first output VOUT+ and this second output VOUT-.In order to suppress common-mode gain; Improve common-mode rejection ratio; Make this operational amplification circuit and system works stable; When the common-mode voltage VCM that need guarantee in input differential signal changed, the electric current that flows through this first FET M1 and the electric current sum that flows through this second FET M2 equaled to flow through the electric current of the 4th FET M4.
It is identical with the breadth length ratio of the 3rd FET M3 that the 5th FET M5 at first is set; The breadth length ratio sum of this first FET M1 and this second FET M2 equals the breadth length ratio of the 4th FET M4; The grid voltage of the 5th FET M5 and the 3rd FET M3 is VB1; The drain voltage of the 3rd FET M3 is VB2, and the drain voltage of the 5th FET M5 is VB3.When common-mode voltage VCM equals reference voltage VREF; Voltage VB3 equals voltage VB2; Then flowing through the 3rd FET M3 equates with the electric current that flows through the 5th FET M5 fully; Can obtain voltage VP and equal voltage VN; The electric current that the electric current of this first adjustable current source IP in such cases equals this second adjustable current source IN is set, does not promptly have this moment extra electric current to inject the 3rd FET M3, the electric current that promptly flows through the 4th FET M4 equals to flow through the electric current and the electric current sum that flows through this second FET M2 of this first FET M1.
As common-mode voltage VCM during greater than reference voltage VREF; Voltage VB2 can follow the rising of input voltage and raise; Voltage VB2 is greater than voltage VB3; Promptly the 3rd FET M3 begins to take place the raceway groove mudulation effect, and the electric current that promptly flows through the 3rd FET M3 can change along with the variation of drain-source voltage, has more electric current and flows through the 3rd FET M3.Because common-mode voltage VCM is greater than reference voltage VREF; Behind comparator C MP; Voltage VP is less than voltage VN; When voltage VP was set less than voltage VN, the electric current of this first adjustable current source IP was greater than the electric current of this second adjustable current source IN, and promptly this first adjustable current source IP can have more one part of current and flows through the 3rd FET M3; Thereby balance out the raceway groove modulated current of the 3rd FET M3, make electric current that flows through the 4th FET M4 and the electric current that flows through this first FET M1 equate with the electric current sum that flows through this second FET M2.
As common-mode voltage VCM during less than reference voltage VREF; Voltage VB2 can follow the decline of input voltage and descend; Voltage VB2 is less than voltage VB3, and promptly the 3rd FET M3 begins to take place the raceway groove mudulation effect, promptly flows through corresponding the reducing of electric current meeting of the 3rd FET M3; Because common-mode voltage VCM is less than reference voltage VREF; Behind comparator C MP, voltage VP is greater than voltage VN, when voltage VP is set greater than voltage VN; The electric current of this first adjustable current source IP is less than the electric current of this second adjustable current source IN; Promptly this second adjustable current source IN can have more one part of current and flows through this first FET M1 and this second FET M2, thereby compensates the raceway groove modulated current of the 3rd FET M3, makes electric current that flows through the 4th FET M4 and the electric current that flows through this first FET M1 equate with the electric current sum that flows through this second FET M2.
Suppose △ V=VCM-VREF, △ I=IP-IN, the gain of this comparator C MP is Av, voltage VP controls the coefficient of the first adjustable current source IP and coefficient that voltage VN controls the second adjustable current source IN is gm, then has:
VN―VP=Av*（VCM―VREF）=Av*△V；
Again because △ I=IP-IN=gm* (VN-VP)=Av* △ V*gm;
The 3rd FET M3 must have △ I=△ I ', that is: because current increment △ I '=λ * (VB2-VB1) * I1 that the raceway groove mudulation effect produces will make compensating effect best
Av*△V*gm=λ*（VB2―VB1）*I1?（1）
Because △ V=VCM-VREF=VB2-VB1, then expression formula (1) can be written as:
Av*gm=λ*I1 （2）
Wherein λ is the raceway groove index of modulation, because the value of λ and bias current sources I1 determines by physical circuit, so only need the gain A v of adjusting comparator C MP and Current Control coefficient gm can make expression formula (2) establishment.
If expression formula (2) is set up, then can know for operational amplification circuit and system whenever flow through the electric current that the P shown in Fig. 2 order and all remain unchanged, i.e. the P equivalent resistance infinity of order is owing to common-mode gain
ACM=（RD）/((1/gm)+2*RP) （3）
RD=RD1=RD2 wherein, RP is the equivalent resistance that P is ordered, because RP → ∞, ACM → 0 then, i.e. the common-mode gain of computing amplification system is about 0;
Because ACMRR=is ADM/ACM, wherein ACMRR representes common-mode rejection ratio, and ADM representes difference mode gain, can know that then ACMRR has been improved greatly.
Operational amplification circuit of the present invention and system have effectively suppressed the raceway groove mudulation effect of the tail current of operational amplification circuit and system; To guarantee that the electric current sum that when input common-mode VCM changes, flows through the electric current of this first FET M1 and flow through this second FET M2 equals to flow through the electric current of the 4th FET M4; Thereby the inhibition common-mode gain improves common-mode rejection ratio; And under the situation of not using cascade, improved common-mode rejection ratio greatly, thereby saved the voltage remaining, made it can be at operation at low power supply voltage.
Claims (10)
1. operational amplification circuit; Comprise a first input end, one second input, one first output and one second output; It is characterized in that: said operational amplification circuit comprises that also link to each other with the said control circuit regulating circuit and of the electric current that is used to regulate said control circuit of the control circuit, that links to each other with said first input end, said second input, said first output and said second output links to each other with said control circuit and said regulating circuit and is used for providing the biasing circuit of proper operation electric current to said operational amplification circuit; Said control circuit comprises second resistance that first resistance and one that the 3rd FET, that second FET, that first FET, that links to each other with said first input end links to each other with said second input links to each other with said first FET and said second FET links to each other with said first FET links to each other with said second FET; Said regulating circuit comprises the 4th resistance that the 3rd resistance and one that second adjustable current source, that first adjustable current source, that a comparator, links to each other with said comparator links to each other with said comparator and said first adjustable current source links to each other with said comparator links to each other with said comparator, and said biasing circuit comprises the 5th FET that the 4th FET and that the 5th resistance, one that a bias current sources, links to each other with said bias current sources links to each other with said the 5th resistance links to each other with said the 4th FET.
2. operational amplification circuit as claimed in claim 1; It is characterized in that: said first adjustable current source is one the 6th FET; Said second adjustable current source is one the 7th FET, and said comparator comprises the 14 FET that the 13 FET and that the 12 FET, that the 11 FET, that the tenth FET, that one the 8th FET, one the 9th FET, link to each other with said the 8th FET links to each other with said the 9th FET links to each other with said the tenth FET and said the 11 FET links to each other with said the 9th FET links to each other with said the 13 FET.
3. operational amplification circuit as claimed in claim 2; It is characterized in that: the grid of said first FET links to each other with an end of said first input end and said the 3rd resistance; The drain electrode of said first FET links to each other with an end and said second output of said first resistance; The grid of said second FET links to each other with an end of said second input and said the 4th resistance, and the drain electrode of said second FET links to each other with an end and said first output of said second resistance.
4. operational amplification circuit as claimed in claim 3; It is characterized in that: the drain electrode of the source class of the source class of said first FET, said second FET, the drain electrode of said the 3rd FET, said the 6th FET and the drain electrode of said the 7th FET connect jointly; The grid of said the 3rd FET links to each other with the grid of the drain electrode of an end of said the 5th resistance, said the 4th FET, said the 5th FET and the grid of said the 12 FET; The source class of said the 4th FET links to each other with the drain electrode of said the 5th FET; The grid of said the 6th FET links to each other with the drain electrode of grid, drain electrode and said the tenth FET of said the 8th FET, and the grid of said the 7th FET links to each other with the drain electrode of grid, drain electrode and said the 13 FET of said the 14 FET.
5. operational amplification circuit as claimed in claim 4; It is characterized in that: the grid of said the 9th FET, drain electrode link to each other with the drain electrode of said the 11 FET and the grid of said the 13 FET; The grid of said the tenth FET links to each other with the other end of said the 3rd resistance and the other end of said the 4th resistance; The source class of said the tenth FET and the source class of said the 11 FET are connected the drain electrode of said the 12 FET jointly, the common reference voltage end that connects of the grid of an end of the grid of said the 11 FET, said bias current sources, the other end of said the 5th resistance and said the 4th FET.
6. operational amplification circuit as claimed in claim 5; It is characterized in that: the common power end that connects of the source class of the other end of the other end of said bias current sources, said first resistance, the other end of said second resistance, the source class of said the 6th FET, the source class of said the 8th FET, said the 9th FET and the source class of said the 13 FET, the common earth terminal that connects of the source class of the source class of the source class of said the 5th FET, said the 3rd FET, the source class of said the 7th FET, said the 12 FET and the source class of said the 14 FET.
7. computing amplification system; Comprise a first input end, one second input, one first output and one second output, it is characterized in that: said operational amplification circuit comprises that also link to each other with the said control circuit regulating circuit and that is used to regulate the electric current of said control circuit and compensates the raceway groove mudulation effect of said computing amplification system tail current of the control circuit, that links to each other with said first input end, said second input, said first output and said second output links to each other with said control circuit and said regulating circuit and is used for providing the biasing circuit of proper operation electric current to said computing amplification system.
8. computing amplification system as claimed in claim 7; It is characterized in that: said control circuit comprises second resistance that first resistance and one that the 3rd FET, that second FET, that first FET, that links to each other with said first input end links to each other with said second input links to each other with said first FET and said second FET links to each other with said first FET links to each other with said second FET; Said regulating circuit comprises the 4th resistance that the 3rd resistance and one that second adjustable current source, that first adjustable current source, that a comparator, links to each other with said comparator links to each other with said comparator and said first adjustable current source links to each other with said comparator links to each other with said comparator, and said biasing circuit comprises the 5th FET that the 4th FET and that the 5th resistance, one that a bias current sources, links to each other with said bias current sources links to each other with said the 5th resistance links to each other with said the 4th FET.
9. computing amplification system as claimed in claim 8; It is characterized in that: the grid of said first FET links to each other with an end of said first input end and said the 3rd resistance; The drain electrode of said first FET links to each other with an end and said second output of said first resistance; The grid of said second FET links to each other with an end of said second input and said the 4th resistance; The drain electrode of said second FET links to each other with an end and said first output of said second resistance; One end of the drain electrode of the source class of the source class of said first FET, said second FET, said the 3rd FET, said first adjustable current source and an end of said second adjustable current source connect jointly; The grid of said the 3rd FET links to each other with the drain electrode of an end of said the 5th resistance, said the 4th FET and the grid of said the 5th FET, and the source class of said the 4th FET links to each other with the drain electrode of said the 5th FET.
10. computing amplification system as claimed in claim 9; It is characterized in that: a normal phase input end of said comparator links to each other with the other end of an end of said bias current sources, said the 5th resistance and the grid of said the 4th FET; One inverting input of said comparator links to each other with the other end of the other end of said the 3rd resistance and said the 4th resistance; One positive output end of said comparator links to each other with a control end of said first adjustable current source, and a reversed-phase output of said comparator links to each other with a control end of said second adjustable current source.
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| CN105075125B (en) * | 2013-03-15 | 2017-03-22 | 高通股份有限公司 | Techniques to reduce harmonic distortions of impedance attenuators for low-power wideband high-resolution DACs |
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