CN102386848B - Annular voltage-controlled oscillator - Google Patents
Annular voltage-controlled oscillator Download PDFInfo
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- CN102386848B CN102386848B CN201110281541.2A CN201110281541A CN102386848B CN 102386848 B CN102386848 B CN 102386848B CN 201110281541 A CN201110281541 A CN 201110281541A CN 102386848 B CN102386848 B CN 102386848B
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Abstract
The invention discloses an annular voltage-controlled oscillator, which comprises a reference voltage source, a voltage stabilizing circuit, a compensation circuit and an oscillation circuit; the output of the reference voltage source is connected with the input end of the voltage stabilizing circuit; the voltage stabilizing circuit generates two output voltages, and the first output is used as a working voltage of the oscillation circuit while the second output is input to the compensation circuit as an input voltage of the compensation circuit; and the output of the compensation circuit is used as a bias voltage of the oscillation circuit. The oscillator controls the oscillation frequency of the oscillation circuit by generating a bias voltage changed along the temperature and the technology to realize automatic compensation of output frequency deviation of the oscillator. When temperature rise results in frequency increment of the oscillation circuit, the compensation circuit generates a control voltage reduced along the temperature so as to compensate drop of frequency; and when a process corner is changed from SS (Slow nmos and Slow pmos) to FF (Fast nmos and Fast pmos), the oscillation circuit also has a rise and the compensation circuit generates a control voltage reduced along the technology so as to compensate drop of frequency.
Description
Technical field
The invention belongs to integrated circuit (IC) design technical field, be specifically related to a kind of annular voltage controlled oscillator with temperature and technique self-compensating function.
Background technology
Oscillator is the main modular of many electronic systems, and the clock generating of range of application from microprocessor is synthetic to the carrier wave in wireless communication system.The most general oscillator is quartz oscillator, and the performance of crystal oscillator is very stable, and precision is very high, but it can not be integrated in chip system inside.Utilize the CMOS technique of standard to realize oscillator on sheet and replace the crystal oscillator outside sheet, for the cost that reduces system, improve the integrated level of system by helpful.
Along with the development of semiconductor process techniques, the integrated level of chip is also more and more higher, thereby has caused the rapid rising of power consumption, and power problems becomes the critical limitation factor that modern large scale integrated circuit is realized just day by day.The numerous characteristics of MOS transistor all changes with temperature in addition, and in chip manufacturing proces, and between different wafers and different batches, transistorized parameter alters a great deal.Therefore, realize the challenge that on sheet, oscillator mainly faces and be mainly manifested in two aspects: the one, low-power consumption, the power consumption of oscillator module should be as far as possible little, to reduce the power consumption of whole chip; The 2nd, high accuracy, frequency of oscillation keeps high stability for the variation of supply voltage, temperature and technique.
Existing upper oscillator mainly contains following several.
(1) pursue the low-power consumption of circuit, and adopted the simple pierce circuit of structure.This oscillator be subject to temperature and technogenic influence larger, the system that frequency accuracy is had relatively high expectations is difficult to meet the demands.
(2) with the pierce circuit of digital circuit calibration function.In order to obtain high-precision frequency of oscillation, in oscillator, add digital circuit calibration module to calibrate frequency of oscillation deviation, but this mode has increased the complexity of design and the power consumption of circuit greatly, be not suitable for being used in the low-power consumption of chip is required in strict system, for example, as the ultrahigh frequency electronic tag of Internet of things node.
(3) oscillator with temperature compensation effect based on band-gap reference.This oscillator adopts the variation of the good bipolar transistor sense temperature of the temperature coefficient linearity, but sort circuit structure power consumption is larger, and bad with standard CMOS process compatibility.In addition, this structure can not compensate technique change, and the frequency departure causing because of technique is also quite large.
Due to the problems referred to above that existing upper pierce circuit exists, therefore can not be used in the system that low-power consumption, low cost, high accuracy and integrated level are all had higher requirements.
Summary of the invention
The object of the invention is to be subject to temperature and the larger problem of technogenic influence in order to solve existing pierce circuit, proposed a kind of annular voltage controlled oscillator.
Technical scheme of the present invention is: a kind of annular voltage controlled oscillator, comprising: reference voltage source, voltage stabilizing circuit, compensating circuit and oscillating circuit, and described reference voltage source output is connected with the input of described voltage stabilizing circuit; Described voltage stabilizing circuit amplifies reference voltage in proportion, produces two output voltage, and the first output is as the operating voltage of oscillating circuit, and second is input to the compensating circuit input voltage of circuit by way of compensation; The output of described compensating circuit is connected with oscillating circuit, and the output of compensating circuit is as the bias voltage of oscillating circuit, and the output of oscillating circuit is the output of described annular voltage controlled oscillator.
The invention has the beneficial effects as follows: annular voltage controlled oscillator of the present invention is controlled the frequency of oscillation of oscillating circuit by producing a bias voltage with temperature and technique change, realize the output frequency deviation of auto-compensation oscillator.In the time that temperature rising causes the frequency of oscillating circuit to raise, compensating circuit produces a bias voltage reducing with temperature, and the frequency of oscillating circuit is declined, thereby reaches the object of compensating frequency, the i.e. decline of compensating frequency; In the time that process corner changes from SS to FF, the frequency of oscillating circuit also raises, and compensating circuit produces a bias voltage reducing with above-mentioned technique change trend, and the frequency of oscillating circuit is declined, thereby also can reach the object of compensating frequency, i.e. the decline of compensating frequency.So, can ensure that output frequency is consistent under different temperatures and process conditions.
Brief description of the drawings
Fig. 1 is annular voltage controlled oscillator structured flowchart of the present invention.
Fig. 2 is the schematic diagram of the reference voltage source of the embodiment of the present invention.
Fig. 3 is the schematic diagram of the voltage stabilizing circuit of the embodiment of the present invention.
Fig. 4 is the schematic diagram of the compensating circuit of the embodiment of the present invention.
Fig. 5 is the schematic diagram of the oscillating circuit of the embodiment of the present invention.
Embodiment
Below in conjunction with drawings and Examples, the present invention is elaborated.
The annular voltage controlled oscillator structured flowchart that the present invention proposes as shown in Figure 1, specifically comprises reference voltage source, voltage stabilizing circuit, compensating circuit and oscillating circuit.Described reference voltage source output is connected with the input of described voltage stabilizing circuit; Described voltage stabilizing circuit amplifies reference voltage in proportion, produces two output voltage, and the first output is as the operating voltage of oscillating circuit, and second is input to the compensating circuit input voltage of circuit by way of compensation; The output of described compensating circuit is connected with oscillating circuit, and the output of compensating circuit is as the bias voltage of oscillating circuit, and the output of oscillating circuit is the output of described annular voltage controlled oscillator.
Wherein, reference voltage source road produce one irrelevant with supply voltage and temperature, and with the reference voltage V of technique change
ref; Voltage stabilizing circuit is by reference voltage V
refamplify in proportion, produce two output voltage, a road V
ddas the operating voltage of oscillating circuit, another road V
pbe input to compensating circuit; Compensating circuit produces a bias voltage V
ctrlthe output frequency of controlling oscillating circuit, bias voltage and frequency of oscillation are positive correlations, in the time that temperature rising causes frequency of oscillation to raise, compensating circuit produces a bias voltage reducing with temperature, thus the decline of compensating frequency; In the time that process corner changes from SS to FF, frequency of oscillation also raises, and compensating circuit produces a bias voltage reducing with above-mentioned technique change trend, thus the decline of compensating frequency.So, can ensure that output frequency is consistent under different temperatures and process conditions.
Fig. 2 is a kind of mode that reference voltage source is implemented.Owing to containing bipolar device in traditional band gap reference, output reference voltage high (in 1.25V left and right), power consumption is large, therefore be not suitable for being used in the CMOS integrated circuit of low-voltage and low-power dissipation, therefore the present invention adopts CMOS reference source circuit, comprise start-up circuit, reference current generating circuit, reference voltage generating circuit, the input of start-up circuit is the output V of CMOS a reference source
ref, the output of start-up circuit is connected to the input of reference current generating circuit, the input of the output termination reference voltage generating circuit of reference current generating circuit, by current mirror by reference current I
0be mirrored to reference voltage generating circuit, reference voltage generating circuit output and supply voltage V
ccwith the irrelevant reference voltage V of temperature
ref.In Fig. 2, all PMOS pipe substrates all meet external power source V
cc, the equal ground connection of all NMOS pipe substrates.
Start-up circuit comprises PMOS pipe MP1, MP2 and NMOS pipe MN1, MN2, and wherein, the drain electrode of the source electrode of PMOS pipe MP1 and NMOS pipe MN2 meets external power source V
ccthe grid of PMOS pipe MP1 is connected with drain electrode and is connected with the source electrode of PMOS pipe MP2, the grid of PMOS pipe MP2 is connected as the input of start-up circuit with the grid of NMOS pipe MN1, the drain electrode of PMOS pipe MP2 is connected with the drain electrode of NMOS pipe MN1 and is connected to the grid of NMOS pipe MN2, and NMOS manages the source electrode of MN2 as the output of start-up circuit.Owing to there are two stable states in reference current source circuit, one is zero current condition, and one is the operating state of wishing, the function of start-up circuit is to make circuit break away from nought state and enters into the operating state of hope.When in zero current condition, output reference voltage V
reffor low-voltage, to manage by PMOS after the inverter of MP2 and NMOS pipe MN1 formation, generation high voltage is input to the grid of NMOS pipe MN2, makes NMOS pipe MN2 conducting, and output HIGH voltage, to reference current generating circuit, works on power circuit.
Reference current generating circuit comprises that PMOS pipe MP3, MP4, NMOS manage MN3, MN4, MN5 and amplifier OPA1, wherein, the grid of PMOS pipe MP3 and MP4 is connected as the output of reference current generating circuit, link together with the output of amplifier OPA1, source electrode and the external power source V of PMOS pipe MP3 and MP4
ccbe connected, the drain electrode of PMOS pipe MP3 is connected as the input of reference current generating circuit with the drain electrode of NMOS pipe MN3, and be connected to the negative input end of amplifier OPA1, the drain electrode of PMOS pipe MP4 is connected with the drain electrode of NMOS pipe MN4 and is connected to the positive input terminal of amplifier OPA1, the grid of NMOS pipe MN3 and MN4 is connected, and the grid of NMOS pipe MN3 is connected with drain electrode, source ground, the source electrode of NMOS pipe MN4 is connected to the drain electrode of NMOS pipe MN5, and the grid of MNOS pipe MN5 is connected to reference voltage V
ref, source ground.
Amplifier OPA1 forces to make the drain voltage of PMOS pipe MP3 and MP4 to equate, thereby in reference voltage generating circuit, the electric current of two branch roads equates, is made as I
0.NMOS pipe MN3 and MN4 work in sub-threshold region, and NMOS pipe MN5 works in dark linear zone, is equivalent to a resistance, is made as R
0.So, obtain a reference current
Wherein n is the sub-threshold slope factor, V
tfor thermal voltage,
k is Boltzmann constant, and T is absolute temperature, and q is the quantity of electric charge of an electronics, and W/L represents the breadth length ratio of metal-oxide-semiconductor.Visible, I
0be to be independent of supply voltage, be directly proportional to absolute temperature.
Reference voltage generating circuit comprises PMOS pipe MP5, MP6, MP7, NMOS pipe MN6, MN7, MN8, MN9, MN10 and capacitor C 1, and wherein, the source electrode of PMOS pipe MP5, MP6, MP7 is all connected to external power source V
cc, grid all links together as the input of reference voltage generating circuit, and drain electrode is connected respectively with the drain electrode of NMOS pipe MN6, MN8, MN10 respectively, the wherein drain electrode output reference voltage V of PMOS pipe MP7
refand be connected to ground by capacitor C 1, NMOS pipe MN6, MN8, MN10 grid and drain electrode separately link together, the source electrode of NMOS pipe MN6 is connected with the source electrode of NMOS pipe MN9 with the drain electrode of NMOS pipe MN7, the source electrode of NMOS pipe MN8 is connected with the source electrode of NMOS pipe MN10 with the drain electrode of NMOS pipe MN9, the grid of NMOS pipe MN7 is connected with the grid of NMOS pipe MN6, source ground, and the grid of NMOS pipe MN9 is connected with the grid of NMOS pipe MN8.
PMOS pipe MP5, MP6, MP7 are identical, thereby mirror image goes out 3 identical electric currents, and NMOS pipe MN6, MN7, MN8, MN9, MN10 all work in sub-threshold region, and its gate source voltage is respectively V
gS6, V
gS7, V
gS8, V
gS9, V
gS10s, output reference voltage is
V
tH0that absolute temperature is the threshold voltage of 0 o'clock metal-oxide-semiconductor, I
d0be subthreshold value characteristic current, κ is the temperature coefficient of metal-oxide-semiconductor threshold voltage, can make the part in above-mentioned bracket equal 0 by the breadth length ratio of determining metal-oxide-semiconductor MP4, MP5, MN6, MN7, MN8, MN9, MN10, thereby obtain V
ref=V
tH0.V
tH0irrelevant with supply voltage and temperature, and be subject to the impact of technique change, in the time that process corner changes from SS to FF, V
tH0reduce, obtained thus with supply voltage and temperature irrelevant and with the reference voltage V of technique change
ref.
Fig. 3 is a kind of execution mode of voltage stabilizing circuit.Voltage stabilizing circuit comprises PMOS pipe MP8, MP9, MP10, MP11, MP12, MP13, MP14, MP15, amplifier OPA2, OPA3 and capacitor C 2, C3, and wherein the negative input end of amplifier OPA2 and OPA3 links together as the input V of voltage stabilizing circuit
refthe positive input terminal of amplifier OPA2 and OPA3 is connected with the grid of PMOS pipe MP9 and MP14 respectively, the output of amplifier OPA2 and OPA3 is connected with the grid of PMOS pipe MP8 and MP12 respectively, the substrate of PMOS pipe MP8, MP9, MP10, MP11, MP12, MP13, MP14, MP15 is all connected to source electrode separately, the grid separately of PMOS pipe MP9, MP10, MP11, MP13, MP14, MP15 is connected and forms MOS diode with drain electrode, and the source electrode of PMOS pipe MP8 and MP12 is all connected to external power source V
ccthe corresponding source electrode that connects PMOS pipe MP9, MP10, MP11, MP13, MP14, MP15 of drain electrode of PMOS pipe MP8, MP9, MP10, MP12, MP13, MP14, the grounded drain of PMOS pipe MP11 and MP15, the drain electrode of PMOS pipe MP8 and MP12 is respectively as the first output V of voltage stabilizing circuit
ddwith the second output V
p, and be connected to ground by capacitor C 2 and C3 respectively.
Can be seen by Fig. 3, voltage stabilizing circuit is made up of two essentially identical branch roads of circuit structure, to produce output voltage V
ddbranch road be the operation principle of example explanation circuit: metal-oxide-semiconductor MP9, MP10, the mutual bleeder circuit in series of MP11, by output voltage V
ddbe divided into some parts, the negative input end of amplifier OPA2 is connected to the grid of one of them metal-oxide-semiconductor, forces it to equal amplifier positive input terminal voltage V
ref, because metal-oxide-semiconductor used is identical, offset the impact of temperature and technique change, thereby reached reference voltage V
refthe effect of amplifying in proportion.Those of ordinary skill in the art is to be appreciated that, Fig. 3 is an example of this voltage regulator circuit structure, in actual applications, the position that the quantity of the metal-oxide-semiconductor of series connection and amplifier negative input end connect should determine according to the size of the voltage stabilizing output voltage of required generation.
Fig. 4 is a kind of execution mode of compensating circuit, comprises that resistance R 1, resistance R 2, NMOS manage MN11, wherein, and the input V that one end of resistance R 1 is compensating circuit
p, the output V that the other end is compensating circuit
ctrl, the grid and the output V that drains and be connected and be connected to compensating circuit by resistance R 2 of NMOS pipe MN11
ctrl, substrate and the source ground of NMOS pipe MN11.The output voltage V of compensating circuit
ctrlas the bias voltage of oscillating circuit, be the main factor that determines frequency of oscillation, V
ctrlcenter voltage ensure that oscillating circuit produces required frequency of oscillation, on the other hand, therein electrocardio press near, V
ctrlneed have variation among a small circle with temperature and technique, thereby the output frequency of compensation oscillating circuit is with the variation of temperature and technique.Both temperature influences of the characteristic of metal-oxide-semiconductor, are subject to again technogenic influence, and the resistance of resistance is mainly subject to the impact of technique change.In compensating circuit, NMOS pipe MN11 and resistance R 1, R2 form bleeder circuit, and NMOS pipe mainly plays temperature-compensating, and resistance R 1, R2 have determined V by dividing potential drop
ctrlcenter voltage (under normal temperature and typical process angle, the output voltage of compensating circuit is V
ctrlcenter voltage).As previously mentioned, reference voltage source produce one irrelevant with supply voltage and temperature, and with the reference voltage V of technique change
ref, the V obtaining after voltage stabilizing circuit amplifies in proportion
palso irrelevant and with technique change with supply voltage and temperature, V
pact on compensating circuit to realize technological compensa tion.In the time that temperature raises, the threshold voltage of metal-oxide-semiconductor reduces, and resistance variation with temperature is very little, can ignore, like this obtain the output voltage V with temperature reduction
ctrl; In the time that process corner changes from SS to FF, the threshold voltage of metal-oxide-semiconductor reduces, and its equivalent resistance reduces, and the resistance of resistance also reduces, and the dividing potential drop in compensating circuit is close like constant, thereby by input V
poperational characteristic be delivered to output V
ctrl, obtain the bias voltage V reducing with above-mentioned technique change trend
ctrl.
Fig. 5 is a kind of execution mode of oscillating circuit, comprises bias current generating circuit, vibration core circuit and pulse shaper.Bias voltage V
ctrlas the input of bias current generating circuit, the temperature of voltage and operational characteristic are converted into the characteristic of bias current, by current mirror, bias current is mirrored to vibration core circuit, control the time of delay of oscillator delay cell, thereby determine the frequency of oscillator, the waveform V that pulse shaper produces vibration core circuit
oscshaping, exports regular Periodic Rectangular square wave V
out.
Bias current generating circuit is a common-source amplifier with source negative feedback resistance, input voltage is converted into output current, negative feedback resistor has improved the linearity of amplifier, make temperature and the operational characteristic of output current milder, when temperature raises or process corner while changing from SS to FF, bias current all reduces.Bias current generating circuit comprises PMOS pipe MP16, NMOS pipe M12 and resistance R 3.The NMOS pipe grid of MN12 and the output V of compensating circuit
ctrlbe connected, the substrate ground connection of NMOS pipe MN12, source electrode is by resistance R 3 ground connection, and drain electrode is connected with the drain electrode of PMOS pipe MP16, and source electrode and the substrate of PMOS pipe MP16 are all connected to operating voltage V
dd, the grid of PMOS pipe MP16 is as the output of bias current generating circuit.
Vibration core circuit is made up of the end to end delay cell of N level, delay cell can be single-ended, also can be difference form, for single-ended delay cell, its progression N is more than or equal to 3 odd number, for the delay cell of difference form, progression N is more than or equal to 2 arbitrary integer, the progression of delay cell should determine depending on the size of the frequency of oscillation that will produce, and the current source being come by bias current generating circuit mirror image is as the size of the load control lag time of delay cell.
As a simple and effective example, in Fig. 5, demonstrate the vibration core circuit of 3 grades of single-ended format, comprise PMOS transistor MP17, MP18, MP19, inverter INV1, INV2, INV3, substrate and the source electrode of PMOS transistor MP17, MP18, MP19 are all connected to operating voltage V
ddgrid all links together as the input of vibration core circuit, and be connected with the output of biasing circuit generation circuit, the drain electrode of PMOS transistor MP17, MP18, MP19 is the corresponding operating voltage as inverter INV1, INV2, INV3 respectively, inverter INV1, INV2, the INV3 formation ring-type that joins end to end, inverter INV3 output waveform V
osc.In the situation that bias current is constant, when temperature raises, the frequency of oscillation of ring oscillator raises, when process corner changes from SS to FF, frequency of oscillation also raises, and the bias current producing reduces with the trend of said temperature and technique change, and bias current and output frequency are linear positive relations, therefore the temperature of bias current and operational characteristic can compensate frequency of oscillation, obtain stable output frequency.
The effect of pulse shaper is that waveform is shaped as to regular cycle square wave, and a scheme the simplest is to adopt one-level inverter.As shown in Figure 5, the input of inverter INV4 is connected with the output of inverter INV3, i.e. inverter INV4 input waveform V
osc, after shaping, export regular recurrent pulse square wave v
out, be the output of oscillating circuit, that is to say the output of annular voltage controlled oscillator.
The present invention utilizes temperature and the operational characteristic of cmos device, design a kind of annular voltage controlled oscillator can automatic frequency aligning rate deviation compensating, at different temperature and process conditions, frequency of oscillation keeps higher stability, circuit power consumption is low, compatibility standard CMOS technique, in the electronic system that is suitable for power consumption, cost and frequency accuracy all to have higher requirements.Pierce circuit of the present invention only comprises NMOS, PMOS, resistance, four kinds of devices of electric capacity, have simple in structure, in CMOS processing line, realize convenient, effectively, compatible good advantage.
Those of ordinary skill in the art will appreciate that, embodiment described here is in order to help reader understanding's principle of the present invention, should be understood to that protection scope of the present invention is not limited to such special statement and embodiment.Those of ordinary skill in the art can make various other various concrete distortion and combinations that do not depart from essence of the present invention according to these technology enlightenments disclosed by the invention, and these distortion and combination are still in protection scope of the present invention.
Claims (2)
1. an annular voltage controlled oscillator, is characterized in that, comprising: reference voltage source, voltage stabilizing circuit, compensating circuit and oscillating circuit, and described reference voltage source output is connected with the input of described voltage stabilizing circuit; Described voltage stabilizing circuit amplifies reference voltage in proportion, produces two output voltage, and the first output is as the operating voltage of oscillating circuit, and second is input to the compensating circuit input voltage of circuit by way of compensation; The output of described compensating circuit is connected with oscillating circuit, and the output of compensating circuit is as the bias voltage of oscillating circuit, and the output of oscillating circuit is the output of described annular voltage controlled oscillator;
Described reference voltage source comprises start-up circuit, reference current generating circuit and reference voltage generating circuit, the input of start-up circuit is the output of reference voltage source, the output of start-up circuit is connected to the input of reference current generating circuit, the input of the output termination reference voltage generating circuit of reference current generating circuit, reference voltage generating circuit output is the output of reference voltage source, wherein
Described start-up circuit comprises PMOS pipe MP1, MP2 and NMOS pipe MN1, MN2, wherein, the drain electrode of the source electrode of PMOS pipe MP1 and NMOS pipe MN2 connects external power source, the grid of PMOS pipe MP1 is connected with drain electrode and is connected with the source electrode of PMOS pipe MP2, the grid of PMOS pipe MP2 is connected as the input of start-up circuit with the grid of NMOS pipe MN1, the drain electrode of PMOS pipe MP2 is connected with the drain electrode of NMOS pipe MN1 and is connected to the grid of NMOS pipe MN2, and NMOS manages the source electrode of MN2 as the output of start-up circuit;
Described reference current generating circuit comprises PMOS pipe MP3, MP4, NMOS manages MN3, MN4, MN5 and amplifier OPA1, wherein, the grid of PMOS pipe MP3 and MP4 is connected as the output of reference current generating circuit, link together with the output of amplifier OPA1, the source electrode of PMOS pipe MP3 and MP4 is connected with external power source, the drain electrode of PMOS pipe MP3 is connected as the input of reference current generating circuit with the drain electrode of NMOS pipe MN3, and be connected to the negative input end of amplifier OPA1, the drain electrode of PMOS pipe MP4 is connected with the drain electrode of NMOS pipe MN4 and is connected to the positive input terminal of amplifier OPA1, the grid of NMOS pipe MN3 and MN4 is connected, the grid of NMOS pipe MN3 is connected with drain electrode, source ground, the source electrode of NMOS pipe MN4 is connected to the drain electrode of NMOS pipe MN5, the grid of MNOS pipe MN5 is connected to the output of reference voltage source, source ground,
Described reference voltage generating circuit comprises PMOS pipe MP5, MP6, MP7, NMOS manages MN6, MN7, MN8, MN9, MN10 and capacitor C 1, wherein, PMOS manages MP5, MP6, the source electrode of MP7 is all connected to external power source, grid all links together as the input of reference voltage generating circuit, drain electrode is corresponding manages MN6 with NMOS, MN8, the drain electrode of MN10 is connected respectively, the wherein drain electrode output reference voltage of PMOS pipe MP7, and be connected to ground by capacitor C 1, NMOS manages MN6, MN8, MN10 grid and drain electrode separately links together, the source electrode of NMOS pipe MN6 is connected with the source electrode of NMOS pipe MN9 with the drain electrode of NMOS pipe MN7, the source electrode of NMOS pipe MN8 is connected with the source electrode of NMOS pipe MN10 with the drain electrode of NMOS pipe MN9, the grid of NMOS pipe MN7 is connected with the grid of NMOS pipe MN6, source ground, the grid of NMOS pipe MN9 is connected with the grid of NMOS pipe MN8,
Described voltage stabilizing circuit comprises PMOS pipe MP8, MP9, MP10, MP11, MP12, MP13, MP14, MP15, amplifier OPA2, OPA3 and capacitor C 2, C3, wherein the negative input end of amplifier OPA2 and OPA3 links together as the input of voltage stabilizing circuit, the positive input terminal of amplifier OPA2 and OPA3 is corresponding to be respectively connected with the grid of PMOS pipe MP9 and MP14, the output of amplifier OPA2 and OPA3 is corresponding to be respectively connected with the grid of PMOS pipe MP8 and MP12, and PMOS manages MP8, MP9, MP10, MP11, MP12, MP13, MP14, the substrate of MP15 is all connected to source electrode separately, and PMOS manages MP9, MP10, MP11, MP13, MP14, the grid separately of MP15 is connected and forms MOS diode with drain electrode, and the source electrode of PMOS pipe MP8 and MP12 is all connected to external power source, and PMOS manages MP8, MP9, MP10, MP12, MP13, the corresponding PMOS pipe MP9 that connects of drain electrode of MP14, MP10, MP11, MP13, MP14, the source electrode of MP15, the grounded drain of PMOS pipe MP11 and MP15, the drain electrode of PMOS pipe MP8 and MP12 is respectively as the first output and second output of voltage stabilizing circuit, and is connected to ground by capacitor C 2 and C3 respectively,
Described compensating circuit comprises that resistance R 1, resistance R 2, NMOS manage M11, wherein, one end of resistance R 1 the by way of compensation input of circuit and the second output of voltage stabilizing circuit is connected, the other end is as the output that is compensating circuit, the grid and the output that drains and be connected and be connected to compensating circuit by resistance R 2 of NMOS pipe MN11, substrate and the source ground of NMOS pipe MN11.
2. annular voltage controlled oscillator according to claim 1, is characterized in that, described oscillating circuit comprises bias current generating circuit, vibration core circuit and pulse shaper, wherein,
Described bias current generating circuit comprises PMOS pipe MP16, NMOS pipe M12 and resistance R 3, the NMOS pipe grid of MN12 and the output of compensating circuit are connected, the substrate ground connection of NMOS pipe MN12, source electrode is by resistance R 3 ground connection, drain electrode is connected with the drain electrode of PMOS pipe MP16, the source electrode of PMOS pipe MP16 and substrate are all connected to the first output of voltage stabilizing circuit, and the grid of PMOS pipe MP16 is as the output of bias current generating circuit;
Described vibration core circuit comprises PMOS transistor MP17, MP18, MP19, inverter INV1, INV2, INV3, PMOS transistor MP17, MP18, the substrate of MP19 and source electrode are all connected to the first output of voltage stabilizing circuit, grid all links together as the input of vibration core circuit, and be connected with the output of biasing circuit generation circuit, PMOS transistor MP17, MP18, the drain electrode of MP19 is corresponding to inverter INV1 respectively, INV2, the operating voltage of INV3, inverter INV1, INV2, the INV3 formation ring-type that joins end to end, inverter INV3 exports waveform,
Described pulse shaper comprises inverter INV4, and the input of inverter INV4 is connected with the output of inverter INV3, and the output of inverter INV4 is the output of described oscillating circuit.
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