CN102386130B - Forming method of dual-stress liner semiconductor device - Google Patents
Forming method of dual-stress liner semiconductor device Download PDFInfo
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- CN102386130B CN102386130B CN 201010275181 CN201010275181A CN102386130B CN 102386130 B CN102386130 B CN 102386130B CN 201010275181 CN201010275181 CN 201010275181 CN 201010275181 A CN201010275181 A CN 201010275181A CN 102386130 B CN102386130 B CN 102386130B
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Abstract
The invention provides a forming method of a dual-stress liner semiconductor device, which comprises the steps of: providing a substrate, wherein the substrate comprises a first region and a second region, which are connected with each other, the first region and the second region are respectively provided with a p-channel metal oxide semiconductor (PMOS) transistor and a n-channel metal oxide semiconductor (NMOS) transistor, and the part of the substrate at which the first region is connected with the second region is further provided with an interconnection structure; sequentially forming aliner layer capable of being ashed and a dual-stress liner layer on the substrate; forming a medium layer on the dual-stress liner layer; etching the medium layer, forming through holes above contactelectrodes of the PMOS transistor, the NMOS transistor and the interconnection structure, and exposing the dual-stress liner layer; etching the dual-stress liner layer at the bottoms of the through holes, and exposing the liner layer capable of being ashed; and removing the liner layer capable of being ashed at the bottoms of the through holes in an ashing way, and exposing the contact electrodesof the PMOS transistor, the NMOS transistor and the interconnection structure. The forming method prevents metallic silicides in the contact electrodes from being damaged when the through holes are formed.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly the formation method of a kind of pair of stress liner semiconductor device.
Background technology
Along with improving constantly of semiconductor process technology, two stress liners (DSL, Dual Stress Liner) technology has obtained using widely.Two stress liner technology form tensile stress laying (tensile stress liner) at nmos pass transistor, form compression laying (compressive stressliner) at the PMOS transistor, thereby increased the drive current of PMOS transistor and nmos pass transistor, improved the response speed of circuit.According to the study, the integrated circuit of the two stress liner technology of use can bring 24% speed lifting.
Fig. 1 to Fig. 4 shows the formation method of two stress liner semiconductor device of prior art.
With reference to figure 1, substrate 10 is provided, be formed with P trap (P-Well) and N trap (N-Well) in the described substrate 10, be formed with nmos pass transistor in the P trap, be formed with the PMOS transistor in the N trap.Described nmos pass transistor comprises source region and the drain region (not shown) in grid structure 11 and the grid structure 11 both sides substrates, described grid structure 11 comprises gate dielectric layer and the gate electrode (not shown) that is positioned on the gate dielectric layer, the surface of the gate electrode of described grid structure 11 has grid contact electrode 111, and the source region of described nmos pass transistor and surface, drain region form active contact electrode 112 and drain contact electrode 113 respectively; Described PMOS transistor comprises source region and the drain region (not shown) in grid structure 12 and the grid structure 12 both sides substrates, described grid structure 12 comprises gate dielectric layer and the gate electrode (not shown) that is positioned on the gate dielectric layer, the surface of the gate electrode of described grid structure 12 has grid contact electrode 121, and the transistorized source region of described PMOS and surface, drain region form active contact electrode 122 and drain contact electrode 123 respectively.Be formed with shallow channel isolation area (STI between described P trap and the N trap, Shallow Trench Isolation) 14, also be formed with grid interconnection structure (gateinterconnect) 13 in the substrate 10 in the zone between described PMOS transistor and the nmos pass transistor, material is polysilicon, and the surface of described grid interconnection structure 13 is formed with the touched electrode 131 that connects.The material of described each contact electrode is metal silicide, can form by self-aligned metal silicate technology, be used for reducing and follow-up formation embolism thereon between contact resistance.
With reference to figure 2, form tensile stress laying 15 (also being the P well area) on the described nmos pass transistor respectively, on described PMOS transistor (also being the N well area) form compression laying 16, the material of described tensile stress laying 15 and compression laying 16 all is silicon nitride, has constituted two stress liner layers jointly.In two stress liner technology, because depositing at twice, described tensile stress laying 15 and compression laying 16 finish, there is deviation of the alignment, therefore form overlapping (overlap) in the two zone that joins 19.
With reference to figure 3, form dielectric layer 17 on described substrate 10 surfaces, cover described tensile stress laying 15 and compression laying 16.
The described dielectric layer 17 of etching, tensile stress laying 15 and compression laying 16, above the contact electrode of described PMOS transistor, nmos pass transistor and grid interconnection structure, form through hole, with reference to figure 4, above described grid contact electrode 111, the touched electrode that connects 131 and grid contact electrode 121, form through hole 171,172 and 173 respectively.Fig. 4 only is signal, in actual applications, can also form through hole above other contact electrodes of needs, and be not limited only to shown in Figure 4.
Described through hole 171,172 and 173 forming process roughly can be divided into for two steps, and the described dielectric layer 17 of etching at first is to exposing described tensile stress laying 15 and compression laying 16; The described tensile stress laying 15 of etching and compression laying 16 afterwards are to exposing each contact electrode.But, owing to exist overlappingly between the tensile stress laying 15 in the zone 19 that joins of described P trap and N trap and the compression laying 16, make the thickness difference of two stress liner layers of different contact electrodes top.Therefore, in tensile stress laying 15 above wearing the described touched electrode 131 that connects quarter and the overlapping part of compression laying 16, can cause quarter (over etch) and damage to the grid contact electrode 111 of described through hole 171 belows and the grid contact electrode 131 of through hole 173 belows, destroy metal silicide wherein, cause the contact resistance between the follow-up contact electrode that is filled in embolism in the described through hole 171,172,173 and its below to increase, influence device performance.
Publication number is the formation method that discloses a kind of pair of liner semiconductor device in 2009/0289375 the U.S. Patent application, grinds by the laying of flatening process to overlapping part, makes the consistency of thickness of laying of each contact electrode top.But the technology of said method is complexity comparatively, the difficult control of the concrete thickness that grinds in the flatening process, and the thickness of the laying of each contact electrode top is in full accord after the very difficult assurance planarization.
Summary of the invention
The problem that the present invention solves provides the formation method of a kind of pair of stress liner semiconductor device, avoids forming in the process of through hole the metal silicide in the contact electrode is caused damage.
For addressing the above problem, the invention provides the formation method of a kind of pair of stress liner semiconductor device, comprising:
Substrate is provided, described substrate comprises first area and the second area that joins, be formed with PMOS transistor and nmos pass transistor in described first area and the second area respectively, also be formed with interconnection structure in the substrate of the joining part of described first area and second area;
But in described substrate, form ashing laying and two stress liner layer successively, cover described PMOS transistor, nmos pass transistor and interconnection structure;
Form dielectric layer at described pair of stress liner layer;
The described dielectric layer of etching forms first through hole, second through hole and third through-hole respectively above the contact electrode of described PMOS transistor, nmos pass transistor and interconnection structure, bottom-exposed goes out described pair of stress liner layer;
Two stress liner layers of described first through hole of etching, second through hole and third through-hole bottom, but described ashing laying exposed;
But the ashing laying of described first through hole, second through hole and third through-hole bottom is removed in ashing, exposes the contact electrode of described PMOS transistor, nmos pass transistor and interconnection structure.
Optionally, the contact electrode of described PMOS transistor and nmos pass transistor comprises one or more in the contact electrode of source electrode, grid or drain electrode of described PMOS transistor and nmos pass transistor, and described interconnection structure is the grid interconnection structure.
Optionally, but describedly in described substrate, form the ashing laying successively and two stress liner layers comprise:
But in described substrate, form the first ashing laying and the first stress liner layer successively;
Form the first photoresist figure at the described first stress liner layer, define described second area;
Be mask with the described first photoresist figure, etching is removed the first stress liner layer in the described second area;
But the first ashing laying in the described first photoresist figure and the described second area is removed in ashing;
But form the second ashing laying and the second stress liner layer successively, cover the first stress liner layer in the described first area and the substrate surface in the second area;
Form the second photoresist figure at the described second stress liner layer, define described first area;
Be mask with the described second photoresist figure, etching is removed the second stress liner layer in the described first area;
But the second ashing laying of first stress liner layer top in the described second photoresist figure and the described first area is removed in ashing.
Optionally, be formed with the PMOS transistor in the described first area, be formed with nmos pass transistor in the described second area, the described first stress liner layer is the compression laying, and the described second stress liner layer is the tensile stress laying.
Optionally, be formed with nmos pass transistor in the described first area, be formed with the PMOS transistor in the described second area, the described first stress liner layer is the tensile stress laying, and the described second stress liner layer is the compression laying.
Optionally, the material of described tensile stress laying and compression laying is silicon nitride.
Optionally, but the material of described ashing laying is amorphous carbon or diamond-like-carbon.
Optionally, but the thickness of described ashing laying be 50 to
Optionally, employed etching gas is CHF in the process of two stress liner layers of described first through hole of described etching, second through hole and third through-hole bottom
3And H
2Mist, or CH
2F
2And H
2Mist.
Optionally, but described ashing remove the reacting gas that uses in the process of ashing laying of described first through hole, second through hole and third through-hole bottom and be the plasma of oxygen or oxygen.
Compared with prior art, technical scheme of the present invention has following advantage:
But the technical program at first forms the ashing laying, but on the ashing laying, form two stress liner layers and dielectric layer afterwards again, form in the process of through hole in etching, but described ashing laying is as etching stop layer, but make etching process stop on the described ashing laying, can not cause damage to the metal silicide in the contact electrode, but last again through the ashing laying removal of ashing with the through hole below, equally can not cause damage to the metal silicide in the described contact electrode yet.
Description of drawings
Fig. 1 to Fig. 4 is the cross-sectional view of formation method of a kind of pair of liner semiconductor device of prior art;
Fig. 5 is the schematic flow sheet of formation method of two liner semiconductor device of the embodiment of the invention;
Fig. 6 to Figure 17 is the cross-sectional view of formation method of two liner semiconductor device of the embodiment of the invention.
Embodiment
In the formation method of two stress liner semiconductor device of prior art, in PMOS transistor and nmos pass transistor adjacent areas, tensile stress laying and compression laying overlap mutually, thickness is thicker, need carry out quarter in order to carve the laying of wearing overlapping part, cause the metal silicide in the contact electrode impaired, increase contact resistance, influence device performance.
But the technical program forms the ashing laying below two stress liner layers, form in the process of through hole in etching, but can make etching process stop on the described ashing laying by selective etch, but by cineration technics the ashing laying of through hole below be removed again afterwards.Because described contact electrode is not subjected to the influence of etching process, and cineration technics can not cause damage to contact electrode yet, thereby avoided the damage to the metal silicide in the contact electrode, improved device performance.
For above-mentioned purpose of the present invention, feature and advantage can more be become apparent, below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.
Set forth detail in the following description so that fully understand the present invention.But the present invention can be different from alternate manner described here and implements with multiple, and those skilled in the art can do similar popularization under the situation of intension of the present invention.Therefore the present invention is not subjected to the restriction of following public embodiment.
Fig. 5 shows the schematic flow sheet of formation method of two stress liner layer semiconductor device of the embodiment of the invention, as shown in Figure 5, comprise: execution in step S21, substrate is provided, described substrate comprises first area and the second area that joins, be formed with PMOS transistor and nmos pass transistor in described first area and the second area respectively, also be formed with interconnection structure in the substrate of the joining part of described first area and second area; Execution in step S22, but ashing laying and two stress liner layer in described substrate, formed successively, cover described PMOS transistor, nmos pass transistor and interconnection structure; Execution in step S23 forms dielectric layer at described pair of stress liner layer; Execution in step S24, the described dielectric layer of etching forms first through hole, second through hole and third through-hole respectively above the contact electrode of described PMOS transistor, nmos pass transistor and interconnection structure, and bottom-exposed goes out described pair of stress liner layer; Execution in step S25, two stress liner layers of described first through hole of etching, second through hole and third through-hole bottom, but expose described ashing laying; Execution in step S26, but the ashing laying of described first through hole, second through hole and third through-hole bottom is removed in ashing, exposes the contact electrode of described PMOS transistor, nmos pass transistor and interconnection structure.
Below in conjunction with Fig. 5 and Fig. 6 to Figure 17 the formation method of two stress liner semiconductor device of the embodiment of the invention is elaborated.
With reference to figure 5 and Fig. 6, execution in step S21, substrate is provided, described substrate comprises first area and the second area that joins, be formed with PMOS transistor and nmos pass transistor in described first area and the second area respectively, also be formed with interconnection structure in the substrate of the joining part of described first area and second area.Concrete, substrate 20 is provided, described substrate 20 is semi-conducting material, can be monocrystalline silicon, also can be silicon Germanium compound, can also be epitaxial layer structure on silicon-on-insulator (SOI, Silicon On Insulator) structure or the silicon.
Described substrate 20 comprises first area I and second area II, wherein, is formed with the P trap among the I of first area, is formed with nmos pass transistor in the P trap, and described nmos pass transistor comprises grid structure 21, source region and drain region (not shown).Described grid structure 21 comprises gate dielectric layer and gate electrode (not shown), the material of described gate dielectric layer is silica, the material of gate electrode is polysilicon, the surface of the gate electrode of described grid structure 21 has grid contact electrode 211, and it forms technology can be self-aligned metal silicate technology.The source region of described nmos pass transistor and the surface in drain region form active contact electrode 212 and drain contact electrode 213 respectively, and it forms technology can be self-aligned metal silicate technology.
Be formed with the N trap among the described second area II, be formed with the PMOS transistor in the N trap, described PMOS transistor comprises grid structure 22, source region and drain region (not shown).Described grid structure 22 comprises gate dielectric layer and gate electrode (not shown), the material of described gate dielectric layer is silica, the material of gate electrode is polysilicon, the surface of the gate electrode of described grid structure 22 has grid contact electrode 221, and it forms technology can be self-aligned metal silicate technology.The surface in the transistorized source region of described PMOS and drain region forms active contact electrode 222 and drain contact electrode 223 respectively, and it forms technology can be self-aligned metal silicate technology.
The joining part of described first area I and second area II also is formed with shallow channel isolation area 24, is used for the isolation between PMOS and the nmos pass transistor, and this shallow channel isolation area is optional.
In the substrate 20 of the joining part of described first area I and second area II, with described PMOS transistor and nmos pass transistor arranged side by side also be formed with interconnection structure 23, interconnection structure described in the present embodiment 23 is the grid interconnection structure, its material is polysilicon, the surface is formed with the touched electrode 231 that connects, and it forms technology can be self-aligned metal silicate technology.In the present embodiment, the joining part that described interconnection structure 23 is formed at described first area I and second area II specifically refers to described interconnection structure 23 across described first area I and second area II; In other embodiment of the technical program, described interconnection structure 23 can also be formed at the part of joining with second area II among the I of first area, or the part of joining with first area I among the second area II.
With reference to figure 5, execution in step S22, but in described substrate, form ashing laying and two stress liner layer successively, cover described PMOS transistor, nmos pass transistor and interconnection structure.Below in conjunction with Fig. 7 to Figure 14 this step is elaborated.
With reference to figure 7, but in described substrate 20, form the first ashing laying 25 and the first stress liner layer 26 successively.But the material of the described first ashing laying 25 is can be by the material of ashing (ashing) technology removal, can be amorphous carbon (amorphous carbon) or diamond-like-carbon (diamond-likecarbon), be preferably amorphous carbon in the present embodiment, its formation method is physical vapor deposition (PVD), and thickness is
Extremely
The described first stress liner layer 26 is tensile stress layings, is specially the tensile stress silicon nitride layer, and its material is silicon nitride, and the formation method of the tensile stress silicon nitride layer of two stress liner technology is identical in formation method and the prior art.
With reference to figure 8, form the first photoresist figure 27 at the described first stress liner layer 26, the described first photoresist figure 27 has defined the pattern of second area II.Concrete, can on the described first stress liner layer 26, spin coating form photoresist layer, more described photoresist layer is carried out patterning afterwards, form the described first photoresist figure 27.
With reference to figure 9, be mask with the described first photoresist figure 27, etching is removed the first stress liner layer 26 among the described second area II, but makes expose the described first ashing laying 25 in second area II.
With reference to Figure 10, but the first ashing laying 25 among the described first photoresist figure 27 and the described second area II is removed in ashing, exposes the surface of substrate 20 of described second area II and the first stress liner layer 26 of first area I.Described podzolic process can adopt the plasma of oxygen or oxygen.So far, but the remaining first ashing laying 25 and the first stress liner layer 26 cover the nmos pass transistor among the described first area I.
With reference to Figure 11, but form the second ashing laying 28 and the second stress liner layer 29 successively, cover the first stress liner layer 26 among the described first area I and the surface of the substrate 20 among the second area II.But but the material of the described second ashing laying 28, formation method are identical with the described first ashing laying 25 with thickness, just repeat no more here.The described second stress liner layer 29 is compression layings, is specially the compression silicon nitride layer, and its material is silicon nitride, and the formation method of the compression silicon nitride layer of two stress liner technology is identical in formation method and the prior art.
With reference to Figure 12, form the second photoresist figure 30 at the described second stress liner layer 29, define the figure of described first area I.Concrete, can on the described second stress liner layer 29, spin coating form photoresist layer, more described photoresist layer is carried out patterning afterwards, form the described second photoresist figure 30.
With reference to Figure 13, be mask with the described second photoresist figure 30, etching is removed the second stress liner layer 29 among the described first area I, but exposes the second ashing laying 28 among the I of first area.
With reference to Figure 14, but the second ashing laying 28 of the first stress liner layer, 26 top among the described second photoresist figure 30 and the described first area I is removed in ashing, exposes the surface of the first stress liner layer 26 among the described first area I and the surface of the second stress liner layer 29 among the second area II.Described podzolic process can adopt the plasma of oxygen or oxygen.
So far, but the remaining first ashing laying 25 and the first stress liner layer 26 cover the nmos pass transistor among the described first area I; But the PMOS transistor that the remaining second ashing laying 28 and the second stress liner layer 29 cover among the described second area II.The described first stress liner layer 26 and the second stress liner layer 29 have constituted described pair of stress liner layer jointly, but but but the described remaining first ashing laying 25 and the remaining second ashing laying 28 have constituted described ashing laying jointly.
Two stress liner processes are similar with forming in the prior art, because tensile stress laying and compression laying form at twice, because problems such as technology deviation of the alignment, make in the joining part 31 of described first area I and second area II, that but but the first ashing laying 25, the first stress liner layer 26, the second ashing laying 28 and the second stress liner layer 29 produce is overlapping, makes the thicknesses of layers of contact electrode top of described interconnection structure obviously greater than other zones.
Need to prove that the formation order of the described first stress liner layer 26 and the second stress liner layer 29 can exchange; And, what form among the described first area I also can be N trap and PMOS transistor, what form among the described second area II also can be P trap and nmos pass transistor, only need guarantee to be formed with the compression laying, to be formed with the tensile stress laying in the zone that is formed with nmos pass transistor and to get final product being formed with the transistorized zone of PMOS.
With reference to figure 5 and Figure 15, execution in step S23 forms dielectric layer at described pair of stress liner layer; Execution in step S24, the described dielectric layer of etching forms first through hole, second through hole and third through-hole respectively above the contact electrode of described PMOS transistor, nmos pass transistor and interconnection structure, and bottom-exposed goes out described pair of stress liner layer.Concrete, forming dielectric layer 32 at the described first stress liner layer 26 and the second stress liner layer 29, the material of described dielectric layer 32 can be silica, (BD, BlackDiamond) etc., its formation method can be chemical vapour deposition (CVD) to black diamond.Afterwards, described dielectric layer 32 is carried out etching, above the grid contact electrode of described nmos pass transistor, form first through hole 321, above the transistorized grid contact electrode of described PMOS, form second through hole 322, above the touched electrode that connects of described interconnection structure, form third through-hole 323, the bottom-exposed of each through hole goes out described pair of stress liner layer, be example with Figure 15, first through hole, 321 bottom-exposed go out the first stress liner layer 26, second through hole, 322 bottom-exposed go out the described second stress liner layer 29, and third through-hole 323 bottom-exposed go out the described second stress liner layer 29.In addition, according to the needs of practical application, in other embodiments, can also above other one or more contact electrodes of described PMOS transistor and nmos pass transistor, form through hole.
With reference to figure 5 and Figure 16, execution in step S25, two stress liner layers of described first through hole of etching, second through hole and third through-hole bottom, but expose described ashing laying.Concrete, the first stress liner layer 26 of described first through hole of etching 321 bottoms, but the described first ashing laying 25 exposed; The second stress liner layer 29 of described second through hole of etching 322 bottoms, but the described second ashing laying 28 exposed; The second stress liner layer 29 of the described third through-hole of etching 323 bottoms, but but expose the described first ashing laying 27 and the second ashing laying 28.Each through hole of this step realizes that by a step etching etching gas in the etching process mainly is CHF
3And H
2Mist, or CH
2F
2And H
2Mist, be preferably CH in the present embodiment
2F
2And H
2Because but but this etching reaction gas has very high selection ratio for the amorphous carbon in the silicon nitride material in the described first stress liner layer 26 and the second stress liner layer 29 and the first ashing laying 25 and the second ashing laying 28 or diamond like carbon material with carbon element, can be so that but but the etching process of each through hole can stop at the surface of the described first ashing laying 25 and the second ashing laying 28 (about the detailed description of high selectivity in the etching process of this step, can be with reference to following document: J.S.Kim, B.S.Kwon, W.Heo, C.R.Jung, and J.S.Park.2010 American Vacuum Society.DOI:10.1116/1.3268624), can not cause damage to the metal silicide in each contact electrode of below.
Need to prove, with reference to Figure 13 and Figure 14, when but the second ashing laying 28 among the described second photoresist figure 30 and the second area II is removed in ashing, in described joining part 31, but the second ashing laying 28 of below, the remaining second stress liner layer 29 edge is influenced by ashing reaction also can is removed, therefore, in fact, in described joining part 31, but the first mutual overlapping stress liner layer 26 and the second ashing laying 28 between the second stress liner layer 29 are also removed by ashing basically.Therefore, with reference to Figure 15, when the second stress liner layer 29 of the described through hole of etching 322 bottoms, owing to can simultaneously the first stress liner layer of its below not worn for 26 quarters, thereby but expose the described first ashing laying 25, form structure as shown in figure 16.
With reference to figure 5 and Figure 17, execution in step S26, but the ashing laying of described first through hole, second through hole and third through-hole bottom is removed in ashing, exposes the contact electrode of described PMOS transistor, nmos pass transistor and interconnection structure.Concrete, through a step ashing, but remove the first ashing laying 25 of described first through hole 321 bottoms, expose the grid contact electrode 211 of nmos pass transistor; But remove the second ashing laying 28 of second through hole, 322 bottoms, expose the transistorized grid contact electrode 221 of described PMOS; But but remove the first ashing laying 25 and the second ashing laying 28 of third through-hole 323 bottoms, expose the touched electrode 231 that connects of described interconnection structure.Employed reacting gas is oxygen (O in the described podzolic process
2) or the plasma of oxygen.Owing to be different from the employed plasma bombardment of dry etching in the podzolic process, belong to chemical reaction process, therefore can not cause damage to the metal silicide in the contact electrode of each via bottoms.Afterwards, the filled conductive material forms embolism in each through hole.
To sum up, but the technical program forms two stress liner layers at first form the ashing laying in substrate after again, make and form in the process of through hole in etching, but etching process can stop on the described ashing laying, through ashing but the ashing laying of through hole below is removed again afterwards, can not cause damage to the metal silicide in the contact electrode of through hole below, improve device performance.
Though the present invention with preferred embodiment openly as above; but it is not to limit the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement that technical solution of the present invention is made possible change and modification; therefore; every content that does not break away from technical solution of the present invention; to any simple modification, equivalent variations and modification that above embodiment does, all belong to the protection range of technical solution of the present invention according to technical spirit of the present invention.
Claims (7)
1. the formation method of two stress liner semiconductor device is characterized in that, comprising:
Substrate is provided, described substrate comprises first area and the second area that joins, be formed with PMOS transistor and nmos pass transistor in described first area and the second area respectively, also be formed with interconnection structure in the substrate of the joining part of described first area and second area;
But in described substrate, form ashing laying and two stress liner layer successively, cover described PMOS transistor, nmos pass transistor and interconnection structure;
Form dielectric layer at described pair of stress liner layer;
The described dielectric layer of etching forms first through hole, second through hole and third through-hole respectively above the contact electrode of described PMOS transistor, nmos pass transistor and interconnection structure, bottom-exposed goes out described pair of stress liner layer;
Two stress liner layers of described first through hole of etching, second through hole and third through-hole bottom, but described ashing laying exposed;
But the ashing laying of described first through hole, second through hole and third through-hole bottom is removed in ashing, exposes the contact electrode of described PMOS transistor, nmos pass transistor and interconnection structure;
Wherein, but in described substrate, form the ashing laying successively and two stress liner layers comprise:
But in described substrate, form the first ashing laying and the first stress liner layer successively;
Form the first photoresist figure at the described first stress liner layer, define described second area;
Be mask with the described first photoresist figure, etching is removed the first stress liner layer in the described second area;
But the first ashing laying in the described first photoresist figure and the described second area is removed in ashing;
But form the second ashing laying and the second stress liner layer successively, cover the first stress liner layer in the described first area and the substrate surface in the second area;
Form the second photoresist figure at the described second stress liner layer, define described first area;
Be mask with the described second photoresist figure, etching is removed the second stress liner layer in the described first area;
But the second ashing laying of first stress liner layer top in the described second photoresist figure and the described first area is removed in ashing;
If be formed with the PMOS transistor in the described first area, be formed with nmos pass transistor in the described second area, then the described first stress liner layer is the compression laying, the described second stress liner layer is the tensile stress laying; If be formed with nmos pass transistor in the described first area, be formed with the PMOS transistor in the described second area, then the described first stress liner layer is the tensile stress laying, the described second stress liner layer is the compression laying.
2. the formation method of according to claim 1 pair of stress liner semiconductor device, it is characterized in that, the contact electrode of described PMOS transistor and nmos pass transistor comprises one or more in the contact electrode of source electrode, grid or drain electrode of described PMOS transistor and nmos pass transistor, and described interconnection structure is the grid interconnection structure.
3. the formation method of according to claim 1 pair of stress liner semiconductor device is characterized in that, the material of described tensile stress laying and compression laying is silicon nitride.
4. according to the formation method of each described pair of stress liner semiconductor device in the claim 1 to 2, it is characterized in that, but the material of described ashing laying is amorphous carbon or diamond-like-carbon.
5. according to the formation method of each described pair of stress liner semiconductor device in the claim 1 to 2, it is characterized in that, but the thickness of described ashing laying is
Extremely
6. according to the formation method of each described pair of stress liner semiconductor device in the claim 1 to 2, it is characterized in that employed etching gas is CHF in the process of two stress liner layers of described first through hole of described etching, second through hole and third through-hole bottom
3And H
2Mist, or CH
2F
2And H
2Mist.
7. according to the formation method of each described pair of stress liner semiconductor device in the claim 1 to 2, it is characterized in that, but described ashing is removed the reacting gas that uses in the process of ashing laying of described first through hole, second through hole and third through-hole bottom and is the plasma of oxygen or oxygen.
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