CN102386083B - MOS (metal oxide semiconductor) transistor and manufacturing method of MOS transistor gate dielectric layer - Google Patents

MOS (metal oxide semiconductor) transistor and manufacturing method of MOS transistor gate dielectric layer Download PDF

Info

Publication number
CN102386083B
CN102386083B CN 201010275191 CN201010275191A CN102386083B CN 102386083 B CN102386083 B CN 102386083B CN 201010275191 CN201010275191 CN 201010275191 CN 201010275191 A CN201010275191 A CN 201010275191A CN 102386083 B CN102386083 B CN 102386083B
Authority
CN
China
Prior art keywords
gate
dielectric
layer
manufacture method
dielectric layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN 201010275191
Other languages
Chinese (zh)
Other versions
CN102386083A (en
Inventor
三重野文健
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Original Assignee
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Manufacturing International Shanghai Corp, Semiconductor Manufacturing International Beijing Corp filed Critical Semiconductor Manufacturing International Shanghai Corp
Priority to CN 201010275191 priority Critical patent/CN102386083B/en
Publication of CN102386083A publication Critical patent/CN102386083A/en
Application granted granted Critical
Publication of CN102386083B publication Critical patent/CN102386083B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The invention relates to a manufacturing method of an MOS (metal oxide semiconductor) transistor gate dielectric layer. The manufacturing method comprises the following steps of: providing a semiconductor substrate, wherein a false gate dielectric layer and a dielectric protective layer are formed on the semiconductor substrate, and a gate opening is formed in the dielectric protective layer and leads the false gate dielectric layer to be exposed; forming a sacrificial layer on the dielectric protective layer and in the gate opening, wherein the sacrificial layer covers the gate opening in a shape-maintaining manner; etching the sacrificial layer in an anisotropic manner, and only retaining the sacrificial layer on the vertical side wall of the gate opening; forming a high-K dielectric material on the dielectric protective layer and in the gate opening, wherein the high-K dielectric material covers the gate opening in a shape-maintaining manner; and carrying out annealing treatment onthe semiconductor substrate and leading the sacrificial layer on the vertical side wall of the gate opening and the high-K dielectric material to react to form a mixed dielectric layer which has a dielectric constant less than that of the high-K dielectric material. In the manufacturing method, a high-K gate dielectric layer at the bottom part of the metal gate is not damaged and simultaneously the gate parasitic capacitance is reduced.

Description

The manufacture method of MOS transistor and gate dielectric layer thereof
Technical field
The present invention relates to technical field of semiconductors, more specifically, the present invention relates to the manufacture method of MOS transistor and gate dielectric layer thereof.
Background technology
Along with the continuous development of ic manufacturing technology, the characteristic size of MOS transistor is also more and more littler.Constantly dwindle under the situation in the MOS transistor characteristic size, in order to reduce the parasitic capacitance of MOS transistor grid, improve device speed, (High K Metal Gate, gate stack structure HKMG) is introduced in the MOS transistor for high K gate dielectric layer and metal gates.
Be the influence to other structures of transistor of the gate metal material of avoiding metal gates, the gate stack structure of described metal gates and high K gate dielectric layer adopts grid to substitute (replacement gate) technology usually and makes.In this technology, before source-drain area injects, at first form the dummy grid that is constituted by polysilicon in gate electrode position to be formed, described dummy grid is used for autoregistration and forms PROCESS FOR TREATMENT such as source-drain area.And after forming source-drain area, can remove described dummy grid and form gate openings in the position of dummy grid, afterwards, in described gate openings, fill high K gate dielectric layer and metal gates more successively.Because metal gates is made after the source-drain area injection is finished again, this makes that the quantity of subsequent technique is reduced, and has avoided the gate metal material to be unsuitable for carrying out the problem of high-temperature process.
Yet, adopt above-mentioned grid alternative techniques to make MOS transistor and still exist challenge.Along with further dwindling of grid length, this problem is more serious.In the gate stack structure that this technology forms, be coated with high K gate dielectric layer on the vertical sidewall of described gate openings equally, this causes the parasitic capacitance between source-drain area and metal gates to increase.And the unnecessary parasitic capacitance increase of metal gates can influence devices switch speed.
For solving the bigger problem of described metal gates parasitic capacitance, US Patent No. 6864145 discloses a kind of by reduce the method for described gate dielectric layer dielectric constant at the gate dielectric layer injection silicon ion of gate openings vertical sidewall.Yet described silicon ion not only is infused in the high K gate dielectric layer of gate openings vertical sidewall, also can be injected into simultaneously in the high K gate dielectric layer of gate openings bottom, and this can destroy the dielectric property of the high K gate dielectric layer in gate openings bottom, and then influences device performance.7148099 of US Patent No. disclose the method for another kind of reduction gate dielectric layer dielectric constant.In the method, need in gate openings, to fill up in advance polysilicon or gate metal material, inject silicon ion with certain angle more afterwards, owing to have polysilicon or gate metal material to do to stop in the gate openings, the dielectric property of gate openings bottom gate dielectric layer are not subjected to inject to be influenced.Yet, described polysilicon or gate metal material stop also that simultaneously silicon ion is injected in the high K gate dielectric layer of gate openings vertical sidewall, make the high K gate dielectric layer of this position only have the dielectric constant of subregion to be minimized, the grid parasitic capacitance still is difficult to effectively reduce.
Summary of the invention
The problem that the present invention solves provides the manufacture method of a kind of MOS transistor and gate dielectric layer thereof, when not destroying the high K gate dielectric layer in metal gates bottom, has reduced the parasitic capacitance of metal gates, has improved device performance.
For addressing the above problem, the invention provides a kind of manufacture method of MOS transistor gate dielectric layer, comprising:
Semiconductor substrate is provided, is formed with pseudo-gate dielectric layer and dielectric protection layer on the described Semiconductor substrate, be formed with gate openings in the described dielectric protection layer, described gate openings makes pseudo-gate dielectric layer expose;
On described dielectric protection layer with in the gate openings, form sacrifice layer, described sacrifice layer conformal cover gate opening;
The described sacrifice layer of anisotropic etching only keeps the sacrifice layer on the gate openings vertical sidewall;
Form high-k dielectric material on described dielectric protection layer with in the gate openings, described high-k dielectric material conformal covers described gate openings;
Described Semiconductor substrate is carried out annealing in process, make that the sacrifice layer on the gate openings vertical sidewall mixes dielectric layer with high-k dielectric material reaction formation, described mixing dielectric layer has the dielectric constant less than high-k dielectric material.
Compared with prior art, the present invention has the following advantages:
1. utilize the chemical reaction between sacrifice layer and high-k dielectric material, both sides at metal gates form the mixing dielectric layer that has than low-k, the shape of described sacrifice layer can accurately be controlled, thereby has avoided the ion injection mode to form the unsteadiness of mixing dielectric layer;
2. the mixing dielectric layer of described low-k effectively reduces the grid parasitic capacitance of MOS transistor.
Description of drawings
Fig. 1 is the schematic flow sheet of the manufacture method of MOS transistor gate dielectric layer of the present invention.
Fig. 2 to Fig. 7 is the generalized section of each production phase of manufacture method of MOS transistor gate dielectric layer of the present invention.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.
Set forth a lot of details in the following description so that fully understand the present invention, implement but the present invention can also adopt other to be different from alternate manner described here, so the present invention has not been subjected to the restriction of following public specific embodiment.
Just as described in the background section, in the high K gate dielectric layer manufacture method of prior art, in order to reduce the dielectric constant of gate openings vertical sidewall gate dielectric layer, need in described gate dielectric layer, inject silicon ion.Yet the injection of described silicon ion may reduce the dielectric property of gate openings bottom gate dielectric layer, or owing to stopping of gate openings packing material makes the gate openings vertical sidewall only have the dielectric constant of the high K gate dielectric layer of part to be lowered.
At the problems referred to above, the present inventor provides a kind of manufacture method of MOS transistor gate dielectric layer.In the method, before filling high-k dielectric material to gate openings, need form sacrifice layer at the vertical sidewall of gate openings, and after high-k dielectric material is filled in conformal, described Semiconductor substrate is carried out annealing in process, described annealing in process makes sacrifice layer and high-k dielectric material react, and forms the mixing dielectric layer that has than low-k, thereby has effectively reduced the parasitic capacitance of metal gates both sides.
With reference to figure 1, show the flow process of the manufacture method of MOS transistor gate dielectric layer of the present invention, comprising:
Execution in step S102 provides Semiconductor substrate, is formed with pseudo-gate dielectric layer and dielectric protection layer on the described Semiconductor substrate, is formed with gate openings in the described dielectric protection layer, and described gate openings makes pseudo-gate dielectric layer expose;
Execution in step S104 forms sacrifice layer on described dielectric protection layer with in the gate openings, described sacrifice layer conformal cover gate opening;
Execution in step S106, the described sacrifice layer of anisotropic etching only keeps the sacrifice layer on the gate openings vertical sidewall;
Execution in step S108 forms high-k dielectric material on described dielectric protection layer with in the gate openings, described high-k dielectric material conformal covers described gate openings;
Execution in step S110 carries out annealing in process to described Semiconductor substrate, makes that the sacrifice layer on the gate openings vertical sidewall mixes dielectric layer with high-k dielectric material reaction formation, and described mixing dielectric layer has the dielectric constant less than high-k dielectric material.
In specific embodiment, described sacrifice layer can adopt semi-conducting material or carbon such as silicon, germanium, SiGe, and described high-k dielectric material comprises HfO 2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al 2O 3, La 2O 3, ZrO 2Or LaAlO etc., described mixing dielectric layer is formed by sacrifice layer and high-k dielectric material reaction, and is corresponding, and described mixing dielectric layer comprises Hf xSi yO z, Hf xSi yO zH, Hf uTi xSi yO z, Hf uTa xSi yO z, Hf uZr xSi yO z, Si xAl yO z, Hf xGe yO zOr Hf uSi xGe yO zDeng.Be that Si, high-k dielectric material are HfO with described sacrifice layer 2Be example, described Si and HfO 2The reaction back generates mixes dielectric layer Hf xSi yO z, and described Hf xSi yO zDielectric constant significantly be lower than HfO 2Dielectric constant.
After above-mentioned steps was finished, the dielectric layer in the described gate openings comprised: the high-k dielectric material (being high K gate dielectric layer) of gate openings bottom and the mixing dielectric layer on the gate openings vertical sidewall.Afterwards, also need to continue in described gate openings, to fill the gate metal material, to form metal gates.
Next, in conjunction with specific embodiments, the manufacture method of MOS transistor gate dielectric layer of the present invention is further detailed.
Fig. 2 to Fig. 7 is the generalized section of each production phase of manufacture method of MOS transistor gate dielectric layer of the present invention.
As shown in Figure 2, provide Semiconductor substrate 201, be formed with pseudo-gate dielectric layer 202 and dielectric protection layer 203 on the described Semiconductor substrate 201 successively, described pseudo-gate dielectric layer 202 covers Semiconductor substrate 201 surfaces.Also be formed with gate openings 207 in the described dielectric protection layer 203, described gate openings 207 makes pseudo-gate dielectric layer 202 surfaces of its bottom expose.Optionally, also be formed with clearance wall 205 in the dielectric protection layer 203 of described gate openings 207 both sides, described clearance wall 205 can adopt silicon nitride.
As shown in Figure 3, form sacrifice layer 209 on described dielectric protection layer 203 with in the gate openings 207, described sacrifice layer 209 conformals cover described gate openings 207.Described conformal covers and refers to that the thickness of sacrifice layer 209 is less for the degree of depth and width of gate openings 207, can not fill completely described gate openings 207, makes described gate openings 207 still keep and does not form the preceding similar shape of film.
In specific embodiment, adopt the mode of chemical vapor deposition to form described sacrifice layer 209, described sacrifice layer 209 comprises: semi-conducting material or carbon such as silicon, germanium, SiGe, its thickness is less than or equal to 20 dusts.Preferably, be mixed with protium or fluorine element in the sacrifice layer 209 that adopts silicon to form, the doping content of described protium is 5% to 30%, and the doping content of described fluorine element is 5% to 15%.The protium of described doping or fluorine element can reduce subsequent anneal handle in the reaction difficulty of silicon and high-k dielectric material.
As shown in Figure 4, the described sacrifice layer 209 of anisotropic etching removes on the dielectric protection layer 203 sacrifice layer 209 with gate openings 207 bottoms, only keeps the sacrifice layer 209 on gate openings 207 vertical sidewalls.Described residual sacrifice layer 209 can also strengthen the metal electrode of follow-up formation and the distance between source-drain area, thereby has reduced the grid parasitic capacitance.In addition, the shape of described sacrifice layer 209 can accurately be controlled, thereby has avoided the ion injection mode to form the unsteadiness of dielectric layer with low dielectric constant technology.
After described sacrifice layer 209 anisotropic etchings, the pseudo-gate dielectric layer 202 of gate openings 207 bottoms exposes.Afterwards, remove the pseudo-gate dielectric layer 202 that expose described gate openings 207 bottoms, until exposing described Semiconductor substrate 201 surfaces.In specific embodiment, described pseudo-gate dielectric layer 202 is silica, and adopting concentration is that 1% hydrofluoric acid solution (DHF) removes described pseudo-gate dielectric layer 202, and the reaction time is 3 to 5 minutes.
According to the difference of specific embodiment, can also select not remove described pseudo-gate dielectric layer 202 and directly carry out subsequent technique.
As shown in Figure 5, on described dielectric protection layer 203 with in the gate openings 207, form high-k dielectric material 211, described high-k dielectric material 211 conformal cover gate openings 207.Described high-k dielectric material comprises HfO 2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al 2O 3, La 2O 3, ZrO 2Perhaps LaAlO.In specific embodiment, the thickness of described high-k dielectric material is less than or equal to 60 dusts.
As shown in Figure 6, described Semiconductor substrate 201 is carried out annealing in process, the sacrifice layer on described gate openings 207 vertical sidewalls and high-k dielectric material 211 reactions form and mix dielectric layer 213, and described mixing dielectric layer 213 is connected with clearance wall 205.Described mixing dielectric layer 213 has the dielectric constant less than high-k dielectric material 211.Adopt semi-conducting material or carbon such as silicon, germanium, SiGe at described sacrifice layer, and described high-k dielectric material adopts HfO 2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al 2O 3, La 2O 3, ZrO 2Or under the situation of LaAlO, described mixing dielectric layer 213 is formed by sacrifice layer and high-k dielectric material reaction, for example can be Hf xSi yO z, Hf xSi yO zH, Hf uTi xSi yO z, Hf uTa xSi yO z, Hf uZr xSi yO z, Si xAl yO z, Hf xGe yO zOr Hf uSi xGe yO zDeng.The dielectric constant of the material of the mixing dielectric layer of more than enumerating 213 is all less than the high-k dielectric material of correspondence.
In specific embodiment, described annealing in process adopts short annealing to handle, and reaction temperature is 650 to 850 degrees centigrade, and the reaction time is 1 to 3 minute, and reaction atmosphere is nitrogen.
Because described sacrifice layer only residues on the vertical sidewall of gate openings 207, when described annealing in process, the high-k dielectric material 211 of gate openings 207 bottoms can't change the mixing dielectric layer 213 of low-k into, has also just avoided the decline of the high K gate dielectric layer of the MOS transistor dielectric property of employing the present invention making.
As shown in Figure 7, after forming described mixing dielectric layer 213, continue in described gate openings, to fill up the gate metal material.Afterwards, the described gate metal material of planarization only keeps the gate metal material in the gate openings, and the gate metal material of described reservation namely constitutes metal gates 215.
In specific embodiment, described gate metal material comprises: Ti, Co, Ni, Al or W, or one or more alloy or metal silicide among Ti, Co, Ni, Al, the W.
In different embodiment, before forming described gate metal material, can also in described gate openings, conformal cover the workfunction metal material, described workfunction metal material is used for regulating the threshold voltage of MOS transistor.Described workfunction metal material includes but not limited to TiN, TiAlN, TaN, TaAlN or TaC.
So far, the grid structure that comprises high K gate dielectric layer and metal gates that adopts the present invention to make completes, described metal gates is positioned on the Semiconductor substrate, be formed with high K gate dielectric layer between the bottom of metal gates and Semiconductor substrate, and described metal gates both sides are formed with the mixing dielectric layer with low-k, and described mixing dielectric layer is connected with clearance wall and metal gates respectively.Described mixing dielectric layer has the dielectric constant less than high K gate dielectric layer, thereby has reduced the grid parasitic capacitance.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.

Claims (17)

1. the manufacture method of a MOS transistor gate dielectric layer is characterized in that, comprising:
Semiconductor substrate is provided, is formed with pseudo-gate dielectric layer and dielectric protection layer on the described Semiconductor substrate, be formed with gate openings in the described dielectric protection layer, described gate openings makes pseudo-gate dielectric layer expose;
On described dielectric protection layer with in the gate openings, form sacrifice layer, described sacrifice layer conformal cover gate opening;
The described sacrifice layer of anisotropic etching only keeps the sacrifice layer on the gate openings vertical sidewall;
Form high-k dielectric material on described dielectric protection layer with in the gate openings, described high-k dielectric material conformal covers described gate openings;
Described Semiconductor substrate is carried out annealing in process, make that the sacrifice layer on the gate openings vertical sidewall mixes dielectric layer with high-k dielectric material reaction formation, described mixing dielectric layer has the dielectric constant less than high-k dielectric material;
Wherein, described sacrifice layer comprises silicon, and is mixed with protium or fluorine element.
2. manufacture method as claimed in claim 1 is characterized in that, the content of protium is 5% to 30% in the described sacrifice layer.
3. manufacture method as claimed in claim 1 is characterized in that, the content of fluorine element is 5% to 15% in the described sacrifice layer.
4. manufacture method as claimed in claim 1 is characterized in that, adopts the mode of chemical vapor deposition to form described sacrifice layer.
5. manufacture method as claimed in claim 1 is characterized in that, the thickness of described sacrifice layer is less than or equal to 20 dusts.
6. manufacture method as claimed in claim 1 is characterized in that, described high-k dielectric material comprises HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al 2O 3, La 2O 3, ZrO 2Or LaAlO.
7. manufacture method as claimed in claim 6 is characterized in that, the thickness of described high-k dielectric material is less than or equal to 60 dusts.
8. manufacture method as claimed in claim 6 is characterized in that, described mixing dielectric layer comprises Hf xSi yO z, Hf uTi xSi yO z, Hf uTa xSi yO z, Hf uZr xSi yO z, Si xAl yO zOr Hf uSi xGe yO z
9. manufacture method as claimed in claim 1, it is characterized in that adopt short annealing to handle described Semiconductor substrate is carried out annealing in process, the reaction condition that described short annealing is handled is: reaction temperature is 650 to 850 degrees centigrade, reaction time is 1 to 3 minute, and reaction atmosphere is nitrogen.
10. manufacture method as claimed in claim 1 is characterized in that, forms before the high-k dielectric material on described dielectric protection layer with in the gate openings, also comprises: remove the pseudo-gate dielectric layer of gate openings bottom and expose semiconductor substrate surface.
11. manufacture method as claimed in claim 1 is characterized in that, described pseudo-gate dielectric layer is silica; Described manufacture method also comprises: adopting concentration is that 1% hydrofluoric acid solution removes described pseudo-gate dielectric layer, and the reaction time is 3 to 5 minutes.
12. manufacture method as claimed in claim 1 is characterized in that, also comprises: before forming sacrifice layer, form clearance wall in the dielectric protection layer of described gate openings both sides, described clearance wall has the dielectric constant less than high-k dielectric material.
13. manufacture method as claimed in claim 12 is characterized in that, described clearance wall adopts silicon nitride.
14. the manufacture method of an application rights requirement 1 forms the method for MOS transistor, wherein, after described Semiconductor substrate is carried out annealing in process, also comprises:
In described gate openings, fill up the gate metal material;
The described gate metal material of planarization keeps the gate metal material in the gate openings.
15. the method for formation MOS transistor as claimed in claim 14, wherein, described gate metal material comprises Ti, Co, Ni, Al, W and alloy thereof or metal silicide.
16. the method for formation MOS transistor as claimed in claim 14 wherein, before forming described gate metal material, covers the workfunction metal material in described gate openings conformal.
17. the method for formation MOS transistor as claimed in claim 16, wherein, described workfunction metal material comprises TiN, TiAlN, TaN, TaAlN or TaC.
CN 201010275191 2010-09-02 2010-09-02 MOS (metal oxide semiconductor) transistor and manufacturing method of MOS transistor gate dielectric layer Active CN102386083B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN 201010275191 CN102386083B (en) 2010-09-02 2010-09-02 MOS (metal oxide semiconductor) transistor and manufacturing method of MOS transistor gate dielectric layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN 201010275191 CN102386083B (en) 2010-09-02 2010-09-02 MOS (metal oxide semiconductor) transistor and manufacturing method of MOS transistor gate dielectric layer

Publications (2)

Publication Number Publication Date
CN102386083A CN102386083A (en) 2012-03-21
CN102386083B true CN102386083B (en) 2013-09-11

Family

ID=45825377

Family Applications (1)

Application Number Title Priority Date Filing Date
CN 201010275191 Active CN102386083B (en) 2010-09-02 2010-09-02 MOS (metal oxide semiconductor) transistor and manufacturing method of MOS transistor gate dielectric layer

Country Status (1)

Country Link
CN (1) CN102386083B (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103839813B (en) * 2012-11-21 2017-05-17 中芯国际集成电路制造(上海)有限公司 MOS transistor and method for forming same
CN105990119B (en) * 2015-02-16 2019-06-28 中芯国际集成电路制造(上海)有限公司 Manufacturing method of semiconductor device, semiconductor devices and electronic device
CN106816413B (en) * 2015-11-27 2019-09-27 中芯国际集成电路制造(上海)有限公司 A kind of manufacturing method of semiconductor devices
CN110034022B (en) * 2018-01-12 2022-04-15 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1790742A (en) * 2004-11-02 2006-06-21 国际商业机器公司 Damascene gate field effect transistor with an internal spacer structure
CN1846313A (en) * 2003-09-09 2006-10-11 国际商业机器公司 Structure and method for metal replacement gate of high performance device
CN101253602A (en) * 2005-08-30 2008-08-27 英特尔公司 Semiconductor device having a metal gate electrode formed on an annealed high-k gate dielectric layer

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1846313A (en) * 2003-09-09 2006-10-11 国际商业机器公司 Structure and method for metal replacement gate of high performance device
CN1790742A (en) * 2004-11-02 2006-06-21 国际商业机器公司 Damascene gate field effect transistor with an internal spacer structure
CN101253602A (en) * 2005-08-30 2008-08-27 英特尔公司 Semiconductor device having a metal gate electrode formed on an annealed high-k gate dielectric layer

Also Published As

Publication number Publication date
CN102386083A (en) 2012-03-21

Similar Documents

Publication Publication Date Title
US10396070B2 (en) Fin-shaped field effect transistor and capacitor structures
US9842930B2 (en) Semiconductor device and fabrication method thereof
US8809962B2 (en) Transistor with reduced parasitic capacitance
CN103022102B (en) Multilayer for ultra-thin interface dielectric layer removes metal gate stacks part
US8114746B2 (en) Method for forming double gate and tri-gate transistors on a bulk substrate
US9627245B2 (en) Methods of forming alternative channel materials on a non-planar semiconductor device and the resulting device
CN104916542A (en) Structure and method for semiconductor device
CN104752503A (en) Mechanisms for forming finfets with different fin heights
CN102460681A (en) Adjusting threshold voltage for sophisticated transistors by diffusing a gate dielectric cap layer material prior to gate dielectric stabilization
TWI593113B (en) Semiconductor devices and method for forming the same
CN102087979A (en) High-performance semiconductor device and method for forming same
CN105321883A (en) Method for fabricating semiconductor device
JP2011146465A (en) Semiconductor device and manufacturing method of the same
CN107104139A (en) Semiconductor devices and its manufacture method
CN102956454A (en) Semiconductor structure and manufacturing method thereof
CN105470133A (en) Semiconductor device manufacturing method
CN102386083B (en) MOS (metal oxide semiconductor) transistor and manufacturing method of MOS transistor gate dielectric layer
CN109786251A (en) The method for forming semiconductor structure
CN102110609B (en) High-performance semiconductor device and forming method thereof
US9343572B1 (en) High-voltage semiconductor device and method for manufacturing the same
US8884346B2 (en) Semiconductor structure
CN102737996B (en) A kind of method making transistor and semiconductor device
CN104112666A (en) Semiconductor device and manufacturing method thereof
CN104143534B (en) Method, semi-conductor device manufacturing method
US8486794B1 (en) Method for manufacturing semiconductor structure

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
ASS Succession or assignment of patent right

Owner name: SEMICONDUCTOR MANUFACTURING (BEIJING) INTERNATIONA

Effective date: 20121106

C41 Transfer of patent application or patent right or utility model
TA01 Transfer of patent application right

Effective date of registration: 20121106

Address after: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18

Applicant after: Semiconductor Manufacturing International (Shanghai) Corporation

Applicant after: Semiconductor Manufacturing International (Beijing) Corporation

Address before: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18

Applicant before: Semiconductor Manufacturing International (Shanghai) Corporation

C14 Grant of patent or utility model
GR01 Patent grant