CN102376765A - 半导体器件及其制作方法 - Google Patents

半导体器件及其制作方法 Download PDF

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CN102376765A
CN102376765A CN2011101817088A CN201110181708A CN102376765A CN 102376765 A CN102376765 A CN 102376765A CN 2011101817088 A CN2011101817088 A CN 2011101817088A CN 201110181708 A CN201110181708 A CN 201110181708A CN 102376765 A CN102376765 A CN 102376765A
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semiconductor device
groove
substrate
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CN102376765B (zh
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马丁·加内特
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Chengdu Monolithic Power Systems Co Ltd
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Abstract

公开了一种沟槽接触型垂直分立器件及其制作方法。在一个实施例中，本发明涉及垂直分立器件，该垂直分立器件的沟槽在其顶面，沟槽内填充导电材料。垂直分立器件的漏极或阴极电连接至器件的顶面，因此其面积较小，且RON×AREA值也较小。

Description

半导体器件及其制作方法
技术领域
本发明涉及分立半导体器件，更具体地说，本发明涉及沟槽接触型垂直分立半导体器件(vertical discrete semiconductor device with trench contacts)及其制作方法。
背景技术
在一些模拟芯片应用场合，常常将集成电路晶片和分立器件晶片封装在一起，这些分立器件晶片包括金属氧化物半导体场效应晶体管(MOSFET)，结型场效应晶体管(JFET)和/或其他合适的器件。在一些应用场合，常常需要把电路晶片和分立器件晶片的接触垫(contact Pad)集成在同一侧。横向器件很容易满足此要求，比如横向双扩散金属氧化物半导体场效应晶体管(LDMOS)。但是，在其他一些应用场合，很难满足此要求。例如，分立器件常要求较低的导通电阻(RON)和较小的面积(AREA)，因此参数RON×AREA非常重要。因为漏极或阴极常包括整个晶片底面，所以诸如集成了肖特基二极管的垂直金属氧化物半导体场效应晶体管(MOSFET)、垂直结型场效应晶体管(JFET)或场效应晶体管(FET)相比于LDMOS，能够降低成本并减小导通电阻RON。因此，在一些共同封装的产品应用场合，需要垂直分立晶片的底面漏/阴极通过过孔与晶片的顶面接触。
图1A所示为根据现有技术的作为示例的常规垂直MOSFET 100的截面图。MOSFET器件100包括器件底面的重掺杂N+衬底10，作为漏极。而在器件顶面，栅区12、P型体区13以及N型源区11均制作在N-外延层15中。在如图1A所示的实施例中，通过在N-外延层15的沟槽中填充多晶硅形成栅区12。栅区12沟槽的侧壁四周为栅极氧化物120，其将栅区12同P型体区13和N-外延层15隔开。在体区13内从顶面向下形成N+源区11，源区11与栅区12的栅极氧化物120相邻。
源区11通过导电互连111连接在一起，并电连接至一个或者多个源接触垫1110，从而形成源电极S。栅区12通过导电互连(未示出)连接在一起，并连接至一个或多个栅接触垫，从而形成栅电极G。与衬底10的整个底面接触的金属层形成漏电极D。在一个实施例中，导电互连和接触垫由金属组成，比如金属铜。源区11和体区13被短接。如图1A所示，沟槽112位于N+源区11之间，并延伸进P型体区13，接着将在沟槽112中淀积金属形成源接触和源极互连111。体区13和源区11被电短接，并通过源极互连111被布置在源接触垫1110上。
如图1B所示，在其他常规器件中，可通过延伸的源接触对源区11和体区13进行短接。在这个方法中，源极互连111B具有延伸的接触区，该接触区与源区11和体区13电接触。图1C中，在P型体区13和源区11上可选地形成P+体接触区131，以短接源区11和体区13。但是，由于P+体接触区需要较大的接触，因此图1C中实施例的单元面积比图1A中的实施例的大。
图2所示为根据现有技术的一种常规分立垂直器件200的俯视图。源板21和栅板22布置在顶面上，源板21通过互连与垂直器件的源区上层接触。在一个实施例中，源板形成部分互连结构。栅板22通过互连与垂直器件的栅区上层接触。在源板21上形成源接触垫211，在栅板22上形成栅接触垫221。
同样地，垂直器件的栅极和源极通过分离的栅板和源板隔开，互相电绝缘。垂直器件的漏/阴极在分立器件晶片200衬底的底面，同时漏板布置在分立器件晶片200的底面。在典型器件中，在整个底面覆盖一层金属作为漏极。
发明内容
本发明提供了一种半导体器件，包括垂直器件和一个沟槽。其中，垂直器件的衬底在底面，且具有与底面相对的顶面；沟槽填充导电材料，从顶面延伸至底面衬底。
本发明所述的半导体器件，导电材料是钨。
本发明所述的半导体器件，衬底作为漏极。
本发明所述的半导体器件，垂直器件是垂直MOSFET。
本发明所述的半导体器件，进一步包括在器件顶面上的多个具有第一掺杂类型的源区，以及至少一个栅区。
本发明所述的半导体器件，进一步包括：外延层，具有第一掺杂类型且形成在衬底上；多个体区，具有第二掺杂类型。体区和沟槽均形成在外延层中，且每个源区分别形成在每个体区内。
本发明所述的半导体器件，栅极是沟槽栅极，形成在外延层中，栅极被覆盖一层氧化物并被填充多晶硅。
本发明所述的半导体器件，进一步包括延伸进体区的多个接触层，接触层端短接源区和体区。
本发明所述的半导体器件，沟槽在双梳形结构中。
本发明所述的半导体器件，进一步包括：栅板，形成于器件顶面；漏板，形成在器件顶面；以及多个源板，形成在器件顶面。
本发明所述的半导体器件，漏板在双梳形结构中。
本发明所述的半导体器件，漏板具有多个漏接触垫，分别对应在双梳形结构的每个指形上。
本发明所述的半导体器件，每个栅板和栅区电短接，每个漏板和导电材料电短接，每个源板和源区电短接。
本发明所述的半导体器件，垂直器件是垂直JFET。
本发明所述的半导体器件，垂直器件是具有集成肖特基二极管的垂直FET。
本发明还提供了一种制造半导体器件的方法，包括：形成垂直器件，垂直器件具有包含衬底的底面和与底面相对的顶面；形成从顶面向底面延伸的沟槽，并延伸进衬底；以及用导电材料填充沟槽。
本发明所述的方法，其特征在于，填充沟槽包括向沟槽中填充钨。
本发明所述的方法，进一步包括，采用普通掩膜形成沟槽并填充沟槽。
本发明所述的方法，形成垂直器件包含：在N+衬底上形成N-外延层；刻蚀N-外延层形成多个具有侧壁的沟槽；在沟槽侧壁形成二氧化硅；用多晶硅填充沟槽形成多个栅区；在N+衬底中扩散P型物质，形成多个体区；以及在体区中扩散N型物质，形成多个源区。
本发明所述的方法，进一步包括在顶面形成栅板、源板和漏板。其特征在于，栅板与栅区结束，源板和源区接触，漏板和沟槽中的导电材料接触。
附图说明
附图作为说明书的一部分，对本发明实施例进行说明，并与实施例一起对本发明的原理进行解释。为了更好地理解本发明，将根据以下附图对本发明进行详细描述。
图1A-图1C所示为根据现有技术的常规垂直MOSFET示意图。
图2为图1A所示常规垂直MOSFET布图。
图3所示为根据本发明实施例的多晶片封装示意图。
图4A所示为根据本发明实施例的一个沟槽接触型垂直MOSFET的截面图。
图4B所示为根据本发明实施例的另一个沟槽接触型垂直MOSFET的截面图。
图5A所示为根据本发明实施例的一个沟槽接触型JFET的截面图。
图5B所示为根据本发明实施例的另一个沟槽接触型JFET的截面图。
图6所示为根据本发明实施例的一个垂直半导体器件的布图。
图7A-图7E为根据本发明实施例的另一个垂直半导体器件制作工艺示意图。
在不同的附图中，相同的参数符号代表相同的器件，同时应了解，这些附图并不是完全按比例绘制的。
具体实施方式
本发明将在下文中结合附图全面描述顶面接触型垂直半导体器件及其制造方法的各个实施例。在下面，术语“垂直半导体器件”一般涉及到MOSFET、JFET、FET、双扩散MOSFET(VDMOS)和/或其他合适的半导体器件。虽然本发明阐述了大量实施例以及制作方法，但应理解为这并非意指将本发明限定于参考图3-7E给出的这些实施例中，相反，本发明意在涵盖由所附权利要求所界定的本发明精神和范围内所定义的各种可选方案、修改方案和等同方案。
图3所示为根据本发明实施例的多晶片封装300的示意图。如图3所示，封装300包含与集成电路晶片32共同封装的分立垂直器件晶片31。在一个实施例中，垂直器件晶片31包含功率分立器件，诸如VDMOS或垂直JFET。集成电路晶片32可包含控制功率分立电路开和关的控制器。垂直器件晶片31的底面310充当漏/阴极。
漏/阴电极的漏/阴极接触垫312、源电极的源极接触垫以及栅电极的栅极接触垫形成在同一表面上，其被称为顶面。为了在垂直器件晶片31的顶面形成漏接触垫312，同时又具有较低的导通电阻，可通过在沟槽中填充导电材料(比如：钨)，使垂直器件的漏/阴极电连接至顶面。
如图3所示，通过沟槽将漏极接触至顶面，垂直器件晶片31和集成电路晶片32粘贴在引线框30上，并通过键合线(bonding wire)与同一边引线33相接。在一个实施例中，可通过在垂直器件晶片31和基底盘(paddle)30之间放置绝缘电介质材料，使垂直器件晶片31的衬底底面与引线框的基底盘30电绝缘。这样，垂直器件晶片31和集成电路晶片32放置在相同基底盘30上，有利于在顶面为集成电路晶片32供电，在底面为分立器件晶片31供电。垂直分立器件晶片31的漏极接触垫312和集成电路晶片32的漏极接触垫322的顶面，通过键合线311和321连接至引线33。
图4A所示为根据本发明实施例的沟槽接触型垂直MOSFET的截面图。与图1A所示的垂直MOSFET 100相比，垂直MOSFET 400进一步包括填充导电材料440的沟槽44，用于将衬底40连接至顶面。因此，漏电极D从底面转至顶面。
在所示实施例中，垂直MOSFET 400为具有底面衬底40的VDMOS。底面衬底40为N型重掺杂，用作VDMOS的漏极。N-外延层45形成在N+衬底40上，在N-外延层45中，从顶面向下形成体区43、源区41和栅区42。
在一个实施例中，在N-外延层45中形成用于栅区42的沟槽，将在栅极沟槽的侧壁和底部形成栅极氧化物420，接着将在沟槽中填充多晶硅以形成栅区42。此外，毗邻栅区42的栅极氧化物420形成P型体区43。接着在体区43中顶面上形成源区41。
在一个实施例中，源接触延伸过源区41进入体区43，并被填充金属形成源极互连层411，从而使得体区43和源区41被短接。在另一个实施例中，通过延长接触对体区43和源区41进行短接，如图1B和1C。
源区41通过导电互连411互连在一起作为源电极S。栅区42通过导电互连(未示出)层互连接在一起作为栅电极G。当给栅区42施加高的栅极电压时，靠近栅区42的P型体区43转换为N型，形成N型通道。当施加正的源漏电压VSD时，电流通过该通道从源极41流向N+漏极40。
继续参见图4A，垂直MOSFET 400进一步包括从顶面延伸至N+衬底40的沟槽44。在沟槽44中填充导电材料，将垂直MOSFET 400的漏极40连接至垂直MOSFET 400的顶面。在一个实施例中，导电材料为钨440，漏极衬底40通过钨440连接至顶面。
在一个实施例中，如图4B所示的半导体器件400B，沟槽44形成在N+区和两个栅区42之间。对于这个实施例，在光刻掩膜制作半导体器件400B的源区41和栅区42时，可选择与图1A所示垂直MOSFET 100相同的掩膜。
用于连接衬底40和顶面的沟槽44较窄，沟槽44的深度部分地取决于垂直MOSFET 400的深度。在一个实施例中，对于击穿电压为30V的垂直MOSFET，其刻蚀深度为2～3μm，宽度为0.5～1μm。虽然可以通过深扩散N型重掺杂使衬底40连接至垂直MOSFET 400的顶面，但是横向扩散会导致形成较大接触面积。相对于深扩散，使用钨填充沟槽44用以与N+衬底连接，由于宽度较小，电阻较低，又无横向扩散，形成的接触面积较小。
图4A所示的垂直分立器件采用沟槽栅极DMOS器件作为一个实施例。但是，其他垂直器件，比如常规的薄膜栅极VDMOS、垂直JFET、肖特基二极管垂直FET或其他衬底漏/阴极器件也可运用在本发明所述的沟槽连接顶面和漏/阴极的场合。
在本发明所述的另一个实施例中，垂直器件也可以是如图5A和图5B所示的垂直JFET器件。垂直JFET 500包括作为漏极的底面衬底50、N型重掺杂源区51、栅区52以及至少一个从顶面开至衬底50的沟槽。在沟槽54中填充导电材料，比如钨540，用于将衬底50连接至顶面。垂直JFET 500进一步包括生长在衬底50上的N-外延层55，其中，栅区52和源区51形成在N-外延层55中。
器件正常工作时，栅区52被浮置，在源区51和衬底50之间将形成一条导电通道，当在漏极和源极之间施加正或负的漏源电压VDS，电流将从源区51流至漏极50或从漏极50流至源区51。当在栅区52施加负电压VGD，N型外延层55靠近栅区52的区域将被耗尽，源极和漏极之间的导通电阻RON增大，当栅区52施加足够的负电压时，导电通道被完全夹断。对于垂直JFET 500，当其正常工作时，通过沟槽将漏极连接至顶层给器件增加了较小的电阻。
在一个实施例中，如图5B所示的半导体器件500B，在N型区和两个栅区52之间制作沟槽54。对于这个实施例，对于没有顶层漏极的垂直JFET，半导体器件500B在用光刻胶掩膜制作源区51和栅区52时，可用相同的掩膜。
图6所示为根据本发明一个实施例的半导体器件600的顶面布图。在一个实施例中，垂直器件600可以是图4A中所示的VDMOS 400。在另一个实施例中，垂直器件600可以是图5A所示的垂直JFET 500。垂直器件600也可以是其他具有底面漏极或阴极的垂直分立器件。如图6所示布图，垂直器件600包括栅板(gate plate)62、多个源板61和漏板64。与图2所示布图不同，半导体器件600的布图进一步包括漏板64，其环绕在布图四周呈双梳形(bi-comb pattern)，源板被分隔为源板61的多个分离段。
栅板62、源板61以及漏板64由金属构成，比如铜。在一个实施例中，栅板62连接至垂直器件600的栅区，每个源板61连接至垂直器件600的源区。换句话说，在源板61下面，源区也因此被分隔为多个N+源区。漏板64通过填充导电材料(比如：钨)的沟槽连接至垂直器件600的衬底漏极。在一个实施例中，栅板62、源板61和漏板64均连接至栅区，其中，垂直器件600的源区和钨通过各自的互连层连接至栅区。在另一个实施例中，栅板62、源板61和漏板64包括部分互连层。
继续参见图6，在一个实施例中，在漏板64下面，填充暗灰色的图格所示为沟槽640，其达到垂直器件600的衬底并被填充钨，。因此，垂直器件600的衬底和顶层漏板64通过钨短接。如图6所示实施例中，沟槽/漏板64布置为双梳形，其包括两个梳形642和643。左梳形642具有左边缘线6421和多个指形结构6422，其中多个指形结构6422从左边缘线6421单向向右延伸至栅板62，但未到达栅区62的区域。右梳形643具有右边缘线6431和多个指形结构6432，其中多个指形结构6432从右边缘线6431单向向左延伸至栅板62，但未到达栅区62的区域。在所示的实施例中，两个梳形结构642和643互连在一起作为一个闭环。由于在沟槽64中填充钨，因此垂直器件600底面衬底上的漏极被连接至顶层。在一个双梳形结构实施例中，用于填充沟槽64的钨分散在整个布线板上，因此，每一部分上增添的量很小，电阻较低，且漏极连接至顶层的RON×AREA值较小。在如图4A和图6所示的实施例中，晶片面积仅为扩散解决方案下晶片面积的33％。
继续参见图6，在一个实施例中，将在漏板64上靠近芯片边缘的地方形成漏接触垫641，用于导线键合，其中每个双梳形结构的指形结构上都将形成一个漏接触垫641。同样，在源板61的每一段处将形成源接触垫611，用于导线键合。在其他实施例中，接触垫641、611和621还可通过凸点连接至引线框或其他部件上。由于通过沟槽连接至顶层的漏极布置在整个布线层上，源极被漏板/沟槽62分为多个分立的区域。
击穿电压30V且底面漏极接触的常规VDMOS，其RON×AREA值为7～15毫欧.平方毫米，这取决于多个变化的参数，比如电容，非钳位感性开关等。而通过深扩散方案的具有顶层漏极的LDMOS或普通VDMOS，其RON×AREA值为25～35毫欧.平方毫米。如图4A所示的通过填充钨的沟槽将漏极连接至顶层的垂直VDMOS，其RON×AREA值为10～25毫欧.平方毫米，这小于LDMOS和深扩散方案的。
在一个实施例中，参见图2，垂直分立FET的面积约为2mm2，VDMOS的阻值为5毫欧，所以其RON×AREA值为10毫欧.平方毫米。参见图5，源的每一段约为75毫欧。每一块N+衬底和垂直沟槽的阻值约为35～40毫欧，因此每一块总的导通电阻值RON为110～115毫欧而非75毫欧，此处N+衬底和垂直沟槽组成的RON×AREA值减小了50％。而由于漏板和漏接触垫减小的面积约为15～20％，因此总的RON×AREA值减小了70％。因此，在这个实施例中，对于RON×AREA值为10毫欧.平方毫米，击穿电压为30V的分立FET，通过使用较窄沟槽的方法将分立FET的N+衬底漏极连接至顶层，其RON×AREA值约变为17毫欧.平方毫米。
图6所示的布图仅用于示例说明，漏板64可包含任何数量的指形结构。在本发明的另一个实施例中，整个布图包括多个重复的如图6所示的图形结构，图6的布图只是整个布图的一部分。
图7A-图7E所示为根据本发明实施例，由沟槽将漏极连接至顶层的垂直器件的制作方法。在图7A中，将制作垂直半导体器件710，其中，垂直器件可以是任何具有底面衬底作为漏极或阴极的器件，比如，具有底面阴极的VDMOS，垂直JFET或垂直FET。
图7A所示垂直半导体器件710为沟槽栅极VDMOS。VDMOS包括N+衬底70作为漏极。在衬底70上将形成N-外延层75，在N-外延层75里，将形成P型体区73，N+源区71和填充多晶硅的沟槽栅区72。氧化层720将每一个栅区72同体区73和外延层75隔开。
在一个实施例中，制作方法进一步包括：在N+衬底70上制作N-外延层75，刻蚀外延层75的顶面形成栅极72的沟槽；在沟槽的侧壁生长氧化层720；在沟槽中填充多晶硅形成栅区72；扩散P型物质形成体区73，其中体区73与栅区72的栅极氧化层720相邻，不会延伸至栅区72下面；扩散N型物质进入体区表面区域形成N+源区71。在一个实施例中，体区73和源区71可通过接触沟槽短接，如图7E所示。
如图7B所示，将在器件顶面701形成电介质层76。如图7C所示，在半导体器件上涂覆一层光刻胶742，接着用另一层掩膜图刻形成沟槽74的开孔。通过开孔将各向异性刻蚀N-外延层75，形成窄而深的沟槽74到达N+衬底70。在另一个实施例中，可采用氮化物或氧化物之类的硬掩膜，在硬掩膜和图刻后，通过硬掩膜的开孔各相异性刻蚀外延层75和部分衬底70。在一个实施例中，沟槽74顶层的图样是双梳形样式，如图6所示。在一个实施例中，各向异性刻蚀可为深反应离子刻蚀(Deep Reactive Ion Etching，DRIE)。
如图7D所示，将在沟槽74中填充导电材料740。在一个具体实施例中，导电材料740包含钨。在一个实施例中，将在刻蚀沟槽74中和电介质层76的表面上均淀积钨，随后，将通过钨刻蚀或化学机械抛光(Chemical MechanicalPolish，CMP)技术移除电介质层76上的钨。填充满钨的沟槽用于将底面衬底70的漏极电连接至顶面。在另一个可替代的实施例中，将在形成电介质层76之前形成沟槽74，并在沟槽中填充导电材料。
如图7E所示，将用另一个掩膜形成接触和互连层。光刻工艺后，将刻蚀层间电介质层76。在所示实施例中，进一步刻蚀N+源区71形成接触沟槽到达P型体区73。在一个实施例中，在刻蚀沟槽中淀积钨形成接触层，用于电短接体区73和源区71。接着将填充和刻蚀金属形成互连层和电极盘。电极盘包括栅板、源板和漏板，分别与栅区、源区和导电材料填充的沟槽74电接触，如图6所示。在一个实施例中，垂直器件制作方法进一步包括：分别在栅板、源板和漏板上形成接触垫。
如图7A至7E所示实施例中，形成垂直器件的顶面漏极仅用一个额外的掩膜，因此，器件在维持低RON×AREA值的同时，附加成本较低。虽然在实施例的说明书中有大量的单复数形式的术语，但其并非被限制于单数或复数，任何合适的数量都可采纳。图中所示的实施例采用N型器件进行说明，但是，P型器件也包括在本发明技术中。本领域技术人员均了解，对于一个P型器件，其掺杂类型正好和N型器件相反。
虽然上面详细的描述了本发明具体的实施例，并指明了最优方案，但是不论先前描述的多详细，本发明仍有许多其他实施方式。在实际执行时可能有些变化，但仍然包含在本发明主旨范围内，因此，本发明旨在包括所有落入本发明和所述权利要求范围及主旨内的替代例、改进例和变化例等。

Claims (20)

1.一种半导体器件，包括：
垂直器件，所述垂直器件的衬底在底面，且具有与底面相对的顶面；
沟槽，从所述顶面延伸至所述底面衬底，采用导电材料填充所述沟槽。
2.如权利要求1所述半导体器件，其中，所述导电材料是钨。
3.如权利要求1所述半导体器件，其中，所述衬底作为漏极。
4.如权利要求1所述半导体器件，其中，所述垂直器件是垂直金属氧化物半导体场效应管。
5.如权利要求3所述半导体器件，进一步包括在器件顶面上的至少一个栅区和具有第一掺杂类型的多个源区，所述衬底为第一掺杂类型。
6.如权利要求5所述半导体器件，进一步包括：
外延层，具有第一掺杂类型且形成在衬底上；
多个体区，具有第二掺杂类型；以及
其中，所述体区和所述沟槽均形成在外延层中，且每个所述源区分别形成在每个所述体区内。
7.如权利要求6所述半导体器件，其中，所述栅极是沟槽栅极，形成在外延层中，所述栅极被内衬了一层氧化物并被填充多晶硅。
8.如权利要求6所述半导体器件，进一步包括延伸进所述体区的多个接触，其中，所述接触对所述源区和体区进行短接。
9.如权利要求5所述半导体器件，其中，所述沟槽形成为双梳形结构。
10.如权利要求1所述半导体器件，进一步包括：
栅板，形成于器件顶面；
漏板，形成在器件顶面；以及
多个源板，形成在器件顶面。
11.如权利要求10所述半导体器件，其中，所述漏板形成为双梳形结构。
12.如权利要求10所述半导体器件，其中，所述漏板具有多个漏接触垫，分别对应于双梳形结构的每个指形。
13.如权利要求10所述半导体器件，其中，每个所述栅板和所述栅区电短接，每个所述漏板和所述导电材料电短接，每个所述源板和所述源区电短接。
14.如权利要求1所述半导体器件，其中，所述垂直器件是垂直结型场效应管。
15.如权利要求1所述半导体器件，其中，所述垂直器件是具有集成肖特基二极管的垂直场效应管。
16.一种制造半导体器件的方法，包括：
形成垂直器件，所述垂直器件具有包含衬底的底面和与底面相对的顶面；
形成从所述顶面向所述底面延伸的沟槽，并延伸进衬底；以及
用导电材料填充沟槽。
17.如权利要求16所述方法，其中，填充所述沟槽包括向沟槽中填充钨。
18.如权利要求16所述方法，进一步包括，使用相同的掩膜用于形成沟槽和填充沟槽。
19.如权利要求16所述方法，其中，形成垂直器件包含：
在N+衬底上形成N-外延层；
刻蚀所述N-外延层以形成具有侧壁的多个沟槽；
在所述沟槽侧壁形成二氧化硅；
用多晶硅填充所述沟槽形成多个栅区；
在N+衬底中扩散P型物质，形成多个体区；以及
在所述体区中扩散N型物质，形成多个源区。
20.如权利要求19所述方法，进一步包括在顶面形成栅板、源板和漏板，其中，所述栅板与栅区接触，所述源板和源区接触，所述漏板和沟槽中的导电材料接触。
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