CN102376642A - Silicon through hole technology - Google Patents
Silicon through hole technology Download PDFInfo
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- CN102376642A CN102376642A CN2011103798630A CN201110379863A CN102376642A CN 102376642 A CN102376642 A CN 102376642A CN 2011103798630 A CN2011103798630 A CN 2011103798630A CN 201110379863 A CN201110379863 A CN 201110379863A CN 102376642 A CN102376642 A CN 102376642A
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Abstract
The invention provides a silicon through hole technology comprising the steps of: providing a silicon slice with a front surface and a back surface, wherein a deep slot is formed on the silicon slice; connecting the front surface of the silicon slice with a first silicon slice carrier, thinning the back surface of the silicon slice until the bottom of the deep slot is exposed so as to form a silicon through hole; cleaning the silicon slice; connecting the back surface of the silicon slice with a second silicon slice carrier, and removing the first silicon slice carrier; sequentially forming an insulation layer, a barrier layer and a copper seed layer on the front surface of the silicon slice; filling the silicon through hole by electroplating copper; connecting a third silicon carrier on the electroplated copper, removing the second silicon carrier, and electroplating copper on the back surface of the silicon slice; and removing the third silicon slice carrier. According to the silicon through hole technology provided by the invention, the back surface of the silicon slice is thinned until the bottom of the deep slot is exposed so as to form the silicon through hole, and the silicon slice is cleaned so as to remove polymer and particles in the through hole much better, therefore, the reliability of the silicon through hole is enhanced, and finally the product yield is increased.
Description
Technical field
The present invention relates to the manufacturing technology field of semiconductor integrated circuit, relate in particular to a kind of silicon via process.
Background technology
Along with the integrated level of integrated circuit improves constantly, semiconductor technology also continues develop rapidly.It mainly is to take to reduce minimum feature size that existing integrated level improves, and making can integrated more element in given zone.But the above-mentioned minimum feature size that reduces substantially basically all is that 2D (two dimension) is integrated; Specifically; The element that is integrated exactly all is positioned at the surface of semiconductor crystal wafer (wafer), but along with integrated circuit technique gets into after 32 nanometers even the 22 nanometer technology platforms, aspects such as system complexity, equipment investment cost sharply rise; Make and utilize the hyundai electronics encapsulation technology to realize that highdensity 3D (three-dimensional) is integrated, become the system-level integrated important technology approach of microelectronic circuit (comprising MEMS).
In numerous 3D encapsulation technologies; Silicon through hole (Through-Silicon Via; TSV) technology becomes the focus of present research, and the TSV technology has following advantage: interconnection length can shorten to chip thickness and equate, adopts the logic module of the logic module substitution level distribution of vertical stacking; Significantly reduce RC and postpone and inductive effect, improve the transmission of digital data transmission speed and microwave; Realize the connection of high density, high-aspect-ratio, thereby can realize the complicated multi-disc total silicon system integration that density is than high times of the current physical package that is used for advanced multichip module; Simultaneously more energy-conservation, expection TSV can reduce chip power-consumption about 40%.
The difficult point of TSV technology is etching, cleaning and the filling of silicon through hole, and this mainly is because the high-aspect-ratio of silicon through hole causes.Because the high-aspect-ratio of TSV through hole, the polymer of via bottoms and particle are difficult to be cleaned totally, these polymer and particle residue can cause the step coverage of insulating barrier, barrier layer and Seed Layer poor in through hole, thereby cause the inefficacy of through hole.
Summary of the invention
Technical problem to be solved by this invention has provided a kind of silicon via process, to solve because high-aspect-ratio makes the through hole interpolymer finally cause the problem of through hole inefficacy with particle residue.
In order to solve the problems of the technologies described above, technical scheme of the present invention is: a kind of silicon via process is provided, has comprised: the silicon chip that comprises front and back is provided, on said silicon chip, forms deep trench; The front of said silicon chip is connected with first silicon chip carrier, and expose the bottom that said silicon chip back is thinned to said deep trench, forms the silicon through hole; Said silicon chip is cleaned; Said silicon chip back is connected with second silicon chip carrier, removes said first silicon chip carrier; On the front of said silicon chip, form insulating barrier, barrier layer and copper seed layer successively; Fill said silicon through hole through the method for electro-coppering; On the copper of electroplating, connect the 3rd silicon chip carrier, remove said second silicon chip carrier, in said silicon chip back electro-coppering; Remove said the 3rd silicon chip carrier.
Further, the cleaning fluid that uses when said silicon chip is cleaned is the mixture of ammonium hydroxide and hydrogen peroxide solution, and the time of cleaning is 20s～120s.
Further, the diameter of said deep trench is 1 micron～50 microns, and the degree of depth of said deep trench is 10 microns～500 microns.
Further, the thickness of said insulating barrier is 5A～500A.
Further, the thickness on said barrier layer is 5A～500A.
Further, the thickness of said copper seed layer is 500A～3000A.
Silicon via process provided by the invention, expose the bottom that silicon chip back is thinned to deep trench, forms the silicon through hole; Silicon chip is cleaned; Can better remove polymer and particle in the silicon through hole, thereby improve the reliability of silicon through hole, finally promote the product yield.
Description of drawings
Fig. 1 is the flow chart of steps of the silicon via process that provides of the embodiment of the invention;
Fig. 2 A～2F is the pairing cross-sectional view of silicon via process that the embodiment of the invention provides.
Embodiment
Below in conjunction with accompanying drawing and specific embodiment a kind of silicon via process that the present invention proposes is done further explain.According to following explanation and claims, advantage of the present invention and characteristic will be clearer.What need explanation is, accompanying drawing all adopts the form of simplifying very much and all uses non-ratio accurately, only is used for conveniently, the purpose of the aid illustration embodiment of the invention lucidly.
Core concept of the present invention is; The silicon via process that provides, expose the bottom that silicon chip back is thinned to deep trench, forms the silicon through hole; Silicon chip is cleaned; Can better remove polymer and particle in the silicon through hole, thereby improve the reliability of silicon through hole, finally promote the product yield.
Fig. 1 is the flow chart of steps of the silicon via process that provides of the embodiment of the invention.With reference to Fig. 1, the silicon via process that provides comprises:
S11, the silicon chip that comprises front and back is provided, on said silicon chip, forms deep trench;
S12, the front of said silicon chip is connected with first silicon chip carrier, expose the bottom that said silicon chip back is thinned to said deep trench, forms the silicon through hole;
S13, said silicon chip is cleaned;
S14, said silicon chip back is connected with second silicon chip carrier, removes said first silicon chip carrier;
S15, on the front of said silicon chip, form insulating barrier, barrier layer and copper seed layer successively;
S16, fill said silicon through hole through the method for electro-coppering;
S17, on the copper of electroplating, connect the 3rd silicon chip carrier, remove said second silicon chip carrier, in said silicon chip back electro-coppering;
S18, said the 3rd silicon chip carrier of removal.
To combine cross-sectional view that silicon via process of the present invention is described in more detail below; The preferred embodiments of the present invention have wherein been represented; Should be appreciated that those skilled in the art can revise the present invention described here, and still realize advantageous effects of the present invention.
Fig. 2 A～2F is the pairing cross-sectional view of silicon via process that the embodiment of the invention provides.With reference to Fig. 2 A and integrating step S11; The silicon chip 21 that comprises front and back is provided, on said silicon chip 21, forms deep trench 22, in the present embodiment; The diameter of said deep trench 22 is 1 micron～50 microns, and the degree of depth of said deep trench 22 is 10 microns～500 microns; With reference to Fig. 2 B and integrating step S12 and step S13, the front of silicon chip 21 is connected with first silicon chip carrier 23, the bottom of thinning back side to the deep trench 22 of silicon chip 21 is exposed; Form the silicon through hole; Silicon chip 21 is cleaned, and in the present embodiment, the cleaning fluid that uses is the mixture of ammonium hydroxide and hydrogen peroxide solution; The time of cleaning remains on 20s～120s; Can remove polymer and the particle in the silicon through hole through cleaning, it should be appreciated by those skilled in the art that said cleaning fluid also can be the mixture of hydrochloric acid and hydrogen peroxide solution;
With reference to Fig. 2 C and integrating step S14, the back side of said silicon chip 21 is connected with second silicon chip carrier 24, remove said first silicon chip carrier 23;
With reference to Fig. 2 D and integrating step S15 and step S16, through the method formation insulating barrier 25 of chemical vapour deposition (CVD), its thickness is 5A～500A; Through the method barrier layer 26 of physical vapour deposition (PVD), said barrier layer can be one or more layers, in the present embodiment; Said barrier layer is an individual layer; Thickness is 5A～500A, and the method through physical vapour deposition (PVD) forms copper seed layer in the bottom of silicon through hole, and its thickness is 500A～3000A; Fill said silicon through hole through the method for electro-coppering, make and fill full ground floor copper 27 in the silicon through hole;
With reference to Fig. 2 E and integrating step S17, on the ground floor copper of electroplating 27, connect the 3rd silicon chip carrier 28, remove said second silicon chip carrier 24, in the electro-coppering of the back side of said silicon chip 21, to form second layer copper 29;
With reference to Fig. 2 F and integrating step S18, remove said the 3rd silicon chip carrier 28.
Obviously, those skilled in the art can carry out various changes and modification to invention and not break away from the spirit and scope of the present invention.Like this, belong within the scope of claim of the present invention and equivalent technologies thereof if of the present invention these are revised with modification, then the present invention also is intended to comprise these changes and modification interior.
Claims (6)
1. a silicon via process is characterized in that, comprising:
The silicon chip that comprises front and back is provided, on said silicon chip, forms deep trench;
The front of said silicon chip is connected with first silicon chip carrier, and expose the bottom that said silicon chip back is thinned to said deep trench, forms the silicon through hole;
Said silicon chip is cleaned;
Said silicon chip back is connected with second silicon chip carrier, removes said first silicon chip carrier;
On the front of said silicon chip, form insulating barrier, barrier layer and copper seed layer successively;
Fill said silicon through hole through the method for electro-coppering;
On the copper of electroplating, connect the 3rd silicon chip carrier, remove said second silicon chip carrier, in said silicon chip back electro-coppering;
Remove said the 3rd silicon chip carrier.
2. silicon via process according to claim 1 is characterized in that, the cleaning fluid that uses when said silicon chip is cleaned is the mixture of ammonium hydroxide and hydrogen peroxide solution, and the time of cleaning is 20s～120s.
3. silicon via process according to claim 1 is characterized in that, the diameter of said deep trench is 1 micron～50 microns, and the degree of depth of said deep trench is 10 microns～500 microns.
4. silicon via process according to claim 1 is characterized in that, the thickness of said insulating barrier is 5A～500A.
5. silicon via process according to claim 1 is characterized in that, the thickness on said barrier layer is 5A～500A.
6. silicon via process according to claim 1 is characterized in that, the thickness of said copper seed layer is 500A～3000A.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2011103798630A CN102376642A (en) | 2011-11-24 | 2011-11-24 | Silicon through hole technology |
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| CN2011103798630A CN102376642A (en) | 2011-11-24 | 2011-11-24 | Silicon through hole technology |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103811413A (en) * | 2012-11-15 | 2014-05-21 | 上海华虹宏力半导体制造有限公司 | Process for manufacturing semiconductor substrate |
| CN109801897A (en) * | 2017-11-16 | 2019-05-24 | 长鑫存储技术有限公司 | Chip stack stereo encapsulation structure and its manufacturing method |
| CN112017967A (en) * | 2019-05-28 | 2020-12-01 | 芯恩（青岛）集成电路有限公司 | Back-side metallized semiconductor structure and preparation method thereof |
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| CN101483149A (en) * | 2009-02-13 | 2009-07-15 | 华中科技大学 | Production method for through wafer interconnection construction |
| CN101840856A (en) * | 2010-04-23 | 2010-09-22 | 中国科学院上海微***与信息技术研究所 | Etch tank adopted in process of packaging and manufacturing TSV (Through Silicon Via) wafer and preparation process |
| CN101853804A (en) * | 2009-04-03 | 2010-10-06 | 南茂科技股份有限公司 | Method for manufacturing semiconductor device |
| US20110241040A1 (en) * | 2010-04-05 | 2011-10-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Novel semiconductor package with through silicon vias |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101483149A (en) * | 2009-02-13 | 2009-07-15 | 华中科技大学 | Production method for through wafer interconnection construction |
| CN101853804A (en) * | 2009-04-03 | 2010-10-06 | 南茂科技股份有限公司 | Method for manufacturing semiconductor device |
| US20110241040A1 (en) * | 2010-04-05 | 2011-10-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Novel semiconductor package with through silicon vias |
| CN101840856A (en) * | 2010-04-23 | 2010-09-22 | 中国科学院上海微***与信息技术研究所 | Etch tank adopted in process of packaging and manufacturing TSV (Through Silicon Via) wafer and preparation process |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103811413A (en) * | 2012-11-15 | 2014-05-21 | 上海华虹宏力半导体制造有限公司 | Process for manufacturing semiconductor substrate |
| CN103811413B (en) * | 2012-11-15 | 2016-06-08 | 上海华虹宏力半导体制造有限公司 | The method of manufacturing technology of semiconductor chip |
| CN109801897A (en) * | 2017-11-16 | 2019-05-24 | 长鑫存储技术有限公司 | Chip stack stereo encapsulation structure and its manufacturing method |
| CN109801897B (en) * | 2017-11-16 | 2021-03-16 | 长鑫存储技术有限公司 | Chip stack three-dimensional packaging structure and manufacturing method thereof |
| CN112017967A (en) * | 2019-05-28 | 2020-12-01 | 芯恩（青岛）集成电路有限公司 | Back-side metallized semiconductor structure and preparation method thereof |
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Application publication date: 20120314 |