CN1023675C - Method for manufacture of semiconductor device - Google Patents
Method for manufacture of semiconductor device Download PDFInfo
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- CN1023675C CN1023675C CN90110138A CN90110138A CN1023675C CN 1023675 C CN1023675 C CN 1023675C CN 90110138 A CN90110138 A CN 90110138A CN 90110138 A CN90110138 A CN 90110138A CN 1023675 C CN1023675 C CN 1023675C
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
According to the present invention, as improvement in the adhesion of inner leads with a packaging resin in a resin-sealed semiconductor device is attained by spreading leads on or near the circuit-forming face of a pellet, or on or near the main non-circuit-forming face of the pellet to extend the lengths of the inner leads on or under the pellet.
Description
The invention relates to a kind of manufacture method of semiconductor device, more specifically say so about effectively being applied to the interconnection technique of resin-encapsulated formula semiconductor device.
Fig. 8 is the plane graph of common lead frame, and this lead frame is used for ordinary resin packaged semiconductor device, particularly in the production of resin-encapsulated type 64KSRAM large scale integrated circuit.Among the figure, digital 100 representational frameworks, 101 is outer lead, and 102 is lead, and 103 is connecting rod, and 104 is table top, 105 is the lead-in wire of table top.
In the production of resin-encapsulated formula semiconductor device a kind of like this trend is arranged, promptly the distance between the table top of shell edge and fixed chip becomes more and more narrow along with the trend of chip size increase.Its reason is because for chip, the size of shell is normalized, although the size of chip is increasing, it is big that the size of shell can not become.
Therefore, can expect that this will inevitably reduce the adherence of so-called short leg greatly, because structurally, that part of length that is embedded in the resin that constitutes shell as these leads of external electrode is shorter, so lead-in wire is easy to come off, and in the bent process of lead-in wire change, very easy generation is peeled off between lead-in wire and the resin.
The present inventor finds that this may cause the inferior moisture resistance etc. that electrically contacts, reduces, thereby reduces the reliability of semiconductor device.
On January 15th, 1980, resin packaged semiconductor device is described on the 149-150 page or leaf that Co., Ltd.'s census of manufacturing can issue, Japanese microelectronics association writes " integrated circuit mounting technique " book.
The manufacture method that the purpose of this invention is to provide a kind of improved semiconductor device, the manufacture method that the semiconductor device of large chip particularly is installed.
Purpose of the present invention and novel feature will be by following explanation and accompanying drawing clarity.
Exactly, the present invention improves the cohesive force of the interlaminar resin of lead and formation shell like this, promptly, in the semiconductor device of resin-encapsulated, make on the circuit formation face that extends to chip to be installed that goes between or near it, perhaps extend on the main inverter circuit formation face of this chip or near it, the inner lead portion of lead-in wire is prolonged.
Fig. 1 is the profile along I among Fig. 2-I line, the semiconductor device that its expression is made with the method for embodiments of the invention 1;
Fig. 2 is the chip of the semiconductor device of expression embodiment 1 and the plane graph of lead-in wire relation;
Fig. 3 is the partial plan of used lead frame in the method for embodiment 1, and it has represented the state of electrodeposit process middle frame;
The chip of the semiconductor device that Fig. 4 makes with the method for embodiments of the invention 2 for expression and the plane graph of lead-in wire relation;
Fig. 5 is that it expresses the internal structure of the semiconductor device of embodiment 2 along the fragmentary cross-sectional view of V among Fig. 4-V line;
Fig. 6 is the profile along Fig. 7 VI-VI line, and Fig. 7 represents the semiconductor device with the method manufacturing of embodiments of the invention 3;
The plane graph of Fig. 7 for concerning between the chip of the semiconductor device of expression embodiment 3 and lead-in wire;
The plane graph of used lead frame in the semiconductor device production of Fig. 8 for the ordinary resin encapsulation.
[embodiment 1]
Fig. 1 is the profile along I among Fig. 2-I line, its semiconductor device for making with the method for the embodiment of the invention 1.Fig. 2 is the plane graph of the lead-in wire relation of the chip of expression embodiment 1.
The semiconductor device of embodiment 1 is a so-called resin-encapsulated formula semiconductor device.Promptly, semiconductor chip 1 is in the middle of the inner lead portion of the lead-in wire 2 that plays the outer lead effect is embedded in the resin that constitutes shell 3, as epoxy resin (hereinafter referred to as " potting resin "), lead-in wire 2 is being bent downwardly near on the limit of shell 3 at the outside lead of shell outside.
In common resin packaged semiconductor device, chip contacts with a table top that plays the mounting panel effect, the size of table top is identical with chip in fact, and the press welding block that plays the chip electrode effect then is electrically connected by the inner end portion formation of fine wire that plays the effect of pressure welding line and the lead-in wire that is arranged in the table top periphery.
And in the semiconductor device of embodiment 1, lead-in wire extends to the back side (the main inverter circuit that does not promptly form semiconductor integrated circuit forms face) of chip 1.Chip links to each other with the heat insulating lamella 5 of polyimide resin by binding agent 6, and this thin slice and these lead-in wires are sticked together.In this case, the table top that chip is used is not installed on the lead frame.Heat insulating lamella makes and reaches electric insulation between the lead-in wire.In the present embodiment, do not have heat insulating lamella 5 in this way, will produce short circuit by the chip 1 of conduction between the lead-in wire.For fear of short circuit, between chip 1 and lead-in wire, placed this heat insulating lamella 5.
As shown in Figure 2, said chip 1 is such with the position relation of lead-in wire 2, the lead-in wire 2a outer lead along the both sides of not preparing to form press welding block 7 on the chip 1 (below, claim " no press welding block forms the limit ") arrange, the lead of lead-in wire 2a extends at the back side of this chip 1 (main inverter circuit forms face), and its end 2b then extends out from the limit that this chip plan forms press welding block 7 always.Heat insulating lamella 5 bonds on the lead-in wire 2a, and it is that main inverter circuit forms the lower surface of face and the upper surface of heat insulating lamella 5 joins for chip 1 usefulness.
In common resin-encapsulated formula semiconductor device, near the embedding place of the packed resin of lead-in wire 2a with the lead that extends has only from the die edge to the table top very length arranged very below chip 1, very short lead-in wire can only be provided.
Common short leg has a problem usually, and promptly owing to have only very little bond area with potting resin, its tensile strength is lower, so lead-in wire comes off from shell easily.Owing to the increase of the bond area between short leg and potting resin along with chip size reduces, therefore, this problem is along with the increase of chip size becomes seriously.
On the contrary, in the semiconductor device of embodiment 1 with above-mentioned short leg relevant position on the lead that provides very long, the bond area of therefore go between 2a and potting resin is very big.Like this, the adhesive strength between lead-in wire and potting resin can obtain big improvement.Therefore, even in using the semiconductor device of large chip, also can prevent from effectively to go between and potting resin between the peeling off of interface place (this peeling off may be taken place when bending outer lead or similarly working), like this, can avoid water from the outside by the chip in the released part intrusion potting resin.Therefore can improve the moisture resistance of semiconductor device.And because heat insulating lamella 5 is very firmly sticking with lead-in wire 2a, lead-in wire 2a just has very high tensile strength.
In addition, because the metal lead wire 2a that thermal conductivity and heat-sinking capability are higher than potting resin contacts going up with it very on a large scale of chip 1 surface, although contact is undertaken by heat insulating lamella 5, the heat that chip produces in working order the time also can directly outwards be distributed by going between.Therefore, the semiconductor device with method manufacturing of the present invention has the good structure of heat-sinking capability.
In addition, owing to being electrically connected of chip 1 and lead-in wire 2a be on the wearing or featuring stage armour chip press welding block 7a be distributed near the press welding block and reach with wire bonds together near the lead 2a end 2b of chip edge, so that pressure welding line 8 can make is very short.Therefore, between the pressure welding line that can prevent to press close to mutually, between pressure welding line and the contiguous lead-in wire or accidental contact the between pressure welding line and the chip.In other words, can prevent short trouble.Moreover, owing to the short total amount that has reduced pressure welding line 8 of pressure welding line, therefore reduced cost.
Semiconductor device among the embodiment 1 is easy to make, its method is: do a lead frame that has pre-determined shape, heat insulating lamella 5 is bonded in the lead predetermined position of lead-in wire, with adhesive chip 1 is bonded on the heat insulating lamella 5, the bonding of the press welding block of chip 1 and lead-in wire is partly linked up with the pressure welding line, use again with ordinary resin packaged semiconductor device production in the assembling of identical step.In this case, the effect of the insulator of accidental short circuit between heat insulating lamella 5 not only plays and prevents to go between, and play the effect of reinforced leads framework on mechanical strength.
The lead bonding part of above-mentioned lead-in wire can be used, and for example, parcel plating method deposit gold forms.
Fig. 3 is the partial plan layout that has the lead frame of heat insulating lamella 5, and thin slice 5 in fact is bonded in connecting rod 9 with interior part.The lead frame part of not drawing among the figure, as, frame part and external lead portion, its shape is similar to those parts shown in Figure 8.In the semiconductor device made from the method for embodiment 1, because heat insulating lamella itself plays a part the parcel plating mask, so only, only carry out selective local with regard to the material (as gold) that good lead binding ability can enoughly be arranged and electroplate at the 2b place, end of lead-in wire 2 just with a parcel plating mask that has a window (shown in band point part among Fig. 3).Thereby simplified the mask preparation method, the formation of bonding part is realized easily.
Among Fig. 3, the mask that the gap is provided along the chip minor face only is shown.But using to have along the long limit of the chip that is parallel to connecting rod 9 provides the mask of the window in gap just can easily carry out parcel plating at all on the lead-in wire of heat insulating lamella 5.In this way, can easily prepare the semiconductor device that chip all has press welding block on every side.
[embodiment 2]
Fig. 4 is the plane graph that shows semiconductor device chips made from the method for another embodiment of the present invention and the relation of going between.
Different among semiconductor device among the embodiment 2 and the embodiment 1, it does not have heat insulating lamella 5, but has adopted a table top littler than chip 1.
Say that exactly in the semiconductor device of embodiment 2, the adhesive 11 that chip 1 usefulness insulating material is made is bonded on the lead of table top and lead-in wire 2a, the outer lead of tying-in 2a is arranged along the limit of the no press welding block of chip.Available insulating material adhesive comprises polyimide resin, silicon rubber and pottery.
In embodiment 2, because not at heat insulating lamella 5, heat energy is enough directly to distribute from chip 1.Therefore compare with embodiment 1, thermal resistance decreases again, thereby reliability is correspondingly higher.
In addition, owing to added table top 10, the bonding strength of chip has also had guarantee.
Fig. 5 is the part sectioned view along Fig. 4 V-V face, and it expresses the status of electrically connecting of the tip portion of chip 1 and lead-in wire 2.On the tip portion 2b of lead-in wire 2a, make a groove 2c.With adhesive adhesion chip 1 time,, can not finish the press welding block 7 of chip 1 and the connection between the bonding part 12 with lead 8 sometimes because adhesive 11 may flow out the surface of the bonding part 12 of making dirty.The barrier that above-mentioned groove 2c flows as blocking-up adhesive 11 is to avoid taking place bonding failure.
[embodiment 3]
Fig. 6 is the profile with the semiconductor device of the method manufacturing of another embodiment of the present invention.Fig. 7 is the plane graph of expression above-mentioned semiconductor device chips with the lead-in wire relation.
Different being of device in the semiconductor device of present embodiment and embodiment 1 and 2, lead is to extend on the circuit formation face of chip.
Particularly, as shown in Figure 6, chip 1 is connected on the polyimide resin heat insulating lamella 5 by means of the adhesive on the circuit formation face 6, and this thin slice 5 is bonded in the back side of lead.The insulator effect of accidental short circuit takes place between in this case, heat insulating lamella 5 plays and prevents to go between.In addition, heat insulating lamella 5 also plays the effect that strengthens lead-in wire the mechanical strength there.
As shown in Figure 7, the size of heat insulating lamella 5 can not be covered the press welding block on the bonding with it chip 1.The outer lead of lead-in wire 2a distributes along the limit that chip does not have press welding block, and its lead extends at the upper surface of heat insulating lamella.The lead-in wire 2a lead stick on the above-mentioned heat insulating lamella 5, its end place press welding block near.
Because the semiconductor device in the present embodiment has the lead that the circuit that is welded on chip 1 forms face one side, so its heat-sinking capability is more superior than the device among the embodiment 1.
Polyimide insulative thin slice 5 is used to prevent that semiconductor device lost efficacy when being subjected to external alpha-irradiation.That is to say that heat insulating lamella 5 plays and stops alpha ray to invade the effect of this device from the outside.Because heat insulating lamella covers on the circuit formation face, also the reliability of conveniently working under the alpha ray condition is improved.
On circuit formation face in the semiconductor device of the wiring and the passivating insulation membrane of circuit with protection chip 1; may not too need to prevent the to go between heat insulating lamella of a short circuit perhaps not only can also can be with the bonding agent of electric conducting material as adhering chip and lead-in wire with insulating material.
In embodiment 3, the end of lead-in wire 2a is placed near on the interior location of press welding block 7, and the position relation between them is opposite with the situation among the embodiment 1.Therefore, welding direction is also opposite.But, welding distance is identical with embodiment 1 basically.
Effect of the present invention is as follows.
(1), in resin-encapsulated formula semiconductor device, on the circuit formation face of the chip of lead in being placed in device or in its vicinity, perhaps on the main inverter circuit formation face of this chip or in its vicinity, extend, can improve the bonding force of lead and potting resin greatly.Therefore, even lay big chip, can prevent that also lead-in wire from coming off from potting resin.
In the present invention, have at least a lead-in wire on chip or below extension.As a result, improved the bonding force of lead and potting resin greatly.Therefore, even lay big chip, can prevent that also lead-in wire from coming off from potting resin.
(2), can prevent from peeling off of bonding plane between lead-in wire and potting resin to be taken place carrying out outer lead when bending.
(3) even the shell of semiconductor device is very little, the chip of wherein laying is very big, also can provide moisture resistance good high reliability semiconductor device.
(4), when lead is fixed on the main inverter circuit formation face of chip, the heat that produces under the operating state can outwards distribute effectively by these lead-in wires.
(5), when in above-mentioned (4) described device, between chip and lead, laying a heat insulating lamella, can improve the bonding strength of chip.
(6) one of preparation is stained with the lead frame of heat insulating lamella and chip is fixed on the heat insulating lamella at predetermined position, just can easily form structure described in (5).
(7), because by heat insulating lamella being bonded in the reservations potential energy reinforcing lead-in wire of lead frame, so even framework contains a large amount of ligaments, lead frame also is easy to processing.
(8), because lead frame has the heat insulating lamella that sticks on the predetermined position, and the parcel plating mask has its size and can be around the heat insulating lamella or the local window that the space is provided, because heat insulating lamella also plays the effect of parcel plating mask, so the combination of these technology makes the wire portion potential energy corresponding to above-mentioned space easily be subjected to parcel plating.
(9), lead is fixed on the circuit formation face of chip, the heat that produces when making circuit in working order can more directly distribute by lead-in wire.
(10), between lead and chip, be provided for stoping alpha ray can protect semiconductor element and the circuit that comprises this element is avoided Alpha-ray radiation to the heat insulating lamella of semiconductor element radiation.Therefore can improve the anti-Alpha-ray reliability of semiconductor device.
(11), provide groove or projection being fixed in close chip mount some areas that chip circuit forms the lead-in wire on the face NOR circuit formation face, can prevent to be used for lead-in wire is bonded at chip or comes out to stain bonding surface partly with the adhesive flow on the heat insulating lamella that chip is connected.Therefore, can prevent inferior lead bonding.
With embodiment the present invention has been done to specify above.But, the present invention has more than and is confined to the foregoing description, and is needless to say more, and the present invention can produce various conversion patterns in the scope that does not depart from main method of the present invention.
For example, all embodiment situation about speaking of all is that lead directly or indirectly is fixed on the first type surface of chip.But, the present invention has more than and is limited to this situation, all or part of lead and can extends near circuit forms face or main inverter circuit formation face.
Lead-in wire is only extending with so-called short leg position relevant chip one side in the situation that all embodiment relate to.Yet the present invention is not only limited to this situation, and it also comprises the situation that lead-in wire with long lead extends in the general semiconductor device.It is a kind of that heat insulating lamella is not only limited to polyimides, can also be a kind of silicon rubber.Certainly, can also add adhesive and/or heat insulating lamella, so that improve heat-sinking capability resembling the such filler of carborundum (sic) powder.
In embodiment 1 and 3, can not necessarily use heat insulating lamella.On the contrary, embodiment 2 can use heat insulating lamella.
The adhesive that prevents to go between resembles the barrier that outflows said among the embodiment 2 and also is not only limited to groove, can also reach the effect of barrier with jut.This barrier can certainly use in embodiment 1 and 3.
Above explanation is mainly concerned with the present invention and is applied to so-called DIP(dual-in-line plastics) the formula semiconductor device, this device is relevant with the application as background of the present invention.But, the present invention is not only limited to this device.Technology of the present invention can be effectively applied to have the semiconductor device of various forms of shell structures, and for example the flat package structure needs only the shell resin-encapsulated.
Claims (4)
1, a kind of manufacture method of semiconductor device comprises above-listed step:
Preparation one comprises lead frame and semiconductor chip with circuit formation face of many lead-in wires, every lead-in wire all has an inner lead portion and an external lead portion, and having a plurality of press welding blocks on the circuit formation face, described inner lead portion extends to described press welding block place;
Make realization electrical connection between described inner lead portion and the corresponding press welding block with the pressure welding line; With
Described chip, described inner lead portion and described pressure welding linear sealing in resin;
Described method is characterised in that also and comprises the following steps:
(1) between described electrical connection and sealing step, a heat insulating lamella is bonded on the described lead portion of described lead-in wire;
(2) afterwards in step (1), with a semiconductor chip agglutination to described heat insulating lamella, thereby the inner lead portion of described lead-in wire is positioned on the described semiconductor chip.
2, the manufacture method of semiconductor device as claimed in claim 1, wherein, described heat insulating lamella is by a kind of the making in silicon rubber, polyimide film or the organic material at least.
3, a kind of technical process of making semiconductor device comprises the following steps:
(1) manufacturing one comprises the lead frame of many lead-in wires, and every lead-in wire all has an inner lead portion and an end, and these inner lead portion are extended in a plane substantially and are divided into first, second, third and the 4th group, and each group all has many inner lead portion;
(2) heat insulating lamella is fixed on the inner lead portion of described lead-in wire;
(3) afterwards, a rectangular shaped semiconductor chip is fixed on the described heat insulating lamella, has an electronic device and a plurality of press welding block on the described chip at least, this chip has first, second, third and four side in step (2);
(4) make described inner lead portion and corresponding press welding block realize being electrically connected with the pressure welding line;
(5) with described chip, inner lead portion and pressure welding linear sealing in resin;
Wherein, described first group of inner lead portion intersects with the first side of described chip at least, and its end extends near the press welding block of arranging near the 3rd side of described chip;
Described second group of inner lead portion intersects with the first side of described chip at least, and its end extends near the press welding block of arranging near the four side of described chip;
Described the 3rd group of inner lead portion intersects with the second side of described chip at least, and its end extends near the press welding block of arranging near the 3rd side of described chip;
Described the 4th group of inner lead portion intersects with the second side of described chip at least, and its end extends near the press welding block of arranging near the four side of described chip.
4, the technical process of manufacturing semiconductor device as claimed in claim 3, wherein, described heat insulating lamella is by a kind of the making in silicon rubber, polyimide film or the organic material at least.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58407/85 | 1985-03-25 | ||
| JP5840785A JPH06105721B2 (en) | 1985-03-25 | 1985-03-25 | Semiconductor device |
| CN198686101795A CN86101795A (en) | 1985-03-25 | 1986-03-19 | Semiconductor device and production method thereof, and the used lead frame of above-mentioned technology |
Related Parent Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN198686101795A Division CN86101795A (en) | 1985-03-25 | 1986-03-19 | Semiconductor device and production method thereof, and the used lead frame of above-mentioned technology |
| CN86101795 Division | 1986-03-19 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1052396A CN1052396A (en) | 1991-06-19 |
| CN1023675C true CN1023675C (en) | 1994-02-02 |
Family
ID=25742185
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN90110138A Expired - Lifetime CN1023675C (en) | 1985-03-25 | 1986-03-19 | Method for manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1023675C (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5650640A (en) * | 1995-04-05 | 1997-07-22 | Motorola | Integrated electro-optic package |
| JP3334864B2 (en) * | 1998-11-19 | 2002-10-15 | 松下電器産業株式会社 | Electronic equipment |
-
1986
- 1986-03-19 CN CN90110138A patent/CN1023675C/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| CN1052396A (en) | 1991-06-19 |
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