CN102364669A - Method for manufacturing copper interconnection layer of ultralow dielectric constant film - Google Patents
Method for manufacturing copper interconnection layer of ultralow dielectric constant film Download PDFInfo
- Publication number
- CN102364669A CN102364669A CN2011102742106A CN201110274210A CN102364669A CN 102364669 A CN102364669 A CN 102364669A CN 2011102742106 A CN2011102742106 A CN 2011102742106A CN 201110274210 A CN201110274210 A CN 201110274210A CN 102364669 A CN102364669 A CN 102364669A
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- dielectric film
- ultralow dielectric
- ultralow
- etching
- groove
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1005—Formation and after-treatment of dielectrics
- H01L2221/1042—Formation and after-treatment of dielectrics the dielectric comprising air gaps
- H01L2221/1047—Formation and after-treatment of dielectrics the dielectric comprising air gaps the air gaps being formed by pores in the dielectric
Abstract
The invention relates to a method for manufacturing a copper interconnection layer of an ultralow dielectric constant film. In the manufacturing method, a shielding graph is covered in an area with a through hole to be formed and a groove to be formed on the ultralow dielectric constant film, so that the ultralow dielectric constant film with a porous structure is obtained outside the area after being irradiated by ultraviolet rays; and the structure of the ultralow dielectric constant film in the area with the through hole to be formed and the groove to be formed is compacted, so that the ultralow dielectric constant film cannot be damaged in subsequent plasma etching steps, ashing steps, sputter deposition barrier layers and seed crystal layers and chemical and mechanical grinding steps. The manufacturing method has the advantages of unchanged and stable dielectric constants of the ultralow dielectric constant film; simultaneously, by the manufacturing method, etching, ashing and cleaning processes in the manufacturing process are easy to finish and have good effects.
Description
Technical field
The present invention relates to semiconductor device, particularly a kind of manufacture method of ultralow dielectric film copper interconnection.
Background technology
Along with the continuous progress of very lagre scale integrated circuit (VLSIC) technology, the characteristic size of semiconductor device is constantly dwindled, and chip area continues to increase, and can compare with the device gate delay time time of delay of interconnecting line.People are faced with how to overcome the problem that the RC (R refers to resistance, and C refers to electric capacity) that brings owing to the rapid growth that connects length postpones remarkable increase.Particularly, cause device performance to descend significantly, become the crucial restraining factors that semi-conductor industry further develops because the influence of metal line line capacitance is serious day by day.The RC that causes in order to reduce to interconnect postpones, and has adopted multiple measure at present.
Parasitic capacitance between the interconnection and interconnection resistance have caused the transmission delay of signal.Because copper has lower resistivity, superior electromigration resistance properties and high reliability can reduce the interconnection resistance of metal, and then reduce total interconnect delay effect, change into low-resistance copper-connection by the aluminium interconnection of routine at present.The electric capacity that reduces simultaneously between the interconnection can reduce to postpone equally, and parasitic capacitance C is proportional to the relative dielectric constant k of circuit layer dielectric, therefore uses low-k materials to replace traditional SiO as the dielectric of different circuit layers
2Medium has become the needs of the development of satisfying high-speed chip.
In order to reduce the parasitic capacitance between the metal interconnecting layer; Prior art has use low-k (low-k) material even ultralow dielectric (untra-low-k) material; And in order to reduce dielectric constant, advanced low-k materials and ultra-low dielectric constant material generally are made into porous, loose structure.Yet also there are a lot of problems in the ultralow dielectric film of porous, open structure in copper-connection is made; Because the soft structure and the easy permeability of ultralow dielectric film; In the chip manufacturing process, be vulnerable to damage; For example, in plasma etching, in the cineration step, in sputtering deposit barrier layer and the inculating crystal layer, in the cmp, often chemical property is more active for the ultralow dielectric film after the damage; Be prone to suction, be prone to and other gas reactions, malleable electric property, the dielectric constant increase.
The manufacture craft of the ultralow dielectric film copper interconnection of prior art is shown in Fig. 1 a-Fig. 1 c; Usually deposition ultralow dielectric film 6 on substrate 5 adopts dual damascene (Dual Damascene) technology to form copper interconnection layer 7 then on the ultralow dielectric film.The porous cancellous soft junction structure of ultralow dielectric film 6 scribbles the dielectric constant film of pore former through ultraviolet irradiation, and dielectric constant film is got rid of gas and obtained.
Summary of the invention
The purpose of this invention is to provide the manufacture method that a kind of ultralow dielectric film copper interconnects, cause the problem of dielectric constant increase with the ultralow dielectric film that solves loose structure in the prior art because of damage.
Technical solution of the present invention is a kind of manufacture method of ultralow dielectric film copper interconnection, and it comprises the following steps:
Deposition-etch stops layer on silicon chip, deposition ultralow dielectric film on etching stop layer;
Form on the ultralow dielectric film through photoetching and to cover figure, use ultraviolet irradiation ultralow dielectric film then, the loose structure that forms in the zone in the ultralow dielectric film below covering figure, figure is covered in removal;
Deposition oxide die and metal die successively on the ultralow dielectric film apply photoresist and form the photoetching window of through hole and/or groove, the metal die that the said photoetching window of etching is interior through photoetching on the metal die; Etch-stop is stayed on the oxide die; Remove the photoresist on the metal die, in the metal die, form etching window, the said etching window inner oxide of etching die, ultralow dielectric film and etching stop layer; Form through hole and/or groove;
The inculating crystal layer of sputtering sedimentation metal barrier and copper in through hole and/or groove, and adopt electroplating technology filling vias and/or groove, form copper interconnection layer;
The wherein said corresponding and said size of covering the size of figure of figure of covering more than or equal to said photoetching window with said photoetching position of window.
As preferably: the dielectric constant of said ultralow dielectric film is 2.2-2.8.
As preferably: the inculating crystal layer of sputtering sedimentation metal barrier and copper in through hole and/or groove; And employing electroplating technology filling vias and/or groove; Also comprise the employing flatening process in the formation copper interconnection layer step, remove metal die and oxide die on the ultralow dielectric film.
As preferably: said flatening process is a cmp.
As preferably: said ultralow dielectric film adopts the CVD process deposits.
Compared with prior art; Advantage of the present invention is said manufacture method will form through hole and/or groove on the ultralow dielectric film a regional overlay masking figure; Make the ultralow dielectric film through only outside above-mentioned zone, obtaining the ultralow dielectric film of loose structure after the ultraviolet irradiation; The ultralow dielectric membrane structure that will form through hole and/or trench region is fine and close, can be in follow-up plasma etching, in the cineration step, in sputtering deposit barrier layer and the inculating crystal layer, cause damage in the cmp.So adopt manufacture method of the present invention; Thereby can avoid the ultralow dielectric film increase to keep the dielectric constant of ultralow dielectric film stable because of damage causes dielectric constant, simultaneously this manufacture method also make make in the flow process etching, ashing, cleaning accomplish easily, effective.
Description of drawings
Fig. 1 a-1c is the manufacture method sketch map of prior art ultralow dielectric film copper interconnection.
Fig. 2 is a making flow chart of the present invention.
Fig. 3-Figure 18 the present invention makes the profile in each processing step in the flow process.
Embodiment
The present invention below will combine accompanying drawing to do further to detail:
Fig. 3-Figure 18 shows preferred embodiment of the present invention, at first provides the surface to be formed with the silicon chip of one deck interconnection layer at least in the present embodiment, need on the current interconnection layer of silicon chip surface, form through hole and groove in regular turn through following step then.Be simplicity of illustration, in Fig. 3-Figure 18, omitted the silicon chip structure below the current interconnection layer.
See also shown in Figure 3, in the present embodiment, deposit first etching stop layer 21 on current interconnection layer 1, on first etching stop layer 21 deposition first ultralow dielectric film 31.
As shown in Figure 4; Utilize the backlight cover of through hole light shield; On the first ultralow dielectric film 31, form first of reservation through hole area and cover figure 32; The said first ultralow dielectric film 31 of ultraviolet irradiation is got rid of in the first ultralow dielectric film 31 gas that covers figure 32 lower zones except that first, obtains the first ultralow dielectric film 31 ' of loose structure; The dielectric constant of the first ultralow dielectric film 31 ' of said loose structure is 2.2-2.8, removes first then and covers figure 32.
As shown in Figure 5; Deposit the first oxide die 33 and the first metal die 34; As shown in Figure 6 again, on the first metal die 34, apply photoresist 35, and adopt photoetching to form the first photoetching window 35a; It is corresponding that the said first photoetching window 35a and said first covers figure 32 positions; And said first cover figure 32 size equal the said first photoetching window 35a, said first covers the first ultralow dielectric film 31 ' compact structure of figure below 32, in follow-up plasma etching, in the cineration step, in sputtering deposit barrier layer and the inculating crystal layer, can not produce damage in the cmp; Solved the ultralow dielectric film that damage brings dielectric constant the increase problem and make in the flow process etching, ashing, cleaning accomplish easily, effective; Certainly, said first cover figure 32 size also can reach above-mentioned technique effect equally greater than the said first photoetching window 35a.
As shown in Figure 7 again; The first metal die 34, the etch-stop that adopt etching technics to remove in the first photoetching window 35a are stayed on the first oxide die 33; Remove the photoresist 35 on the first metal die 34, in the first metal die 34, form the first etching window 34a, as shown in Figure 8 again; The first oxide die 33 in the etching first etching window 34a, the first ultralow dielectric film 31 ', first etching stop layer 21 form the through hole 36 that is communicated to current interconnection layer 1.Said etching technics adopts plasma etching, and said photoresist 35 is removed through cineration technics.
As shown in Figure 9, the inculating crystal layer of sputtering deposit metal barrier and copper in said through hole 36 utilizes electroplating technology to fill the deposit through hole, forms the first metal layer 37; Then, adopt flatening process, remove the first metal layer 37, the first metal die 34 and the first oxide die 33 on the first ultralow dielectric film 31 ', obtain structure shown in figure 10.Said flatening process adopts cmp.
Shown in figure 11; Go up deposition second etching stop layer 22 at the first ultralow dielectric film 31 '; On second etching stop layer 22, deposit the second ultralow dielectric film 41, utilize the backlight cover of groove light shield, form second of reservation trench area at the second ultralow dielectric film 41 and cover figure 42; Shown in figure 12 again; The ultraviolet irradiation second ultralow dielectric film 41 is got rid of the second ultralow dielectric film 41 and is covered the second ultralow dielectric film 41 ' that figure extra-regional gas below 42 obtains loose structure except that second, and the dielectric constant of the second ultralow dielectric film 41 ' of said loose structure is 2.2-2.8.
Shown in figure 13; Remove second and cover figure 42, go up the deposition second oxide die 43 and the second metal die 44 at the second ultralow dielectric film 41 ', shown in figure 14 again; On the second metal die 44, apply photoresist 45; Adopt photoetching to form the second photoetching window 45a, it is corresponding that the said second photoetching window 45a and said second covers figure 42 positions, and said second cover figure 42 size equal the said second photoetching window 45a; Said second covers second ultralow dielectric film 41 compact structures of figure below 42; In follow-up plasma etching, in the cineration step, in sputtering deposit barrier layer and the inculating crystal layer, can not produce damage in the cmp, solved the ultralow dielectric film that damage brings dielectric constant the increase problem and make in the flow process etching, ashing, cleaning accomplish easily, effective, certainly; Said second cover figure 42 size also can reach above-mentioned technique effect equally greater than the said second photoetching window 45a.
Shown in figure 15; The second metal die 44 in the etching second photoetching window 45a, etch-stop are stayed on the second oxide die 43; Remove the photoresist 45 on the second metal die 44; In the second metal die 44, form the second etching window 44a, shown in figure 16 again, the second oxide die 43 in the etching second etching window 44a, the second ultralow dielectric film 41 ', second etching stop layer 21 form grooves 46.Said etching technics adopts plasma etching, and said photoresist 45 is removed through cineration technics.
Shown in figure 17, the inculating crystal layer of sputtering deposit metal barrier and copper in groove 46 utilizes electroplating technology to fill deposit groove 46, forms second metal level 47;
Shown in figure 18, adopt flatening process, remove second metal level 47, the second metal die 44 and the second oxide die 43 on the second ultralow dielectric film 41 ', form the interconnection layer 8 of copper.Said flatening process adopts cmp.
Though present embodiment is after doing through hole earlier on the current interconnection layer, to do groove; But the invention is not restricted to this; Can also directly be made on the device layer of silicon chip surface; Perhaps in one deck interconnection layer, not only comprise through hole but also comprise groove, perhaps be applied in other structure that is similar to through hole, groove, the present invention can save etching stop layer when making groove.
The above is merely preferred embodiment of the present invention, and all equalizations of being done according to claim scope of the present invention change and modify, and all should belong to the covering scope of claim of the present invention.
Claims (5)
1. the manufacture method of ultralow dielectric film copper interconnection is characterized in that:
Deposition-etch stops layer on silicon chip, deposition ultralow dielectric film on etching stop layer;
Form on the ultralow dielectric film through photoetching and to cover figure, use ultraviolet irradiation ultralow dielectric film then, the loose structure that forms in the zone in the ultralow dielectric film below covering figure, figure is covered in removal;
Deposition oxide die and metal die successively on the ultralow dielectric film; The coating photoresist also forms the photoetching window of through hole and/or groove through photoetching on the metal die, the metal die in the said photoetching window of etching, and etch-stop is stayed on the oxide die; Remove the photoresist on the metal die; In the metal die, form etching window, oxide die, ultralow dielectric film and etching stop layer in the said etching window of etching form through hole and/or groove;
The inculating crystal layer of sputtering sedimentation metal barrier and copper in through hole and/or groove, and adopt electroplating technology filling vias and/or groove, form copper interconnection layer;
The wherein said corresponding and said size of covering the size of figure of figure of covering more than or equal to said photoetching window with said photoetching position of window.
2. the manufacture method of ultralow dielectric film copper interconnection according to claim 1, it is characterized in that: the dielectric constant of said ultralow dielectric film is 2.2-2.8.
3. the manufacture method of ultralow dielectric film copper interconnection according to claim 1; It is characterized in that: the inculating crystal layer of sputtering sedimentation metal barrier and copper in through hole and/or groove; And employing electroplating technology filling vias and/or groove; Also comprise the employing flatening process in the formation copper interconnection layer step, remove metal die and oxide die on the ultralow dielectric film.
4. the manufacture method of ultralow dielectric film copper interconnection according to claim 3, it is characterized in that: said flatening process is a cmp.
5. the manufacture method of ultralow dielectric film copper interconnection according to claim 1 is characterized in that: said ultralow dielectric film adopts the CVD process deposits.
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| CN2011102742106A CN102364669A (en) | 2011-09-15 | 2011-09-15 | Method for manufacturing copper interconnection layer of ultralow dielectric constant film |
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| CN2011102742106A CN102364669A (en) | 2011-09-15 | 2011-09-15 | Method for manufacturing copper interconnection layer of ultralow dielectric constant film |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116798952A (en) * | 2023-08-21 | 2023-09-22 | 合肥晶合集成电路股份有限公司 | Method for manufacturing semiconductor device and semiconductor device |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040135254A1 (en) * | 2002-11-07 | 2004-07-15 | Keiji Fujita | Semiconductor device and method for manufacturing the same |
| CN1537330A (en) * | 2000-12-20 | 2004-10-13 | ض� | Structural reinforcement of highly porous low k dielectric films by cu diffusion barrier structures |
| WO2005062348A1 (en) * | 2003-12-23 | 2005-07-07 | Infineon Technologies Ag | Method for producing a semiconductor product |
| US7125793B2 (en) * | 2003-12-23 | 2006-10-24 | Intel Corporation | Method for forming an opening for an interconnect structure in a dielectric layer having a photosensitive material |
| US20080182379A1 (en) * | 2005-03-31 | 2008-07-31 | Freescale Semiconductor, Inc. | Semiconductor Wafer With Low-K Dielectric Layer and Process For Fabrication Thereof |
| CN101295670A (en) * | 2007-04-28 | 2008-10-29 | 联华电子股份有限公司 | Production method of semi-conductor device |
| JP2010103151A (en) * | 2008-10-21 | 2010-05-06 | Tokyo Electron Ltd | Method for manufacturing semiconductor device and apparatus for manufacturing the semiconductor device |
-
2011
- 2011-09-15 CN CN2011102742106A patent/CN102364669A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1537330A (en) * | 2000-12-20 | 2004-10-13 | ض� | Structural reinforcement of highly porous low k dielectric films by cu diffusion barrier structures |
| US20040135254A1 (en) * | 2002-11-07 | 2004-07-15 | Keiji Fujita | Semiconductor device and method for manufacturing the same |
| WO2005062348A1 (en) * | 2003-12-23 | 2005-07-07 | Infineon Technologies Ag | Method for producing a semiconductor product |
| US7125793B2 (en) * | 2003-12-23 | 2006-10-24 | Intel Corporation | Method for forming an opening for an interconnect structure in a dielectric layer having a photosensitive material |
| US20080182379A1 (en) * | 2005-03-31 | 2008-07-31 | Freescale Semiconductor, Inc. | Semiconductor Wafer With Low-K Dielectric Layer and Process For Fabrication Thereof |
| CN101295670A (en) * | 2007-04-28 | 2008-10-29 | 联华电子股份有限公司 | Production method of semi-conductor device |
| JP2010103151A (en) * | 2008-10-21 | 2010-05-06 | Tokyo Electron Ltd | Method for manufacturing semiconductor device and apparatus for manufacturing the semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116798952A (en) * | 2023-08-21 | 2023-09-22 | 合肥晶合集成电路股份有限公司 | Method for manufacturing semiconductor device and semiconductor device |
| CN116798952B (en) * | 2023-08-21 | 2023-11-14 | 合肥晶合集成电路股份有限公司 | Method for manufacturing semiconductor device and semiconductor device |
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| CB03 | Change of inventor or designer information |
Inventor after: Chen Yuwen Inventor after: Zheng Chunsheng Inventor after: Xu Qiang Inventor after: Zhang Wenguang Inventor before: Chen Yuwen |
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| COR | Change of bibliographic data |
Free format text: CORRECT: INVENTOR; FROM: CHEN YUWEN TO: CHEN YUWEN ZHENG CHUNSHENG XU QIANG ZHANG WENGUANG |
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Application publication date: 20120229 |