CN102354670B - Comprehensive surface processing method for improving capsulation reliability of semiconductor - Google Patents

Comprehensive surface processing method for improving capsulation reliability of semiconductor Download PDF

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Publication number
CN102354670B
CN102354670B CN2011103096587A CN201110309658A CN102354670B CN 102354670 B CN102354670 B CN 102354670B CN 2011103096587 A CN2011103096587 A CN 2011103096587A CN 201110309658 A CN201110309658 A CN 201110309658A CN 102354670 B CN102354670 B CN 102354670B
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adhesion promoter
described step
semiconductor packages
treatment method
surface treatment
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CN102354670A (en
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***
秦琳玲
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WUXI SHIYI ELECTRIC POWER MACHINERY EQUIPMENT CO Ltd
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WUXI SHIYI ELECTRIC POWER MACHINERY EQUIPMENT CO Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826Connecting between the body and an opposite side of the item with respect to the body
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
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    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
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    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

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  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

The invention discloses a comprehensive surface processing method for improving the capsulation reliability of a semiconductor. The method is characterized by comprising the following steps of: step a, carrying out plasma treatment on a part in the need of being processed of a material to be processed; step b, applying an adhesion promoter solution to the surface of the material to be processed so that the adhesion promoter solution is adhered to the surface in the need of being strengthened; and step c, volatilizing and drying a solvent in the adhesion promoter solution with the air at a room temperature, or drying the solvent in the adhesion promoter solution by roasting. With the adoption of the comprehensive surface processing method, the bonding strength of a plurality of key interfaces in a chip capsulation can be improved, and the phenomena of layering and cracking are prevented in a technology process; the humidity level and the like are reduced; the service life of the product is prolonged; and the problem of the storage time of the processed product is solved.

Description

A kind of comprehensive surface treatment method that improves the semiconductor packages reliability
Technical field
The present invention relates to the semiconductor chip field, relate in particular to the semiconductor die package technical field.
Background technology
Common semiconductor packages flow process is: the cutting of chip disk; Chip bonding is on lead frame or substrate; The lead bonding makes chip be connected conducting with external circuit; The epoxy resin coating chip, chip carrier, the inside pin of the lead frame that lead and lead connect or the weld pad on the substrate; Be divided into single and external pin moulding.
Epoxy resin enclosed main effect is the chip to its inside, and lead and lead connect provides mechanical support, heat radiation, electric insulation, the corrosion that opposing moisture or soda acid cause.The epoxy encapsulated member is the synthesis that a multiple material intersects, and has the combination interface of epoxy and multiple material, if the bond strength at interface is not enough, will layering under abominable situation, and reliability of products descends.
Particularly since the eighties in 20th century, extensive use along with surface mounting technology, a kind of more serious failure mode is exactly that packaging body is when client is carried out surface mount SMT, chip packing-body is from ftractureing at the interface, lead bonding at the interface is subjected to the easy open circuit of separation stresses effect and causes product failure, chip has at the interface been set up the moisture path with the external world, its failure mechanism be exactly since some operation in temperature than higher, the moisture that the interface absorbs at high temperature volume expands rapidly, and the stress of generation is higher than the cracking that the adhesion at interface causes.JEDEC solid state technology association has announced the standard at the moisture susceptibility of SMT device for this reason, this has been given the clear and definite definition of moisture susceptibility, experimental technique, grade classification.
Since the eighties in 20th century, the work that how to improve the moisture susceptibility did not just stop.With Sumitomo Bakelite (Sumitomo Bakelite), eastern electrician of day (Nitto Denko) adjusts by prescription for the epoxy resin supplier of representative, but the adjustment of prescription will be with respect to moulding, breast the tape, release property, and release property and caking property contradict, thereby the effect that produces is limited, and they are target with the standard of the MSL3 that satisfies Jedec usually.And moisture resistance gas grade as one of core competitiveness of product, for example the epoxy resin of nominal MSL2 is higher more than 50% than the price of MSL3, nominal MSL2 owing to the difference of packaging body, has some can not reach MSL2 through after actual measurements in actual use.
Be the research that frame material surface coarsening that the lead frame supplier of representative carries out is handled with ASM, because alligatoring acts on the framework surface, its main live part is the interface that acts on framework and epoxy resin, inoperative for chip and lead, usually framework is in order to adapt to the requirement of lead bonding, done silver-plated or Nickel Plating Treatment to the pin weld pad, the effect of alligatoring does not often reach the effect as base material on the surface of coating, and interface debonding herein plays the important effect of closing of putting to the life-span of product usually, is exactly that the more common framework of handling of framework cost increase increases very big to the influence of whole packaging cost in addition.
Plasma treatment also is a kind of comparatively common processing method, obtain cleaning by the product before the plasma gas impact plastic packaging, the surface of activation, usually comparatively effective to shallow-layer pollutant or the oxidation of clean surface, but produce can increase bond effect the active group function ratio a little less than, and owing to pollutants such as some oil gas of existence in the air, its effect can decay with handling the time of placing the back, usually can not be above 12 hours.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of comprehensive surface treatment method that improves the semiconductor packages reliability, and the bond strength that it can improve a plurality of crucial interfaces in the chip encapsulation prevents layering in the technical process, cracking; Reduce the moisture number of degrees; Prolong product useful life; Solve the holding time problem after handling.
For solving the problems of the technologies described above, the invention provides following technical scheme: a kind of comprehensive surface treatment method that improves the semiconductor packages reliability wherein, may further comprise the steps step a: the part that pending material require is handled is carried out plasma treatment; Step b: pending material surface is used adhesion promoter solution, make it to be attached to the surface that needs reinforcement; Step c: the solvent normal temperature volatilization in the adhesion promoter solution is air-dry, perhaps dries by roasting mode.
As a kind of preferred version of the comprehensive surface treatment method of raising semiconductor packages reliability of the present invention, wherein: among the described step a, use argon gas that pending material is carried out plasma treatment earlier, re-use nitrogen and carry out plasma treatment.
A kind of preferred version as the comprehensive surface treatment method of raising semiconductor packages reliability of the present invention, wherein: among the described step a, the surface of pending material is exposed under the plasma incident scope, vacuumize and make the interior vacuum degree of cavity less than 0.2 holder, radio freqnency generator sends high frequency waves, make the argon gas in the cavity that is connected as a single entity become plasma, the surface of pending material in the impact cavity under the driving of electric field, rf wave power 550+/-200 watts, action time 30+/-15 seconds, the flow 25+ of argon gas/-15 standard cubic centimeters, treat that the argon gas treatment step is finished after, feed nitrogen again, nitrogen is done the time spent, rf wave power 350+/-150 watts, action time 30+/-20 seconds, the flow 25+ of nitrogen/-15 standard cubic centimeters.
As a kind of preferred version of the comprehensive surface treatment method of raising semiconductor packages reliability of the present invention, wherein: among the described step b, adhesion promoter solution is sprayed on the surface that pending material require strengthens in the noncontact mode by little spraying equipment.
As a kind of preferred version of the comprehensive surface treatment method of raising semiconductor packages reliability of the present invention, wherein: the active component of adhesion promoter solution is titanate coupling agent or silane coupler among the described step b.
A kind of preferred version as the comprehensive surface treatment method of raising semiconductor packages reliability of the present invention, wherein: in the adhesion promoter solution of described step b, organic solvent content is 95%-99.9%, the adhesion promoter active component content is 0.1%-5%, adhesion promoter solution evenly is sprayed on pending material surface, and the use amount of adhesion promoter solution is 5ml/m 2-100ml/m 2
A kind of preferred version as the comprehensive surface treatment method of raising semiconductor packages reliability of the present invention, wherein: among the described step b, adhesion promoter solution evenly is sprayed on pending material surface, and the thickness of the adhesion promoter active component that retains after the solvent evaporates is 5-100nm.
A kind of preferred version as the comprehensive surface treatment method of raising semiconductor packages reliability of the present invention, wherein: in the adhesion promoter solution of described step b, organic solvent content is 97%-99.7%, the adhesion promoter active component content is 0.3%-3%, solution evenly is sprayed on pending material surface, and the solution use amount is 20ml/m 2-60ml/m 2, the thickness of the adhesion promoter active component that retains after the solvent evaporates is 20-60nm.
As a kind of preferred version of the comprehensive surface treatment method of raising semiconductor packages reliability of the present invention, wherein: described step a ionic medium processing region leaded framework on the lead frame series products connects lead, chip; Perhaps on PCB substrate series products, the PCB substrate is arranged, connect lead, chip.
As a kind of preferred version of the comprehensive surface treatment method of raising semiconductor packages reliability of the present invention, wherein: help sticking processing region leaded framework on the lead frame series products among the described step b, connect lead, chip; Perhaps on PCB substrate series products, the PCB substrate is arranged, connect lead, chip.
A kind of preferred version as the comprehensive surface treatment method of raising semiconductor packages reliability of the present invention, wherein: among the described step b, should in storage, help sticking the processing, finish pending material after the plasma treatment and be exposed to time control in the atmosphere within 1.5 hours, the time of preserving under 10000 and 100000 grades of dustfree environments, the holding time was less than 12 hours in the nitrogen cabinet less than 3 hours.
A kind of preferred version as the comprehensive surface treatment method of raising semiconductor packages reliability of the present invention, wherein: among the described step c, the liquid coating that adhesion promoter solution forms can adopt the mode of normal temperature volatilization, the time of volatilization is 5 minutes to 72 hours, or adopt the mode of heated baking to dry, the baking temperature be 60 the degree to 150 the degree, the time of baking is 5 to 60 minutes.
A kind of preferred version as the comprehensive surface treatment method of raising semiconductor packages reliability of the present invention, wherein: among the described step c, after the oven dry, within 96 hours, play the plastic packaging operation under the atmospheric environment, under the dustless nitrogen cabinet storage environment, within 1 month, play the plastic packaging operation.
A kind of preferred version as the comprehensive surface treatment method of raising semiconductor packages reliability of the present invention, wherein: the active component of adhesion promoter solution is three isostearic acid base isopropyl titanates or 3-aminopropyl silanetriol among the described step b, or isopropyl tri titanate, or vinyltrimethoxy silane.
" pending material " herein refers to the semi-finished product of semiconductor chip before epoxy resin enclosed, as the lead frame class, mainly comprises lead frame, connects lead, chip; As PCB substrate class, mainly comprise the PCB substrate, connect lead, chip.Can select the zone and the zone that helps sticking processing of plasma treatment according to concrete arts demand.
At present, generally encapsulate the employed independent plasma cleaning of factory, the effect that its cohesive force is strengthened only is embodied in the opposing subsequent technique, as: the stress in plating, Trim Molding, the cutting, and can not reach the effect that reduces the moisture grade; And the limited time of depositing was generally in 12 hours.The surface coarsening technology of lead frame, it provides the interface of lead frame and epoxy resin to strengthen, and does not improve chip and lead and combination interface epoxy resin; And the expense of lead frame is to account for more than 50% of whole packaging body cost, and the increase of its price is big to the whole cost impact of product.
The present invention at first utilizes the radio-frequency driven carrier gas to finishing chip attachment, and the lead bonding treats that the material of plastic packaging carries out the shock surface processing, to reach to remove machining surface pollutant, the purpose on activated material surface is arranged; And then using little spraying equipment or other equipment that adhesion promoter is sprayed in the noncontact mode on the interface that needs to strengthen, natural air drying or heating, drying form stable and firm coupling agent in conjunction with coating at the interface for the treatment of plastic packaging.The surface that the adhesion promoter active component coupling agent of nanometer grade thickness and pending material require are handled forms chemical bonding; Behind the plastic packaging, another group active group of adhesion promoter active component coupling agent and epoxy resin form crosslinked, form chemical bonding, finally reach required high strength bond interface.Material after the processing will avoid having left in dusty gas, in the environment of liquid.
Adopt beneficial technical effects of the present invention to comprise: one: the bond strength that can improve clad materials such as epoxy resin and lead frame, PCB substrate, chip, the formed a plurality of crucial interfaces of lead, prevent the layering that machinery in the technical process or thermal stress cause, the appearance of cracking, avoid full inspection and substandard products unnecessary in the technical process; Its two: can reduce the moisture number of degrees of product, eliminate product potential defective when client is used, avoid the customer complaint of being correlated with, product recall is compensated; Avoid because high moisture number of degrees high required technology controlling and process cost and damp-prrof packing expense; Make packaging body reach industry, automobile etc. are to the product humidity, the customer requirement of high temperature resistant requirement harshness; Its three: because the coating layer thickness of the adhesion promoter active component that need to form is nano level, the material usage that simultaneously little spraying is used is very low, and cost own is very low, has reduced to encapsulate overall cost; Its four: can prolong the useful life of product more than one times, improve the competitiveness of product in market; Its five: can solve as the timeliness problem of depositing after the plasma treatment, the resting period up to one month makes it to have more practicality on the technology.
Description of drawings
Fig. 1 is lead frame class chip encapsulation schematic top plan view.
Fig. 2 is lead frame class chip package side surface schematic diagram.
Fig. 3 is the real schematic diagram of PCB class chip package side surface.
Fig. 4 is standard-water contact angle for the treatment effect of argon gas with the cleannes index, with the schematic diagram of power influences.
Fig. 5 is the sign Rz of nitrogen treatment and surface roughness, and DU is nanometer, with the schematic diagram of power influences.
Fig. 6 is the table of comparisons (0,5,20,60,100nm, 0 refers to no adhesion promoting coating) of adhesion promoter coating layer thickness and interface peel power (cohesive force).
Fig. 7 is consumption and the reliability function failure rate schematic diagram of adhesion promoter.
Embodiment
Below in conjunction with drawings and the specific embodiments the present invention is described in further detail.
As figure, comprising: 1. lead frame external pin; 2. epoxy resin; 3. the inner pin of lead frame; 4. the chip pad of lead frame; 5. connection lead; 6. chip and framework adhesive; 7. chip; 8 fin.9. chip bonding glue; 10.PCB substrate.
Embodiment 1: the lead frame series products is implemented to handle.
Product before implementing plastic packaging, in its reaction chamber of packing into, can many tilings, automatic or manual all can.The surface of pending material is exposed in the plasma incident scope, connecting vacuum pump vacuumizes, vacuumize and make the interior vacuum degree of cavity less than 0.2 holder, radio freqnency generator sends high frequency waves, make the argon gas in the cavity that is connected as a single entity become plasma, the surface of pending material in the impact cavity under the driving of electric field, rf wave power 550+/-200 watts, action time 30+/-15 seconds, the flow 25+ of argon gas/-15 standard cubic centimeters, after treating that the argon gas treatment step is finished, feed nitrogen again, nitrogen is done the time spent, rf wave power 350+/-150 watts, action time 30+/-20 seconds, the flow 25+ of nitrogen/-15 standard cubic centimeters.Treatment effect to argon gas in the process of the test is standard with the cleannes index, and near the parameter result 550 watts of power is optimum, sees also Fig. 4 in detail.
Nitrogen treatment is relevant with surface roughness, represents with the difference in height of peak dot and valley point, and near the parameter result 430 watts of power is optimum.See also Fig. 5 in detail.
Finish material after the plasma treatment and can be exposed to time control in the atmosphere less than 1.5 hours, the time of preserving under 10,000 and 100,000 grades of dustfree environments, the holding time was less than 12 hours in the nitrogen cabinet less than 3 hours.Falling characteristic is relevant in time with surface activity in the time control that exposes, and downward trend can be slowed down, the prolongation storage time in the dustless and low humidity compression ring border of nitrogen cabinet.
Need finish in storage after the plasma treatment its surface is helped sticking the processing, its position that need strengthen is coated with enclose adhesion promoter, active component is titanate coupling agent, and three isostearic acid base isopropyl titanates, chemical molecular formula are,
Figure BDA0000098202300000051
Solvent is 95%-99.9%, and active coupling agent content is 0.1%-5%, and the adhesion promoter use amount is 5ml/m 2-100ml/m 2, the thickness of the active nano layer that retains after the solvent evaporates is between 5-100nm.Adhesion promoter consumption and effect concern schematic diagram, referring to Fig. 6 and Fig. 7.
Can adopt the mode of natural air drying, 5 minutes to 72 hours time, perhaps baking oven baking 60-150 is Celsius, and 5 to 60 minutes time, it is crosslinked to make the material surface at itself and coated position form chemical bond.After the oven dry, can deposit under the atmospheric environment and reach 96 hours, the dustless nitrogen cabinet resting period can reach 1 month.
Adopt the product after present embodiment is handled, the moisture grade is JEDEC MSL1, reaches the requirement of non-moisture sensitiveness, need not damp-prrof packing, and the term of validity that can deposit is 1 year.The product of common flow process, moisture grade are JEDEC MSL3, need to use damp-prrof packing.Go tide baking 25 hours before the packing, vacuum packaging, vacuum bag need be placed the moisture test card, must use up in 168 hours behind the Kaifeng.Product after the processing of employing present embodiment, MSL1 test rear interface place does not have layering, and no electrical property lost efficacy, and cold cycling, can tolerate the no leads disengaging of 2000 circulations or disconnection by-65 degrees centigrade to 150 degrees centigrade.The product of common flow process, cold cycling ,-65 degrees centigrade to 150 degrees centigrade, only to tolerate 600 circulate no wire stripping or disconnections.
Embodiment 2: the lead frame series products is implemented to handle.
Plasma treatment step is with embodiment 1.Need in storage, finish after the plasma treatment its surface is helped sticking the processing, its position that need strengthen is coated with encloses adhesion promoter, active component is the titanate coupling agent isopropyl tri titanate, and solvent is 99.5%, active coupling agent content is 0.5%, and the adhesion promoter use amount is 5ml/m 2-100ml/m 2, the thickness of the active nano layer that retains after the solvent evaporates is between 5-100nm.The consumption of adhesion promoter and effect concern schematic diagram, referring to Fig. 6 and Fig. 7.
Subsequent step is identical with embodiment 1.
Embodiment 3: the lead frame series products is implemented to handle.
Plasma treatment step is with embodiment 1.Need finish in storage after the plasma treatment its surface is helped sticking the processing, its position that need strengthen is coated with enclose adhesion promoter, active component is silane coupler, and 3-aminopropyl silanetriol, chemical molecular formula be,
Figure BDA0000098202300000061
Solvent is 95%, and active coupling agent content is 5%, and the adhesion promoter use amount is 5ml/m 2-100ml/m 2, the thickness of the active nano layer that retains after the solvent evaporates is between 5-100nm.The consumption of adhesion promoter and effect concern schematic diagram, referring to Fig. 6 and Fig. 7.
Subsequent step is identical with embodiment 1.
Embodiment 4: the lead frame series products is implemented to handle.
Plasma treatment step is with embodiment 1.Need in storage, finish after the plasma treatment its surface is helped sticking the processing, its position that need strengthen is coated with encloses adhesion promoter, active component is the silane coupling agent vinyl trimethoxy silane, and solvent is 99%, active coupling agent content is 1%, and the adhesion promoter use amount is 5ml/m 2-100ml/m 2, the thickness of the active nano layer that retains after the solvent evaporates is between 5-100nm.The consumption of adhesion promoter and effect concern schematic diagram, referring to Fig. 6 and Fig. 7.
Subsequent step is identical with embodiment 1.
Embodiment 5: the PCB series products is implemented to handle.
Product is before implementing plastic packaging, and plasma treatment step is with embodiment 1.Need in storage, finish after the plasma treatment its surface is helped sticking the processing, its position that need strengthen is coated with encloses adhesion promoter, active component is silane coupler, 3-aminopropyl silanetriol, solvent is 95%-99.9%, and active coupling agent content is 0.1%-5%, and the adhesion promoter use amount is 5ml/m 2-100ml/m 2, the thickness of the active nano layer that retains after the solvent evaporates is between 5-100nm.The consumption of adhesion promoter and the signal of the relation of effect as figure are referring to Fig. 6 and Fig. 7.
Can adopt the mode of natural air drying, 5 minutes to 72 hours time, perhaps baking oven baking 60-150 is Celsius, and 5 to 60 minutes time, it is crosslinked to make the material surface at itself and coated position form chemical bond.After the oven dry, can deposit under the atmospheric environment and reach 96 hours, the dustless nitrogen cabinet resting period can reach 1 month.
Adopt the product after present embodiment is handled, the moisture grade reaches JEDEC MSL1, reaches the requirement of non-moisture sensitiveness, need not damp-prrof packing, and the term of validity that can deposit at ambient temperature is 1 year.The product of common flow process, moisture grade are JEDEC MSL3 or are higher than MSL3, belong to climax air-sensitive perceptual device, need to use damp-prrof packing, go tide baking 25 hours before the packing, vacuum packaging, vacuum bag need be placed the moisture test card, must use up in 168 hours behind the Kaifeng.
Adopt the product after present embodiment is handled, the MSL1 test no layering in back, no electrical property lost efficacy, and cold cycling, can tolerate 800 no layerings of circulation by-65 degrees centigrade to 150 degrees centigrade.The product of common flow process, cold cycling ,-65 degrees centigrade to 150 degrees centigrade, only to tolerate 200 no layerings of circulation.
Product after the processing, cold cycling, can tolerate 1500 no leads of circulation and break away from or disconnection by-65 degrees centigrade to 150 degrees centigrade.The product of common flow process, cold cycling ,-65 degrees centigrade to 150 degrees centigrade, only to tolerate 600 circulate no wire stripping or disconnections.
It should be noted that, above embodiment is only unrestricted in order to technical scheme of the present invention to be described, although with reference to preferred embodiment the present invention is had been described in detail, those of ordinary skill in the art is to be understood that, can make amendment or be equal to replacement technical scheme of the present invention, and not breaking away from the spirit and scope of technical solution of the present invention, it all should be encompassed in the middle of the claim scope of the present invention.

Claims (12)

1. comprehensive surface treatment method that improves the semiconductor packages reliability, it is characterized in that, may further comprise the steps, step a: the part that pending material require is handled is carried out plasma treatment, among the described step a, use argon gas that pending material is carried out plasma treatment earlier, re-use nitrogen and carry out plasma treatment; Step b: pending material surface is used adhesion promoter solution, make it to be attached to the surface that needs reinforcement; Step c: the solvent normal temperature volatilization in the adhesion promoter solution is air-dry, perhaps dries by roasting mode; Among the described step a, the surface of pending material is exposed under the plasma incident scope, vacuumize and make the interior vacuum degree of cavity less than 0.2 holder, radio freqnency generator sends high frequency waves, make the argon gas in the cavity that is connected as a single entity become plasma, the surface of pending material in the impact cavity under the driving of electric field, rf wave power 550+/-200 watts, action time 30+/-15 seconds, the flow 25+ of argon gas/-15 standard cubic centimeters, after treating that the argon gas treatment step is finished, feed nitrogen again, nitrogen is done the time spent, rf wave power 350+/-150 watts, action time 30+/-20 seconds, the flow 25+ of nitrogen/-15 standard cubic centimeters.
2. the comprehensive surface treatment method of raising semiconductor packages reliability according to claim 1 is characterized in that: among the described step b, adhesion promoter solution is sprayed on the surface that pending material require strengthens in the noncontact mode by little spraying equipment.
3. the comprehensive surface treatment method of raising semiconductor packages reliability according to claim 1, it is characterized in that: the active component of adhesion promoter solution is titanate coupling agent R1-O-Ti-(O-X1-R2-Y) n or silane coupler (R1-O) 2-Si-R2-Y among the described step b.
4. the comprehensive surface treatment method of raising semiconductor packages reliability according to claim 3, it is characterized in that: in the adhesion promoter solution of described step b, organic solvent content is 95%-99.9%, the adhesion promoter active component content is 0.1%-5%, among the described step b, adhesion promoter solution evenly is sprayed on pending material surface, and the use amount of adhesion promoter solution is 5ml/m2-100ml/m2.
5. the comprehensive surface treatment method of raising semiconductor packages reliability according to claim 3, it is characterized in that: among the described step b, adhesion promoter solution evenly is sprayed on pending material surface, and the thickness of the adhesion promoter active component that retains after the solvent evaporates is 5-100nm.
6. the comprehensive surface treatment method of raising semiconductor packages reliability according to claim 3, it is characterized in that: in the adhesion promoter solution of described step b, organic solvent content is 97%-99.7%, the adhesion promoter active component content is 0.3%-3%, solution evenly is sprayed on pending material surface, the solution use amount is 20ml/m2-60ml/m2, and the thickness of the adhesion promoter active component that retains after the solvent evaporates is 20-60nm.
7. the comprehensive surface treatment method of raising semiconductor packages reliability according to claim 1 is characterized in that: described step a ionic medium processing region leaded framework on the lead frame series products, connection lead, chip; Perhaps on PCB substrate series products, the PCB substrate is arranged, connect lead, chip.
8. the comprehensive surface treatment method of raising semiconductor packages reliability according to claim 1 is characterized in that: help sticking processing region leaded framework on the lead frame series products among the described step b, connect lead, chip; Perhaps on PCB substrate series products, the PCB substrate is arranged, connect lead, chip.
9. the comprehensive surface treatment method of raising semiconductor packages reliability according to claim 1, it is characterized in that: among the described step b, should in storage, help sticking the processing, finish pending material after the plasma treatment and be exposed to time control in the atmosphere within 1.5 hours, the time of preserving under 10000 and 100000 grades of dustfree environments, the holding time was less than 12 hours in the nitrogen cabinet less than 3 hours.
10. the comprehensive surface treatment method of raising semiconductor packages reliability according to claim 1, it is characterized in that: among the described step c, the liquid coating that adhesion promoter solution forms can adopt the mode of normal temperature volatilization, the time of volatilization is 5 minutes to 72 hours, or adopt the mode of heated baking to dry, the baking temperature be 60 the degree to 150 the degree, the time of baking is 5 to 60 minutes.
11. the comprehensive surface treatment method of raising semiconductor packages reliability according to claim 1, it is characterized in that: among the described step c, after the oven dry, within 96 hours, play the plastic packaging operation under the atmospheric environment, under the dustless nitrogen cabinet storage environment, within 1 month, play the plastic packaging operation.
12. the comprehensive surface treatment method of raising semiconductor packages reliability according to claim 1, it is characterized in that: the active component of adhesion promoter solution is three isostearic acid base isopropyl titanates or 3-aminopropyl silanetriol among the described step b, or isopropyl tri titanate, or vinyltrimethoxy silane.
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