CN102354291A - Reset value controllable circuit for asynchronous register and reset value controllable operation method for asynchronous register - Google Patents
Reset value controllable circuit for asynchronous register and reset value controllable operation method for asynchronous register Download PDFInfo
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Abstract
The invention discloses a reset value controllable circuit for an asynchronous register and a rest value controllable operation method for the asynchronous register. The circuit comprises a first register A_1, a second register A_2 and a combination circuit MUX, wherein the first register A_1 is used at an asynchronous position; the second register A_2 is used for asynchronous reset; the combination circuit MUX is used for result selection; a system clock signal clk is respectively connected with the clock end of the first register and the clock end of the second register; a data signal data is respectively connected with data ends D_1 and D_2 of the first register and the second register; a system reset signal rest is respectively connected with the asynchronous reset end CLR of the first register and the asynchronous position end SET of the second register; the output Q_1 of the first register and the output Q_2 of the second register are respectively connected with the input I_1 and I_2 of the combination circuit; and a selection signal ctr1 is connected with the selection end SL of the combination circuit.
Description
Technical field:
The invention belongs to microelectronic, relate to a kind of reset values controllable operating method of asynchronous register reset values controlable electric current structure, especially asynchronous register reset values controlable electric current and asynchronous register.
Background technology:
Along with development of integrated circuits, be that the SOC (system on a chip) function of core becomes increasingly complex with the processor, be controlled to be the processor design of characteristics with many operational modes, be faced with the complicacy and the dirigibility of operational mode design.When resetting, the flexible Application that the multimodal controlled selection of system is designed to system provides advantage.
Register has been realized the sequential function of integrated circuit (IC) system, and the research that designs to register also just seems particularly important.The reset/set of register for making register before normal operation, is confirmed at a certain state.According to the difference of reset/set structure, register is divided into SYN register and asynchronous register.SYN register guarantees reset/set behavior strictness on the clock edge, and the little burr of reset/set signal can be by the clock elimination.But reset/set signal is joined in the data routing, not only want strict and guarantee that the length of reset/set signal satisfies the requirement on system clock edge,, increased the tensity of critical path simultaneously to satisfy the clock collection.Adopt asynchronous register, can not add the logic expense of bringing by reset/set on the system data path.But a burr of reset/set signal possibly cause an erroneous resets behavior, and SYN register has just become a good solution so.
Because the objective relative merits that both deposit separately make that these two kinds of design philosophys are also deposited in present integrated circuit (IC) design.The deviser often plans as a whole system design, and a kind of register type is selected in compromise, has obtained reaching the division of the synchronous reset system that uses SYN register to use the asynchronous reset system of asynchronous register.
Summary of the invention:
Asynchronous register reset values controlable electric current structure of the present invention; A kind of method of the configurable system model that resets towards any asynchronous reset, many operational modes system is provided; This method comprises: the structure overhead computational method under system's multi-mode definition, and the method for designing of the configurable system model that resets.
The objective of the invention is to overcome the shortcoming of above-mentioned prior art; A kind of asynchronous register reset values controlable electric current is provided, and this circuit comprises the first register A_1 that is used for asynchronous set, the combinational circuit MUX that is used for the second register A_2 of asynchronous reset and is used for result's selection; Clock signal of system clk connects the clock end of said first register, the clock end of second register respectively; Data-signal data meets data terminal, the data terminal D_1 of second register, the D_2 of said first register respectively; Systematic reset signal rest connects the asynchronous reset end CLR of said first register respectively, and the asynchronous set end SET of said second register; The output Q_1 of said first register links to each other with input I_1, the I_2 of said combinational circuit respectively with the output Q_2 of said second register; Select signal ctrl to meet the selecting side SL of said combinational circuit.
Said first register comprises three input end D_1, CLR and clock end, an output terminal Q_1; Wherein D_1 is the data input pin of register, and at the edge of clock clk, output Q_1 equals to import data data; CLR is the reset terminal of register, is 1 o'clock at reset signal rest, and output Q_1 equals 0; The sequential of first register does, rest equals at 1 o'clock, and the output Q_1 of first register equals 0; Equal at 0 o'clock at rest, during the edge of clock clk, data equals 1, and Q_1 equals 1.
Said second register comprises three input end D_2, SET and clock end, an output terminal Q_2; Wherein D_2 is the data input pin of register, and at the edge of clock clk, output Q_2 equals to import data data; SET is the set end of register, is 1 o'clock at reset signal rest, and output Q_2 equals 1; The sequential of second register does, rest equals at 1 o'clock, and the output Q_2 of second register equals 1; Equal at 0 o'clock at rest, during the edge of clock clk, data equals 1, and Q_2 equals 1.
Said combinational circuit comprises three input end I_1, I_2 and SL, an output terminal Q; Wherein I_1 connects the output terminal Q_1 of first register, and I_2 connects the output terminal Q_2 of second register; SL is the selecting side, and signal ctrl is selected in selecting, and ctrl is 0 o'clock, and output Q equals to import I_1, and ctrl is 1 o'clock, and output Q equals to import I_2; The sequential of combinational circuit does, ctrl equals 0, and output Q equals to import I_1, and ctrl equals 1, and output Q equals to import I_2.
A kind of reset values controllable operating method of asynchronous register when resetting, through selecting the output of signal ctrl control register, promptly selects signal ctrl to equal 0, then exports Q and equals 0, if select signal to equal 1, then exports Q and equals 1; And after the end that resets, first register and second register all will latch data data when the clock edge, and export Q this moment all is the data value, realize the reset values controllable operating of asynchronous register.
The reset values controllable operating method of asynchronous register reset values controlable electric current of the present invention and asynchronous register; Comprise the structure overhead computational method under system's multi-mode definition; And the method for designing of the configurable system model that resets; Through the effect of control signal, realize that the reset values of asynchronous register is controlled.
Description of drawings:
Fig. 1 is a SYN register structural drawing of the present invention;
Fig. 2 is the present invention's asynchronous register according to the invention controlable electric current figure that resets;
Fig. 3 is an asynchronous register structural drawing of the present invention;
Fig. 4 is the asynchronous register of the present invention controlable electric current figure that resets
Fig. 5 is the first register sequential chart figure of the present invention;
Fig. 6 is the second register sequential chart of the present invention;
Fig. 7 is a combinational circuit sequential chart of the present invention;
Fig. 8 is the circuit structure diagram of the configurable system model that resets of the present invention;
Wherein: 1 does; 2 do; 3 do; 4 do; 5 do; 6 do; 7 do; 8 do; 9 do; 10 do; 11 do.
Embodiment:
Below in conjunction with accompanying drawing the present invention is done and to describe in further detail:
Referring to Fig. 1-8, provided the structural representation of SYN register in the accompanying drawing 1, D is a data input pin among the figure, and CLK is a clock end, and Q is a data output end, when arriving at the clock edge, the value of data input pin is deposited in the register, will deposit the value output of register in through Q.In the accompanying drawing 2, provided a kind of controlled circuit structure of SYN register reset values commonly used, comprised in this structure that a combinational logic MUX does input and selects a SYN register.Reset signal meets the selecting side SL of combinational logic, and input signal ctrl and data receive I_1, the I_2 end of combinational logic respectively, are input to D.When resetting (rest equals 0), at the edge of clock clk, output Q equals ctrl; The end (rest equals 1) that resets, at the edge of clk, Q equals data.So, be implemented in when resetting controlled to the register reset values.
Provided the synoptic diagram of asynchronous register in the accompanying drawing 3, the mechanism that data are deposited is identical with SYN register, and institute's difference is, has increased asynchronous reset end CLR and asynchronous set end SET.In case reset terminal is effective,,,,, in 1 fixing value of register will be deposited no matter whether the clock edge arrives in case the set end is effective with depositing 0 fixing value of register in no matter whether the clock edge arrives.Obviously, systematic reset signal can not be received the CLR and the SET end of a register simultaneously, when resetting, through the asynchronous reset end or the set end of register, can only compose a definite value to register, can't realize the controlled of register reset values.
The present invention is exactly to this status of design, adopts a kind of function register of double copies structure, when resetting, and through the output validity of control double copies structure, decision register reset values; After resetting, the double copies structure becomes one, guarantees the correct function of register.Circuit structure is shown in accompanying drawing 4.
This circuit comprises the first register A_1 that is used for asynchronous set, the combinational circuit MUX that is used for the second register A_2 of asynchronous reset and is used for result's selection.Clock signal of system clk connects the clock end of said first, second register respectively; Data-signal data meets data terminal D_1, the D_2 of said first, second register respectively; Systematic reset signal rest connects the asynchronous reset end CLR of said first register respectively, and the asynchronous set end SET of said second register; The output Q_1 of said first register links to each other with input I_1, the I_2 of said combinational circuit respectively with the output Q_2 of said second register; Select signal ctrl to meet the selecting side SL of said combinational circuit.
First register comprises three input end D_1, CLR and clock end, an output terminal Q_1.Wherein D_1 is the data input pin of register, and at the edge of clock clk, output Q_1 equals to import data data; CLR is the reset terminal of register, and when reset signal rest was ' 1 ', output Q_1 equaled ' 0 '; Accompanying drawing 5 has provided the sequential of first register, and rest equals at 1 o'clock, among the said figure 1. shown in, the output Q_1 of first register equals 0.Equal at 0 o'clock at rest, as as described among the figure 2. shown in, during the edge of clock clk, input data equals 1, output Q_1 equals 1; As as described among the figure 3. shown in, during the edge of clock clk, input data equals 0, output Q_1 equals 0; As among the chatting figure 4. shown in, during the edge of clock clk, input data equals 1, output Q_1 equals 1.
Second register comprises three input end D_2, SET and clock end, an output terminal Q_2.Wherein D_2 is the data input pin of register, and at the edge of clock clk, output Q_2 equals to import data data; SET is the set end of register, and when reset signal rest was ' 1 ', output Q_2 equaled ' 1 '; Accompanying drawing 6 has provided the sequential of second register, and rest equals at 1 o'clock, among the said figure 1. shown in, the output Q_2 of second register equals 1.Equal at 0 o'clock at rest, as as described among the figure 2. shown in, during the edge of clock clk, input data equals 1, output Q_2 equals 1; As as described among the figure 3. shown in, during the edge of clock clk, input data equals 0, output Q_2 equals 0; As as described among the figure 4. shown in, during the edge of clock clk, input data equals 1, output Q_2 equals 1;
Combinational circuit is realized " alternative " function, comprises three input end I_1, I_2 and SL, an output terminal Q.Wherein I_1 connects the output terminal Q_1 of first register, and I_2 connects the output terminal Q_2 of second register; SL is the selecting side, and signal ctrl is selected in selecting, and ctrl is 0 o'clock, and output Q equals to import I_1, and ctrl is 1 o'clock, and output Q equals to import I_2.Accompanying drawing 7 has provided the sequential of combinational circuit, and ctrl equals 0, as as described among the figure 1. shown in, output Q equals to import I_1,2. 3. 4., ctrl equals 1 among the said figure, output Q equals to import I_2.
Said structure is realized, when resetting, can promptly select signal ctrl to equal 0 through selecting the output of signal ctrl control register, then exports Q and equals 0, if select signal to equal 1, then exports Q and equals 1; And reset finish after, first register and second register all will latch data data when the clock edge, this moment, no matter why the selection control signal of combinational logic was worth, output Q is the data value, the double copies structure becomes one, and is same function register.So, realize the reset values controllable operating of asynchronous register.
System running pattern is the N kind, defined function M=log
2xN, this function realize that the result rounds up 2 to be the logarithm at the end, and during N=1, M=1.Subordinate list 1 provides the corresponding M value of different N value.According to above-mentioned function definition, adopt circuit structure according to the invention, when accomplishing the controlled design of system model, required hardware spending comprises: the register of M band asynchronous reset, the register of M band asynchronous set, M combinational logic, M pattern controlled the selection signal.
Accompanying drawing 8 has provided the circuit structure signal of the configurable system model that resets; Wherein, Clock signal of system clk connects the clock end of M said invention circuit; Systematic reset signal rest connects the reset terminal rest of M said invention circuit; Mode select signal ctrl_1～ctrl_M meets a corresponding M said invention circuit control end ctrl respectively; Data-signal data_1～data_M meets the data input pin data of a corresponding M said invention circuit respectively, and the data output end Q of M said invention circuit connects Q1～QM respectively.After the end that resets, get in N the system running pattern by Q1～QM control system.
Subordinate list 1M=log
2xN
Above content is to combine concrete preferred implementation to further explain that the present invention did; Can not assert that the specific embodiment of the present invention only limits to this; Those of ordinary skill for technical field under the present invention; Under the prerequisite that does not break away from the present invention's design; Can also make some simple deduction or replace, all should be considered as belonging to the present invention and confirm scope of patent protection by claims of being submitted to.
Claims (5)
1. asynchronous register reset values controlable electric current is characterized in that: this circuit comprises the first register A_1 that is used for asynchronous set, is used for the second register A_2 of asynchronous reset and is used for the combinational circuit MUX that the result selects; Clock signal of system clk connects the clock end of said first register, the clock end of second register respectively; Data-signal data meets the data terminal D_1 of said first register, the data terminal D_2 of second register respectively; Systematic reset signal rest connects the asynchronous reset end CLR of said first register respectively, and the asynchronous set end SET of said second register; The output terminal Q_1 of said first register links to each other with input end I_1, the input end I_2 of said combinational circuit respectively with the output terminal Q_2 of said second register; Select signal ctrl to meet the selecting side SL of said combinational circuit.
2. asynchronous register reset values controlable electric current according to claim 1, it is characterized in that: said first register comprises data terminal D_1, asynchronous reset end CLR and clock end, an output terminal Q_1; Wherein data terminal D_1 is the data input pin of register, and at the edge of clock clk, output terminal Q_1 equals to import data data; Asynchronous reset end CLR is the reset terminal of register, is 1 o'clock at reset signal rest, and output terminal Q_1 equals 0; The sequential of first register does, rest equals at 1 o'clock, and the output terminal Q_1 of first register equals 0; Equal at 0 o'clock at rest, during the edge of clock clk, data equals 1, and Q_1 equals 1.
3. asynchronous register reset values controlable electric current according to claim 1, it is characterized in that: said second register comprises three input end D_2, SET and clock end, an output terminal Q_2; Wherein D_2 is the data input pin of register, and at the edge of clock clk, output terminal Q_2 equals to import data data; SET is the set end of register, is 1 o'clock at reset signal rest, and output terminal Q_2 equals 1; The sequential of second register does, rest equals at 1 o'clock, and the output terminal Q_2 of second register equals 1; Equal at 0 o'clock at rest, during the edge of clock clk, the output terminal Q_2 that data equals 1, the second register equals 1.
4. asynchronous register reset values controlable electric current according to claim 1, it is characterized in that: said combinational circuit comprises input end I_1, input end I_2 and selecting side SL, an output terminal Q; Wherein I_1 connects the output terminal Q_1 of first register, and I_2 connects the output terminal Q_2 of second register; SL is the selecting side, and signal ctrl is selected in selecting, and ctrl is 0 o'clock, and output terminal Q equals input end I_1, and ctrl is 1 o'clock, and output terminal Q equals input end I_2; The sequential of combinational circuit does, ctrl equals 0, and output terminal Q equals input end I_1, and ctrl equals 1, and output terminal Q equals input end I_2.
5. the reset values controllable operating method of an asynchronous register is characterized in that: when resetting, through selecting the output of signal ctrl control register; Promptly select signal ctrl to equal 0; Then output terminal Q equals 0, if select signal to equal 1, then output terminal Q equals 1; And after the end that resets, first register and second register all will latch data data when the clock edge, and this moment, output terminal Q was the data value, realized the reset values controllable operating of asynchronous register.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104200178A (en) * | 2014-08-06 | 2014-12-10 | 中国科学院信息工程研究所 | Double-edge triggering driving logic system and method for resisting energy analysis attacks |
| CN104348465A (en) * | 2013-07-26 | 2015-02-11 | 华为技术有限公司 | Control method and control circuit |
| CN105425926A (en) * | 2015-12-22 | 2016-03-23 | 无锡芯响电子科技有限公司 | Controllable-bandwidth reset circuit capable of achieving asynchronous reset and synchronous release |
| CN109240474A (en) * | 2018-08-30 | 2019-01-18 | 成都锐成芯微科技股份有限公司 | Reset values controllable digital circuit and its design method |
| CN110489363A (en) * | 2019-10-08 | 2019-11-22 | 灿芯半导体(上海)有限公司 | Transmitting line based on DDR write access |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104348465A (en) * | 2013-07-26 | 2015-02-11 | 华为技术有限公司 | Control method and control circuit |
| CN104348465B (en) * | 2013-07-26 | 2018-08-14 | 华为技术有限公司 | A kind of control method and control circuit |
| CN104200178A (en) * | 2014-08-06 | 2014-12-10 | 中国科学院信息工程研究所 | Double-edge triggering driving logic system and method for resisting energy analysis attacks |
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| CN105425926A (en) * | 2015-12-22 | 2016-03-23 | 无锡芯响电子科技有限公司 | Controllable-bandwidth reset circuit capable of achieving asynchronous reset and synchronous release |
| CN109240474A (en) * | 2018-08-30 | 2019-01-18 | 成都锐成芯微科技股份有限公司 | Reset values controllable digital circuit and its design method |
| CN110489363A (en) * | 2019-10-08 | 2019-11-22 | 灿芯半导体(上海)有限公司 | Transmitting line based on DDR write access |
| CN110489363B (en) * | 2019-10-08 | 2024-03-22 | 灿芯半导体(上海)股份有限公司 | Sending circuit based on DDR write channel |
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Application publication date: 20120215 |