CN102347749A - Dual-edge-triggered state-retention scan flip-flop (DET-SRSFF) - Google Patents

Abstract

The invention relates to the technical field of integrated circuits and discloses a dual-edge-triggered state-retention scan flip-flop (DET-SRSFF), which is characterized by comprising a pulse generating circuit and a static-state latch circuit which are connected with each other, wherein the static-state latch circuit comprises a leakage feedback pulse structure. According to the invention, leakage feedback buffer (LFB) circuits in the pulse generating circuit of the traditional DET-SRSFF as well as a static-state latch and input-output circuit are improved, the structure of the LFB is simplified on the premise of completely maintaining the low-power-consumption advantage of the DET-SRSFF. In addition, the pulse generating circuit is modified, and generated redundant pulses are removed. Finally, a simulation result from high-precision simulation program with integrated circuit emphasis (HSPICE) shows that the improved structure has advantages in the aspects of both power consumption and speed. A power consumption lagged product is reduced by 19.56%, and the improved DET-SRSFF is more suitable to meeting requirements of the development of the integrated circuit on a trigger.

Description

But the bilateral sweep trigger that keeps along the state that triggers

Technical field

The present invention relates to technical field of integrated circuits, but particularly a kind of bilateral sweep trigger that keeps along the state that triggers.

Background technology

Along with the decline of integrated circuit technology characteristic size, the rising of circuit work frequency, the leakage power consumption that reduces circuit has become the focus and the difficult point of integrated circuit (IC) design.And be one of power consumption source maximum in VLSI (very lagre scale integrated circuit (VLSIC)) system by the clock system that timing unit (trigger and latch) and clock network are formed.Statistics shows that nearly 30% to 60% leakage power consumption is all produced by clock system, and the power consumption that therefore reduces trigger just has profound significance (referring to document [2]).In document [1]; H.Karimiyan; But bilateral sweep trigger (the Dual-edgetriggered state-retention scan flip-flop that keeps along the state that triggers of S.M.Sayedi and H.Saidi design; DET-SRSFF) be exactly the structure that proposes to the low-power consumption of trigger, shown in Fig. 1 (a), Fig. 1 (b).Integral body, this structure mainly are to have adopted following 6 kinds of Low-power Technology:

1, adopt the power-gating technology, increase CG and SLEEP control signal, power supply reduces leakage power to the path on ground when cutting off sleep state.

2, adopt the multi-threshold mos Manifold technology, critical path adopts the metal-oxide-semiconductor of low threshold voltage to come assurance speed, and non-critical path adopts the high threshold voltage metal-oxide-semiconductor to reduce power consumption.

3, adopt the multi-power source voltage technology,,, reduce power consumption so the power supply of low-voltage has been adopted in pulse when producing because pulse-generating circuit has consumed very most power consumption.

4, adopt Low Voltage Technique, for the part that latchs of trigger, during sleep state, the supply voltage that latchs part through reduction reduces leakage power.

5,, thereby cause that the PMOS pipe that output connects can not turn-off fully, increases power consumption because the high level that the low level technology possibly cause latching is undesirable.So DET-SRSFF has introduced the structure of LFB (leakage feedback buffer) and has prevented to latch the big leakage current that undesirable high level partly causes.

6, adopt long deflection (gate-length biasing) technology of grid.In document [3], proposed this technology, it is to reduce power consumption through the grid length of finely tuning metal-oxide-semiconductor.In general, in the long fine setting 10% of grid, when having guaranteed domain structure regular basically, can reduce appreciable power consumption.

In document [1], the author utilizes HSPICE emulation that DET-SRSFF and CBS_ip (document [2]), ep-DSFF (document [4]), SPGFF (document [5]), CDFF (document [6]) and D2LCFF (document [7]) are compared.Though the power consumption lagged product of DET-SRSFF is not minimum, integral body, DET-SRSFF has the advantage that state keeps (node does not suspend) and can scan when the power consumption lagged product is very little.

At first introduce existing static latch and leakage feedback buffer circuit below.

Among Fig. 1 (a), CG representes clock pulse gate signal (Clock Gate), and CLOCK representes clock signal; Among Fig. 1 (b), SE representes scan enable signals (Scan Enable), adds the inverted signal of "-" expression SE above; SI, SO represent scan input signal and scanning output signal respectively; SLEEP representes sleep signal; P indicating impulse output signal.

The static latch of traditional DET-SRSFF and imput output circuit are shown in Fig. 1 (b), and the static latch of DET-SRSFF has partly adopted Low Voltage Technique.Under mode of operation, when the SLEEP point is low level (0), PMOS pipe MP5 conducting, the supply voltage of this static latch part is VCCH, the circuit operate as normal.And under the sleep pattern; SLEEP is 1, and MP5 breaks off, and the supply voltage of this static latch part is the voltage (VCCH deducts 2Vth) that obtains after VCCH transmits through two NMOS pipe MN5 and MN6; Have the loss of two NMOS pipe threshold voltages, wherein Vth representes the threshold voltage of MN1 and MN2.Like this, just reduce the leakage current under the sleep pattern, saved power consumption.

But the situation of imperfect high level will appear in the high level of this static latch part under the sleep pattern, and the not exclusively situation of shutoff will appear in the PMOS pipe of at this moment exporting in the buffer structure, can cause big leakage current.

So used leakage feedback buffering (LFB) structure (marking with circle among Fig. 1 (b)) that proposes in the document [8] in the document [1].LFB is used for preventing the big leakage current that when using the multi-Vt metal-oxide-semiconductor, causes, and is used for preventing the big leakage current that imperfect level causes in the document [1], guarantees that simultaneously the level of output is an ideal level.

After the circuit structure of LFB (being the output circuit of DET-SRSFF) is taken out separately from Fig. 1 (b) as shown in Figure 2.Under mode of operation, SLEEP is 0, MP1 and MN1 conducting, and total is equivalent to an inverter.SLEEP is 1 o'clock, and MP1 and MN1 break off. will remain before the end of the level.Because unfavorable level possibly appear in the O end, MP3 and MN3 possibly not exclusively end, but always have a meeting to end fully among MP2 and the MN2, so limited leakage current.Meanwhile

VCCH or terminal is always connected to ground GND, and therefore have the desired high and low.

Traditional pulse produces structure and in Fig. 1 (a), provides, and its course of work is:

During operating state, CG is 0, the MP1 conducting, and MN1 ends, and node 1 signal is the non-of CLOCK.Node 4 is signals after 1 the delay.The part of back is an XOR gate, and P is the XOR of voltage v (4) of voltage v (1) and the node 4 of node 1.When the CLOCK saltus step, 1 saltus step, 4 also not to become, and therefore 1 is different with 4 voltages, thus P is output as high level, and after the delay of passing through INV2 and INV3,4 become the same with 1 voltage, and P becomes low level again.So each CLOCK saltus step all can produce a high level pulse.

During sleep state, CG is 1, and MP4 ends, the MN4 conducting, and such 1 node is pulled to low level all the time, and the saltus step of CLOCK can not be passed to 1 place, and the P node does not produce pulse.

But also there is a problem in top structure: in the time will getting into sleep state, CG can become 1 by 0, and original expection was that P place horse back stops to produce pulse.If but in fact when node 1 is in high level, CG has become 1 by 0, node 1 place can be 0 by 1 saltus step so, at this moment will produce a pulse at the P place.Go up jumping along appearing at CLOCK when low of CG in other words can produce one and gone up by CG and to jump the unwanted pulse that produces.

List of references above-mentioned is following:

[1]H.Karimiyan?S.M.Sayedi?H.Saidi，“Low-power?dual-edgetriggered?state-retentionscan?flip-flop”，IET?Comput.Digit.Tech.，2010，Vol.4，Iss.5，pp.410-419

[2]ZHAO?P.，MCNEELY?J.，GOLCONDA?P.，BAYOUMI?M.A.，BARCENAS?R.A.，KUANG?W.，“Low-power?clock?branch?sharingdouble-edgetriggered?flip-flop”，IEEE?Trans.VLSI?Syst.，2007，15，(3)，pp.338-345

[3]GUPTA?P.，KAHNG?A.B.，SHARMA?P.，SYLVESTERD.，“Gate-lengthbiasing?for?runtime-leakage?control”，IEEE?Trans.Comput.Aided-Des.，2006，25，(8)，pp.1475-1485

[4]TSCHANZ?J.，NARENDRA?S.，CHEN?Z.，BORKAR?S.，SACHDEV?M.，DE?V.，”Comparative?delay?and?energy?of?singleedge-triggered?anddual?edge?triggered?pulsed?flip-flops?forhigh-performancemicroprocessors”.Proc.2001?Int.Symp.Low?onPowerElectronics?and?Design，ISPLED，Huntington?Beach，California，USA，2001，pp.147-152

[5]NEDOVIC′N.，OKLOBDZIJA?V.G.，“Dual-edge?triggeredstorageelements?and?clocking?strategy?for?low-power?systems”，IEEETrans.VLSI?Syst.，2005，13，(5)，pp.577-590

[6]ZHAO?P.，DARWISH?T.，BAYOUMI?M.，“High-performanceandlow?power?conditional?discharge?flip-flop”，IEEE?Trans.VLSISyst.，2004，12，(5)，pp.477-484

[7]CHIOU?L.-Y.，LOU?S.-C.，“An?energy-efficientdualedgetriggered?level-converting?flip-flop”.IEEE?Int.Symp.on?Circuitsand?Systems，ISCAS，May?2007，pp.1157-1160

[8]KAO?J.，CHANDRAKASAN?A.P.，“MTCMOS?sequentialcircuits”.Proc.27th?European?Solid-State?Circuits?Conf.(ESSCIRC2001)，September?2001，pp.317-320。

Summary of the invention

(1) technical problem that will solve

The technical problem that the present invention will solve is, how to improve the circuit speed of service, reduces the power consumption of circuit simultaneously.

(2) summary of the invention

In order to solve the problems of the technologies described above; But the invention provides a kind of bilateral sweep trigger that keeps along the state that triggers; Comprise interconnective pulse-generating circuit and static latch circuit, said static latch circuit comprises leakage feedback pulse structure, and said leakage feedback pulse structure comprises:

3 PMOS pipe MP1～MP3 and 1 NMOS pipe MN3, first end of MP1 connects sleep signal, and first end of MP2 connects scanning output signal; Second end of MP1, MP2 links to each other, and connects power supply VCCH, and the 3rd end of MP1, MP2 links to each other, and connects first end of MP3; Second end of MP3 connects the inverted signal of said scanning output signal and first end of MN3, and the 3rd end of MP3 connects second end of MN3, the 3rd termination ground wire of MN3.

Wherein, said pulse-generating circuit comprises 5 PMOS pipe MP7～MP10, MPcg; 5 NMOS manage MN7～MN10, MNcg; And 3 inverter INV1～INV3; First end of MP7 connects the clock pulse gate signal, and second end connects first end of MP8, and the 3rd end connects first end of MNcg and the 3rd end of MN8; Second end of MP8 connects first end of clock signal and MN7, and the 3rd end connects second end, first end of MN8 and first end of MP9 of MN7; The 3rd end of MN7 connects second end and the ground wire of MN8, and second end connects first end, first end of INV1 and second end of MP10 of inverter INV2; The 3rd end of INV2 connects another power supply VCCL, and the 4th end connects ground wire, and second end connects first end of INV3; The 3rd end of INV3 connects the 3rd end of MPcg, the 4th end ground connection, and second end connects second end, the 3rd end of MP9, the 3rd end of MN9, first end of MP10 and first end of MN10 of MNcg; The said power supply VCCL of second termination of MPcg, first end of the first termination MNcg; The 3rd end ground connection of MNcg; The 3rd end of the 3rd termination MN10 of MP10, second end of MN9, second end and the pulse output signals of MP9.

Wherein, the voltage that provided greater than power supply VCCL of the voltage that provided of power supply VCCH.

(3) beneficial effect

The present invention has following beneficial effect: the present invention improves the leakage feedback buffer circuit (LFB) as export structure in the pulse-generating circuit of traditional DET-SRSFF and static latch and the imput output circuit.Under the prerequisite that keeps DET-SRSFF low-power consumption advantage fully, simplified the LFB structure.Revise pulse-generating circuit in addition, removed the redundant pulse that produces.Simulation result with HSPICE shows that the structure after the improvement all has advantage aspect power consumption and the speed at last.Power consumption lagged product aspect has 19.56% reduction, makes that the DET-SRSFF after improving adapts to the requirement of integrated circuit development for trigger more.

Description of drawings

Fig. 1 (a) is the pulse-generating circuit of traditional DET-SRSFF; Static latch and the imput output circuit of the DET-SRSFF that Fig. 1 (b) is traditional;

Fig. 2 is traditional leakage feedback buffer structure (LFB), and it is included among Fig. 1 (b);

(a) is the static latch circuit behind the simplification LFB of the present invention among Fig. 3; (b) be amended pulse-generating circuit of the present invention;

Fig. 4 (a) is the waveform of former pulse-generating circuit Fig. 1 (a), and Fig. 4 (b) is that the pulse of revising (b) in the circuit diagram 3 of back produces waveform;

Fig. 5 is simulation configurations figure;

Fig. 6 is the simulation waveform of DET-SRSFF before and after simplifying.

Embodiment

Below in conjunction with accompanying drawing and embodiment, specific embodiments of the invention describes in further detail.Following examples are used to illustrate the present invention, but are not used for limiting scope of the present invention.

The present invention improves respectively the static latch of the DET-SRSFF of the pulse-generating circuit of the DET-SRSFF of Fig. 1 (a) and Fig. 1 (b) and imput output circuit (being to be Fig. 2 as the LFB circuit of export structure wherein specifically).

Improvement to Fig. 1 (b) is following: through we can see among Fig. 1 (b), the static latch part so the level that latchs only the loss of high level can occur, and low level loss can not occur because the gate pipe has only broken off power supply VCCH.So LFB just need not consider the situation that NMOS can not turn-off fully.MN1 and MN2 can delete, and in order to reduce leakage current, MN3 should be changed to the NMOS pipe of high threshold voltage simultaneously.

In addition, owing to just have the Q signal of control MP2 among Fig. 1 (b) originally, so need not produce this signal through inverter.So Fig. 1 (b) is through after simplifying, the structure that obtains is shown in (a) among Fig. 3.Wherein HVT representes the metal-oxide-semiconductor of high threshold voltage; LVT representes the metal-oxide-semiconductor of low threshold voltage.

Structure after the simplification has kept all Low-power Technology and the structural advantages of original structure.Meanwhile structure reduces unnecessary MOS transistor 10 (including two LFB each four MOS transistors and the resulting signal an inverter).

In order to prevent that traditional pulse from producing issuable problem (described in background technology) in the structure (Fig. 1 (a)), the present invention is revised as the structure in (b) among Fig. 3 with the pulse-generating circuit of Fig. 1 (a).Increased by two NMOS pipes: MPcg and MNcg, all directly by the CG signal controlling.The effect of MNcg is when CG becomes 1, and node 4 signals are dragged down, and node 1 and 4 can be moved to low level simultaneously like this, and the output node P of XOR gate can not produce high level, and CG just can cut off the generation of P place pulse well like this.And the effect of MPcg is for the influence to node 4 of the inverter that cuts off node 4 fronts, and MPcg can also reduce the leakage power of this inverter device under sleep state simultaneously.

The oscillogram that pulse produced before and after Fig. 4 (a), Fig. 4 (b) had provided and changed.Simulation waveform can be found out, when the circuit of Fig. 1 (a) is high in the CG saltus step, has produced an extra pulse, and this is unwanted.And amended circuit does not have unnecessary pulse.So not only guarantee the correctness of function, reduced the generation of pulse especially, reduced a part of power consumption.

The experiment simulation checking

Utilize pulse-generating circuit (among Fig. 3 (b)) and static latch circuit (among Fig. 3 (a)) after improving, formed bilateral pulse trigger along triggering, the node P (pulse output signals) in the (a) and (b) of Fig. 3 is linked together to get final product.For environment that is virtually reality like reality, the artificial circuit signal all flows to inside circuit through the buffer that two inverters are formed, as shown in Figure 5.

Utilize HSPICE and adopt SMIC 90nm technology library to carry out emulation (supply voltage VCCH=1V, low supply voltage VCCL adopts 0.8V), the result shows that speed and power consumption all have improvement.Following Fig. 6 has provided the emulation output waveform.Wherein Q1 is the Q end output of the DET-SRSFF after simplifying, and Q2 is the Q end output of the DET-SRSFF before simplifying.

Can see, be (under the mode of operation) between low period at CG, and the D signal can be transferred to the Q end in the hopping edge of clock.The two in logic can both operate as normal.Wherein the high level of SLEEP signal is narrower than CG, and the reason of She Zhiing has in document [1] and mentions like this: because the generation of CG control impuls, the power supply of SLEEP control static latch part is supplied with.So during CG was low level (mode of operation), it is low that SLEEP should be always, to provide the static latch part normal supply voltage.So in order to guarantee the circuit operate as normal, the pulse of SLEEP is narrower than CG.

Utilize the measurement functions of HSPICE, it is as shown in table 1 to obtain time of delay and power consumption (average power consumptions of 100 clock cycle):

Delay and the power consumption of DET-SRSFF before and after table 1 improves

Data in the table 1 show that the power consumption of the DET-SRSFF after the improvement all has improvement with postponing, and its medium velocity has improved 12.24%, and the power consumption lagged product has reduced by 19.56%.

The present invention improves with leakage feedback buffer circuit (LFB) the pulse-generating circuit of traditional DET-SRSFF.Under the prerequisite that keeps DET-SRSFF low-power consumption advantage fully, simplified the LFB structure.Revise pulse-generating circuit in addition, removed the redundant pulse that produces.Simulation result with HSPICE shows that the structure after the improvement all has advantage aspect power consumption and the speed at last.Power consumption lagged product aspect has 19.56% reduction, makes that the DET-SRSFF after improving adapts to the requirement of integrated circuit development for trigger more.

Above execution mode only is used to illustrate the present invention; And be not limitation of the present invention; The those of ordinary skill in relevant technologies field; Under the situation that does not break away from the spirit and scope of the present invention; Can also make various variations and modification; Therefore all technical schemes that are equal to also belong to category of the present invention, and scope of patent protection of the present invention should be defined by the claims.

Claims (3)

1. but a bilateral sweep trigger that keeps along the state that triggers is characterized in that, comprises interconnective pulse-generating circuit and static latch circuit, and said static latch circuit comprises leakage feedback pulse structure, and said leakage feedback pulse structure comprises:

3 PMOS pipe MP1～MP3 and 1 NMOS pipe MN3, first end of MP1 connects sleep signal, and first end of MP2 connects scanning output signal; Second end of MP1, MP2 links to each other, and connects power supply VCCH, and the 3rd end of MP1, MP2 links to each other, and connects first end of MP3; Second end of MP3 connects the inverted signal of said scanning output signal and first end of MN3, and the 3rd end of MP3 connects second end of MN3, the 3rd termination ground wire of MN3.

2. trigger as claimed in claim 1 is characterized in that, said pulse-generating circuit comprises 5 PMOS pipe MP7～MP10, MPcg; 5 NMOS manage MN7～MN10, MNcg; And 3 inverter INV1～INV3; First end of MP7 connects the clock pulse gate signal, and second end connects first end of MP8, and the 3rd end connects first end of MNcg and the 3rd end of MN8; Second end of MP8 connects first end of clock signal and MN7, and the 3rd end connects second end, first end of MN8 and first end of MP9 of MN7; The 3rd end of MN7 connects second end and the ground wire of MN8, and second end connects first end, first end of INV1 and second end of MP10 of inverter INV2; The 3rd end of INV2 connects another power supply VCCL, and the 4th end connects ground wire, and second end connects first end of INV3; The 3rd end of INV3 connects the 3rd end of MPcg, the 4th end ground connection, and second end connects second end, the 3rd end of MP9, the 3rd end of MN9, first end of MP10 and first end of MN10 of MNcg; The said power supply VCCL of second termination of MPcg, first end of the first termination MNcg; The 3rd end ground connection of MNcg; The 3rd end of the 3rd termination MN10 of MP10, second end of MN9, second end and the pulse output signals of MP9.

3. trigger as claimed in claim 1 or 2 is characterized in that, the voltage that the voltage that power supply VCCH is provided is provided greater than power supply VCCL.

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