CN102346368A - Method for manufacturing double pattern exposure mask and double pattern exposure method - Google Patents
Method for manufacturing double pattern exposure mask and double pattern exposure method Download PDFInfo
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- CN102346368A CN102346368A CN 201010240544 CN201010240544A CN102346368A CN 102346368 A CN102346368 A CN 102346368A CN 201010240544 CN201010240544 CN 201010240544 CN 201010240544 A CN201010240544 A CN 201010240544A CN 102346368 A CN102346368 A CN 102346368A
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Abstract
The invention relates to a method for manufacturing a double pattern exposure mask and a double pattern exposure method. The method for manufacturing the double pattern exposure mask comprises the following steps: 1, preparing a target pattern which comprises a first pattern and a second pattern, wherein the first pattern comprises at least two discrete first sprites, there are same first gaps between adjacent first sprites, and the characteristic dimension of each first sprite of the first pattern is less than the characteristic dimension of the second pattern; 2, forming a third pattern according to the first pattern, wherein the third pattern comprises discrete second sprites corresponding with the first sprites; 3, extracting the second sprites at the even position of the third pattern, and keeping the positions of the second sprites at the even position unchanged to form a fourth pattern; 4, writing the second pattern into a first mask; and 5, writing the fourth pattern into a second mask. The method for manufacturing the double pattern exposure mask has the advantages of simplicity and high decomposition precision.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly a kind of double-pattern exposure mask manufacture method and double-pattern exposure method.
Background technology
Semiconductor technology strides forward towards littler process node under the driving of Moore's Law constantly.Along with the continuous progress of semiconductor technology, the function of device is gradually become strong, but the semiconductor manufacture difficulty also grows with each passing day.And photoetching technique is a production technology the most key in the semiconductor fabrication process; Along with the semiconductor technology node enters into 65 nanometers, 45 nanometers; Even 32 lower nanometers; The ArF light source light lithography of existing 193nm can't satisfy the needs that semiconductor is made, and extreme ultraviolet light photoetching technique (EUV), multi-beam do not have the research focus that mask technique and nanometer embossing become photoetching candidate technologies of future generation.But above-mentioned photoetching candidate technologies of future generation still has inconvenience and defective, demands urgently further improving.
When the step that continues to extend forward when Moore's Law is irreversible; The double-pattern exposure technology becomes the optimal selection of industry undoubtedly; The double-pattern exposure technology only need be carried out very little change to existing photoetching infrastructure, just can fill up 45 nanometers effectively to 32 nanometers even more the photoetching technique of minor node is blank.The principle of double-pattern exposure technology resolves into the lower figure of discrete, the density of two covers with the highdensity circuitous pattern of a cover, then they is prepared on the wafer., publication number just disclosed a kind of double-pattern exposure technology in being 101109911 Chinese patent file; Comprise: the figure for preparing half earlier; Comprise and adopt the figure of preparation earlier to carry out exposure imaging, etching; And then prepare second half figure; Utilize the figure of back preparation to carry out exposure imaging, utilize hard mask or selective etch technology to accomplish whole photoetching process at last.
But; With the highdensity circuitous pattern of a cover resolve into that two covers are discrete, the lower figure of density is suitable complicacy and difficult; And the exposure second time of double-pattern exposure is perhaps carried out in the gap on the basis of the exposure figure first time; Very high to first time exposure figure and exposure figure accuracy requirement for the second time, existing decomposition technique needs the time of the labor fund a large amount of with input usually.
Summary of the invention
The problem that the present invention solves provides a kind of simple and high double-pattern exposure mask manufacture method and a kind of double-pattern exposure method of decomposition precision.
For addressing the above problem; The present invention provides a kind of double-pattern exposure mask manufacture method; Comprise: targeted graphical is provided; Said targeted graphical comprises first figure and second graph; Said first figure comprises at least two first discrete spirtes; Have the first identical gap between the first adjacent spirte, the characteristic dimension of first spirte of said first figure is less than the characteristic dimension of second graph; Form the 3rd figure according to said first figure; Said the 3rd figure comprises discrete second spirte corresponding with first spirte; The said second spirte position is corresponding with first interstitial site; Has second gap between the second adjacent spirte; Said second interstitial site is corresponding with the first spirte position; The size of said second spirte equals the size in first gap, and the size in said second gap equals the size of first spirte; Extract second spirte of the even bit in the 3rd figure, and keep the second spirte invariant position of even bit, form the 4th figure; Second graph is write first mask; The 4th figure is write second mask.
The present invention also provides a kind of double-pattern exposure method, comprising: the substrate that provides the surface to be formed with functional layer, the said functional layer pattern corresponding with targeted graphical to be formed; Second mask that employing writes the 4th figure forms the sacrifice figure on functional layer; On functional layer, form side wall layer, said side wall layer covers sacrifices figure; On side wall layer, form overlayer, and the planarization overlayer; First mask that employing writes second graph forms second graph in overlayer, and exposes side wall layer; Return the etching side wall layer, form side wall, said side wall is corresponding with first spirte of targeted graphical; Remove and sacrifice figure, expose functional layer; Is mask with side wall with the overlayer that is formed with second graph, and the etching functional layer forms and the targeted graphical graph of a correspondence in functional layer.
Compared with prior art; The present invention has the following advantages: double-pattern exposure mask manufacture method provided by the invention is simple and the decomposition precision is high; And adopt double-pattern exposure mask manufacture method of the present invention to realize double-pattern exposure mask through computer operation fully based on the original figure decomposition; Figure that forms and targeted graphical coupling, exposure accuracy is high.
Description of drawings
Fig. 1 is a double-pattern exposure mask manufacture method process flow diagram provided by the invention;
Fig. 2 is a targeted graphical synoptic diagram provided by the invention;
Fig. 3 carries out decomposing schematic representation with targeted graphical;
Fig. 4 is first pictorial diagram that decomposites from targeted graphical;
Fig. 5 is the second graph synoptic diagram that decomposites from targeted graphical;
Fig. 6 is the 3rd pictorial diagram that forms according to first figure;
Fig. 7 is the synoptic diagram of the 4th figure;
Fig. 8 is the contrast synoptic diagram that merges figure 5 and the 3rd figure;
Fig. 9 is that first son merges pictorial diagram;
Figure 10 is that second son merges pictorial diagram;
Figure 11 is that the 3rd son merges pictorial diagram;
Figure 12 is that the 4th son merges pictorial diagram;
Figure 13 is a double-pattern exposure method flow diagram provided by the invention;
Figure 14 to Figure 22 is the process synoptic diagram of double-pattern exposure method of the present invention.
Embodiment
The double-pattern exposure technology is the exposure technique commonly used that the semiconductor technology node enters into 65 nanometers; The double-pattern exposure technology only need be carried out very little change to existing photoetching infrastructure, just can be effectively to 45 nanometers in addition more the figure of minor node make public.The principle of double-pattern exposure technology resolves into the lower figure of discrete, the density of two covers with the highdensity circuitous pattern of a cover.But the targeted graphical of semiconductor manufacturing has high density usually, is broken down into two covers and can be used for very difficulty of double-pattern exposure.
For this reason, the present invention provides a kind of double-pattern exposure mask manufacture method, and Fig. 1 is a double-pattern exposure mask manufacture method process flow diagram provided by the invention, comprising:
Step S101; Targeted graphical is provided; Said targeted graphical comprises first figure and second graph; Said first figure comprises at least two first discrete spirtes; Have the first identical gap between the first adjacent spirte, the characteristic dimension of first spirte of said first figure is less than the characteristic dimension of second graph;
Step S102; Form the 3rd figure according to said first figure; Said the 3rd figure comprises discrete second spirte corresponding with first spirte; The said second spirte position is corresponding with first interstitial site; Has second gap between the second adjacent spirte; Said second interstitial site is corresponding with the first spirte position, and the size of said second spirte equals the size in first gap, and the size in said second gap equals the size of first spirte;
Step S103 extracts second spirte of the even bit in the 3rd figure, and keeps the second spirte invariant position of even bit, forms the 4th figure;
Step S104 writes first mask with second graph; The 4th figure is write second mask.
Below in conjunction with accompanying drawing, describe the double-pattern exposure mask manufacture method of the specific embodiment of the invention in detail.
Execution in step S101; In conjunction with reference to figure 2 and Fig. 1; Targeted graphical 100 is provided; Said targeted graphical 100 is used to form the particular functionality device; Grid for example; Conductive trench; Shallow trench isolation leaves; Electrode etc.; Targeted graphical 100 comprises first figure 101 and second graph 102 in this specific embodiment; Wherein second graph 102 can be positioned at first figure, 101 outsides; Perhaps second graph 102 can semi-surrounding first figure 101; Second graph 102 can surround first figure 101 entirely; Perhaps second graph 102 can be away from first figure 101, and particularly, the second graph 102 and first figure 101 can be decided with design requirement.First figure 101 comprises at least 2 first spirtes 1011, and wherein the visual device requirement of concrete number of first spirte 1011 and designing particularly, can be 2,20,30,34,100,200,400,3000,5000,6003,7000,10000; First spirte 1011 can be the linear pattern figure of less characteristic dimension, and first spirte 1011 has width and length; In the present embodiment, second graph 102 can be peripheral pattern, and second graph 102 is generally the figure than large-feature-size, and second graph 102 can be linear pattern figure, broken line type figure or other combined figures; Has the first identical gap 1012 between the first adjacent spirte 1011; Has the first identical gap 1012 between second graph 102 and adjacent first spirte 1011; Above-mentioned parameter is all set when element layout designs, and concrete parameter can visual organ spare demand and select.Need to prove that the width in the width of a sub-figure 1011 and one first gap 1012 is a pitch (Pitch) among the present invention.
After obtaining targeted graphical 100, targeted graphical 100 is resolved into independently first figure 101 and independently second graph 102.
In this specific embodiment, at first confirm the cutting position of layout figure 100: cutting position is dotted line 200 positions shown in Fig. 3.In other embodiments, cutting position changes according to the layout figure of reality.Be specially and disassemble than the second graph 102 of large-feature-size with than first figure 101 of small-feature-size; Form as shown in Figure 4 first figure 101 and second graph as shown in Figure 5 102; Wherein first figure 101 comprises first spirte 1011 and first gap 1012; It is to be noted; First gap 1012 of first figure 101 after the decomposition comprises first gap 1012 in the targeted graphical 100; The both sides of the edge (be positioned at the leftmost side and the rightmost side of Fig. 4) of a plurality of first spirtes 1011 in orientation that also comprise first figure 101 also respectively can be regarded as a gap respectively, and this gap is set at identical with first gap 1012.For the ease of understanding, first figure 101 after the decomposition will respectively add one first gap 1012 in a plurality of first spirtes 1011 orientation both sides.
Execution in step S102; In conjunction with reference to figure 6 and Fig. 1; Form the 3rd figure 103 according to said first figure 101; Said the 3rd figure 103 comprises a plurality of second spirtes 1031; Has second gap 1032 between the second adjacent spirte 1031; Said second spirte 1031 positions are corresponding with 1012 positions, first gap; 1032 positions, said second gap are corresponding with first spirte, 1011 positions; In the present embodiment; Because said second spirte 1031 is linear pattern figures; Said second spirte, 1031 width are for equaling first gap, 1012 width; Said second gap 1032 width equal first spirte, 1011 width, and the length of second spirte 1031 is identical with first spirte 1011.
Need to prove; Be positioned at also corresponding second spirte 1031 that converts in gap of a plurality of first both sides of the edge of spirte 1011 in orientation of first figure; And when embodiment is the linear pattern figure; The size of said second spirte refers to the length and the width of figure; In other embodiments, the size of said second spirte can be for specifically embodying the parameter of the second spirte characteristic.
Particularly, adopting domain process software execution in step S103, can adopt counter-rotating (Reverse) operation of PaintShop, forming the 3rd figure 103 according to said first figure 101.What need particularly point out is; The position of second spirte 1031 of the 3rd figure 103 that forms is corresponding with 1012 positions, first gap of second graph 102, and second gap 1032 of the 3rd figure 103 of formation is corresponding with first spirte, 1011 positions of second graph 102.In the present embodiment; Form length second spirte 1031 identical in 1012 positions, first gap of second graph 102, in first spirte, 1011 positions of second graph 102 formation width, second gap 1032 identical with second spirte 1031 with first spirte 1011.
Step S104, second spirte that extracts the even bit in the 3rd figure forms the 4th figure.
With reference to figure 7, with second spirte, 1031 formation the 4th figure 104 of the even bit in the 3rd figure 103.Said even bit can be from left to right an even bit during second spirte 1031 is arranged in the 3rd figure, also can be the even bit that second spirte 1031 is turned left from the right side in arranging in the 3rd figure, and above-mentioned two kinds of extractions do not influence final result.
Particularly; The step of extracting second spirte, 1031 formation the 4th figure 104 of the even bit in the 3rd figure 103 comprises: the second all spirte 1031 to the 3rd figure 103 merges formation merging figure 105; Understand for convenient; Please refer to Fig. 8; Fig. 8 is for merging the contrast synoptic diagram of figure 105 and the 3rd figure 103; Described merging specifically comprises: do a face territory according to the 3rd figure 103, this face territory is the minimum rectangle that comprises the second all spirtes 1031.Said union operation can adopt the semiconductor layout process software, with the 3rd figure 103 input semiconductor layout process softwares, adopts " merge " instruction, obtains merging figure 105.
Then; With reference to figure 9; Along 1031 orientations of second spirte; To merge 1 pitch of figure reduction; Add 1 second spirte 1031 in merging figure reduction position; Have second gap 1032 between the merging figure after second spirte 1031 that adds and 1 pitch of reduction, form first son and merge figure 106 (for ease of understanding, also provide merge figure 105 and the 3rd figure 103 at Fig. 9); With reference to Figure 10; Along 1031 orientations of second spirte; To merge 2 pitches of figure reduction; Add 2 second spirtes 1031 in merging figure reduction position; Has second gap 1032 between the merging figure after 2 second spirtes 1031 that add and 2 pitches of reduction; And have second gap 1032 between 2 second spirtes 1031, form second son and merge figure 107 (, also providing merging figure 105 and the 3rd figure 103) at Figure 10 for ease of understanding; Second son is merged figure 107 handle with doing common factor, first son merges figure 106 and the 3rd figure 103 is done the processing of occuring simultaneously, and two figures that occur simultaneously after handling are subtracted each other, and obtains being positioned at second spirte 1031 of second order digit.
Particularly, said 1 pitch of figure reduction that will merge is for forming the face territory according to merging figure 105, and this face territory is than merging figure 105 along little 1 pitch of second spirte, 1031 orientations.Same, will merge 2 pitches of figure reduction for forming the face territory according to merging figure 105, this face territory is than merging figure 105 along little 2 pitches of second spirte, 1031 orientations.
Second son is merged figure 107 and first son to be merged figure 106 and does to occur simultaneously to handle with the 3rd figure 103 after subtracting each other and be specially: (second son merges figure 107 ∩ the 3rd figure 103)-(the first son merging figure, 106 ∩ the 3rd figure 103); With reference to Figure 10; What the second son merging figure, 107 ∩ the 3rd figure 103 obtained is that first son merges figure 106 leftmost two second spirtes 1031; With reference to figure 9; What the first son merging figure, 106 ∩ the 3rd figure 103 obtained is that first son merges figure 106 leftmost second spirtes 1031, and (second son merges figure 107 ∩ the 3rd figure 103) then-(first sub figure 106 ∩ the 3rd figure 103 that merges) what obtain is second spirte 1031 that is positioned at second order digit.
With reference to Figure 11; Along 1031 orientations of second spirte; To merge 3 pitches of figure reduction; Add 3 second spirtes 1031 in merging figure reduction position; Has second gap 1032 between second spirte 1031 that adds and between the merging figure after second spirte 1031 that adds and 3 pitches of reduction; Form the 3rd son and merge figure 108, (, also providing merging figure 105 and the 3rd figure 103) at Figure 11 for ease of understanding; With reference to Figure 12; Along 1031 orientations of second spirte; To merge 4 pitches of figure reduction; Add 4 second spirtes 1031 in merging figure reduction position; Has second gap 1032 between second spirte 1031 that adds and between the merging figure after second spirte 1031 that adds and 4 pitches of reduction; Form the 4th son and merge figure 109, (, also providing merging figure 105 and the 3rd figure 103) at Figure 12 for ease of understanding; The 4th son is merged figure 109 and the 3rd son merge figure 108 and do the processing of occuring simultaneously with the 3rd figure 103 after subtracting each other, select second spirte 1031 that is positioned at four figures;
Handle second spirte 1031 of the even bit in selecting the 3rd figure 103 fully successively, even bit second spirte of selecting 1031 is superposeed by the origin-location, form the 4th figure 104.
The embodiment of second spirte of the even bit in said extracted the 3rd figure can handle through PaintShop, realizes extracting second spirte of the even bit in the 3rd figure through computer software.
Execution in step S105 writes first mask with second graph 102; The 4th figure 104 is write second mask.At first mask described in this specific embodiment and second mask is chrome substrate, also can use other substrates as known in the art in other embodiments.Said write is that optics is directly write, projection electron-beam direct writing or scanning electron microscope are directly write.
The present invention also provides a kind of mask that adopts above-mentioned double-pattern exposure mask manufacture method to form to carry out the double-pattern exposure method, with reference to Figure 13, comprises the steps:
Step S201, the substrate that provides the surface to be formed with functional layer, the said functional layer pattern corresponding to be formed with targeted graphical;
Step S202 adopts second mask that writes the 4th figure on functional layer, to form and sacrifices figure;
Step S203 forms side wall layer on functional layer, said side wall layer covers sacrifices figure;
Step S204 forms overlayer on side wall layer, and the planarization overlayer;
Step S205 adopts first mask that writes second graph in overlayer, to form second graph, and exposes side wall layer;
Step S206 returns the etching side wall layer, forms side wall, and said side wall is corresponding with first spirte of targeted graphical;
Step S207 removes and sacrifices figure, exposes functional layer;
Step S208 is mask with side wall with the overlayer that is formed with second graph, and the etching functional layer forms and the targeted graphical graph of a correspondence in functional layer.
Below in conjunction with accompanying drawing, describe the double-pattern exposure method of the specific embodiment of the invention in detail.
With reference to Figure 14, substrate 100 is provided, said substrate 100 is a silicon-based substrate, for example is that n type silicon substrate, p type silicon substrate perhaps are the SOI substrate; Said substrate 100 also can be silicon, germanium, gallium arsenide or silicon Germanium compound substrate; Said substrate 100 can also be the substrate that comprises the part of integrated circuit and other elements, or has the substrate of covering dielectric and metal film, specially illustrates at this, should too not limit protection scope of the present invention.
Be formed with functional layer 110 on the said substrate 100; Said functional layer is used to form the pattern corresponding with targeted graphical; Said targeted graphical is used to form the particular functionality device; Said functional layer can be dielectric layer, silicon epitaxial layers, polysilicon layer etc.; The material of said functional layer is corresponding with function element to be formed; Look the function element that need to form and decide, do not exemplify one by one at this.Said functional layer 110 can adopt chemical vapor deposition, physical vapour deposition (PVD), epitaxial growth, oxidation growth or atomic layer to pile up and be formed on the substrate 100; In the present embodiment; With the functional layer is that dielectric layer is that example is done exemplary illustrated, adopts chemical vapor deposition to form.
With reference to Figure 15, adopt second mask that writes the 4th figure on functional layer 110, to form and sacrifice figure 111.
Said sacrifice figure 111 material selective oxidation silicon or silicon nitrides, said sacrifice figure 111 is corresponding with the 4th figure.The concrete step of sacrificing figure 111 that forms comprises: adopt depositing operation on functional layer 110, to form sacrifice layer (not shown); Form photoresist layer in sacrificial layer surface; Second mask that employing writes the 4th figure makes public, develops said photoresist layer; Form the first photoresist figure (not shown) corresponding with the 4th figure; With the first photoresist figure is mask; The said sacrifice layer of etching forms the sacrifice figure 111 corresponding with the 4th figure, removes the first photoresist figure.
With reference to Figure 16, on functional layer 110, form side wall layer 120, said side wall layer 120 covers sacrifices figure 111.
Said side wall layer 120 materials select to have with sacrifice figure 111 material of high selective etching ratio, and as an embodiment, said sacrifice figure 111 materials are monox, and said side wall layer 120 materials are silicon nitride; Said sacrifice figure 111 materials are silicon nitride, and said side wall layer 120 materials are monox.
Adopt chemical vapor deposition method on functional layer 110, to form side wall layer 120, said side wall layer 120 forms through subsequent technique and is positioned at the side wall of sacrificing figure 111 both sides.
Need to prove that sacrifice figure 111 because side wall layer 120 covers, said side wall layer 120 surfaces are rough pattern.
With reference to Figure 17, on side wall layer 120, form overlayer 130, and planarization overlayer 130.
Said overlayer 120 is selected insulating material; For example monox, silicon nitride or silicon oxynitride; It is to be noted; The material of said overlayer 120 has high selective etching ratio with the material of side wall layer 120; Adopt chemical vapor deposition on side wall layer 120, to form overlayer 130; Said overlayer 130 thickness are wanted and the uneven of side wall layer can be filled up, and adopt CMP (Chemical Mechanical Polishing) process with side wall layer 120 planarizations then.
With reference to Figure 18, adopt first mask that writes second graph in overlayer 130, to form second graph, and expose side wall layer 120.
Concrete steps comprise: form photoresist layer in cover surface 130; Adopt first mask that writes second graph that said photoresist layer is made public, develops; Form the second photoresist figure corresponding with second graph; With the second photoresist figure is mask; Employing and side wall layer 120 have the etching technics of selective etching ratio, and etching overlayer 130 is until exposing side wall layer 120; In overlayer 120, form second graph, remove the second photoresist figure.
With reference to Figure 19, return etching side wall layer 120, form side wall 121, said side wall 121 is corresponding with first spirte of targeted graphical.
Said time etching technics also can be removed the side wall layer 120 that is positioned at the second graph position simultaneously, exposes the functional layer 110 that is positioned at the second graph position.
With reference to Figure 20, remove and sacrifice figure 111, expose functional layer 110.
Concrete, adopt with side wall 121 to have high selective etching comparison etching technics, remove and sacrifice figure 111, keep side wall 121, expose functional layer 110.
With reference to Figure 21, be mask with side wall 121 with the overlayer 130 that is formed with second graph, etching functional layer 110 forms and the targeted graphical graph of a correspondence in functional layer 110.
Particularly; Said side wall 121 is corresponding with first spirte of targeted graphical; And the overlayer 130 that is formed with second graph is corresponding with the second graph of targeted graphical; So; Is mask with side wall 121 with the overlayer 130 that is formed with second graph; Etching functional layer 110, the figure of formation are and the targeted graphical graph of a correspondence.
Wherein concrete etching technics can be selected according to the concrete material of functional layer 110.
With reference to Figure 22, remove overlayer 130 and side wall 121.
Concrete removal technology can be removed technology or wet etching removal technology for etching.
Double-pattern exposure mask manufacture method provided by the invention is simple and decompose the precision height, and adopt double-pattern exposure mask manufacture method of the present invention to form mask and carry out double exposure, the figure of formation and targeted graphical coupling, exposure accuracy is high.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art are not breaking away from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (7)
1. a double-pattern exposure mask manufacture method is characterized in that, comprising:
Targeted graphical is provided; Said targeted graphical comprises first figure and second graph; Said first figure comprises at least two first discrete spirtes; Have the first identical gap between the first adjacent spirte, the characteristic dimension of first spirte of said first figure is less than the characteristic dimension of second graph;
Form the 3rd figure according to said first figure; Said the 3rd figure comprises discrete second spirte corresponding with first spirte; The said second spirte position is corresponding with first interstitial site; Has second gap between the second adjacent spirte; Said second interstitial site is corresponding with the first spirte position; The size of said second spirte equals the size in first gap, and the size in said second gap equals the size of first spirte;
Extract second spirte of the even bit in the 3rd figure, and keep the second spirte invariant position of even bit, form the 4th figure;
Second graph is write first mask; The 4th figure is write second mask.
2. double-pattern exposure mask manufacture method as claimed in claim 1; It is characterized in that the step that second spirte that extracts the even bit in the 3rd figure forms the 4th figure comprises: n+1 second spirte of the 3rd figure merged to form merge figure; Along the second spirte orientation, will merge 1 pitch of figure reduction, add 1 second spirte in merging figure reduction position, have second gap between the merging figure after second spirte that adds and 1 pitch of reduction, form the first son merging figure; Along the second spirte orientation; To merge 2 pitches of figure reduction; Add 2 second spirtes merging figure reduction position, between 2 second spirtes that add and and 2 pitches of reduction after the merging figure between all have second gap, form second son and merge figure; Second son is merged figure 107 handle with doing common factor, first son merges figure 106 and the 3rd figure 103 is done the processing of occuring simultaneously, and two figures that occur simultaneously after handling are subtracted each other, and selects second spirte that is positioned at second order digit; Handle second spirte of the even bit in selecting the 3rd figure fully successively, even bit second spirte of selecting is formed the 4th figure.
3. double-pattern exposure mask manufacture method as claimed in claim 1 is characterized in that, first spirte is the linear pattern figure.
4. double-pattern exposure mask manufacture method as claimed in claim 1 is characterized in that, the width of second spirte equates that with the width in first gap width in second gap equates with the width of first spirte.
5. the mask that forms of any described double-pattern exposure mask manufacture method of employing such as claim 1 to 4 carries out the double-pattern exposure method, it is characterized in that,
The substrate that provides the surface to be formed with functional layer, the said functional layer pattern corresponding to be formed with targeted graphical;
Second mask that employing writes the 4th figure forms the sacrifice figure on functional layer;
On functional layer, form side wall layer, said side wall layer covers sacrifices figure;
On side wall layer, form overlayer, and the planarization overlayer;
First mask that employing writes second graph forms second graph in overlayer, and exposes side wall layer;
Return the etching side wall layer, form side wall, said side wall is corresponding with first spirte of targeted graphical;
Remove and sacrifice figure, expose functional layer;
Is mask with side wall with the overlayer that is formed with second graph, and the etching functional layer forms and the targeted graphical graph of a correspondence in functional layer.
6. double-pattern exposure method as claimed in claim 5 is characterized in that, the material of said side wall layer has high selective etching ratio with the material of sacrificing figure.
7. double-pattern exposure method as claimed in claim 5 is characterized in that, said tectal material has high selective etching ratio with the material of side wall layer.
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| CN103367156A (en) * | 2012-03-31 | 2013-10-23 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor device and method for forming fin field effect transistor |
| CN103367156B (en) * | 2012-03-31 | 2015-10-14 | 中芯国际集成电路制造(上海)有限公司 | The formation method of semiconductor device, the formation method of fin field effect pipe |
| CN103676484A (en) * | 2012-09-03 | 2014-03-26 | 中芯国际集成电路制造(上海)有限公司 | Method for exposing graphics of mask pate |
| CN103676484B (en) * | 2012-09-03 | 2016-04-27 | 中芯国际集成电路制造(上海)有限公司 | A kind of method that mask plate patterns is exposed |
| CN103441068A (en) * | 2013-08-16 | 2013-12-11 | 上海华力微电子有限公司 | Method for forming double patterning based on DARC mask structure |
| CN103441068B (en) * | 2013-08-16 | 2016-03-30 | 上海华力微电子有限公司 | Based on the double-pattern forming method of DARC mask structure |
| CN104777718A (en) * | 2015-04-09 | 2015-07-15 | 中国科学院上海光学精密机械研究所 | Detection method for wave aberration of projection objective of large-numerical-aperture photoetching machine |
| CN104777718B (en) * | 2015-04-09 | 2017-06-06 | 中国科学院上海光学精密机械研究所 | A kind of large-numerical aperture wave aberration of photo-etching machine projection objective detection method |
| CN109216163A (en) * | 2017-06-29 | 2019-01-15 | 中芯国际集成电路制造(上海)有限公司 | The manufacturing method of semiconductor devices |
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