CN102339842A - Implementation method of TSV (Through Silicon Via)-free high-reliability image sensor encapsulation structure - Google Patents
Implementation method of TSV (Through Silicon Via)-free high-reliability image sensor encapsulation structure Download PDFInfo
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- CN102339842A CN102339842A CN2011102947286A CN201110294728A CN102339842A CN 102339842 A CN102339842 A CN 102339842A CN 2011102947286 A CN2011102947286 A CN 2011102947286A CN 201110294728 A CN201110294728 A CN 201110294728A CN 102339842 A CN102339842 A CN 102339842A
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Abstract
The invention relates to an implementation method of a TSV (Through Silicon Via)-free high-reliability image sensor encapsulation structure. The structure comprises a chip body (1), wherein the upper surface of the chip body is provided with an isolation layer (5), and a transparent cover plate (6) is arranged on the isolation layer; a silicon groove (8) is formed on the chip body; an insulation layer (9) is selectively arranged on the lower surface of the chip body, the lateral wall of the silicon groove (8) and the lower surface of an exposed intra-chip passivation layer (2); the intra-chip passivation layer (2) is provided with a blind hole (10); a metal line layer (11) is selectively formed on the surface of the isolation layer (9) and in the blind hole (10); a line protection layer (12) is selectively arranged on the isolation layer (9) and the metal line layer (11); and a welded ball (13) is arranged on a part on which the line protection layer (12) is exposed, of the metal line layer (11). The invention provides the TSV-free high-reliability image sensor encapsulation structure which has the characteristics of simple structure, good interconnection reliability, simple process and low cost, as well as a technological method for implementing the structure.
Description
Technical field
The present invention relates to a kind of implementation method of wafer level image sensor package structure.Belong to the semiconductor packaging field.
Background technology
Imageing sensor is to convert external optical signals to the signal of telecommunication, and institute's signal of telecommunication that obtains is through handling the semiconductor device that can finally form images.The wafer level image sensor package is novel image sensor package mode, closes encapsulation and compares than conventional wire is strong, has that package dimension is little, a photosensitive area advantage such as pollution not when low price and downstream assembling, is receiving increasing concern.Because the chip electrode of imageing sensor or chip internal metal level and photosensitive area all are positioned at chip front side; So wafer-level packaging just need give over to photosensitive window with chip front side; And the chip internal metal level is redistributed chip back from chip front side, to realize with extraneous interconnected.
Realize that this positive back side is shifted and to pass through silicon through hole (Through Silicon Via) interconnected method.The silicon through hole is interconnected promptly to utilize diameter that the method for dry etching forms silicon through hole, silicon through hole on the silicon body of chip back about 100um, and the degree of depth is about 100um.Comprise that to exposing silicon the silicon in body and the hole carries out the insulating processing then, and need leave interconnected window in the bottom, hole so that follow-up filling metal contacts with the formation of chip internal metal level.Then need in the hole, fill metal, and redistribution metallic circuit layer.This wafer level image sensor package mode is interconnected owing to having introduced the silicon through hole, makes encapsulating structure complicated; And that is that all right is ripe for silicon through hole interconnection technique; Often, cause this type to utilize the interconnected wafer level image sensor package of carrying out of silicon through hole to have the low problem of big, the interconnected reliability of technology difficulty because imperfect and metal filled unreal the causing of bad, the interconnected window that insulate in the hole lost efficacy or reliability is bad.Simultaneously, the interconnected process complexity of silicon through hole also causes adopting this technological wafer level image sensor package price comparison expensive.
Summary of the invention
The objective of the invention is to overcome the deficiency of current wafer level image sensor package mode, provide not have simple in structure, interconnected good reliability, technology simply, the crystalline substance of characteristics does not have the implementation method of silicon through hole high reliability image sensor package structure cheaply.
The objective of the invention is to realize like this: a kind of implementation method of not having silicon through hole high reliability image sensor package structure; Said structure comprises the chip body that is provided with chip internal passivation layer, chip internal metal level and photosensitive area; Upper surface at the chip body is provided with separator, and separator does not cover or be covered in the chip photosensitive area; Euphotic cover plate is set on separator, when separator is not covered in the chip photosensitive area, forms cavity between euphotic cover plate, separator and the chip body; On the chip body, form silicon trench, and directly stop at the lower surface of chip internal passivation layer bottom the silicon trench, make chip internal passivation layer lower surface expose out; Lower surface at chip body lower surface, silicon trench sidewall and the chip internal passivation layer that exposes optionally is provided with insulating barrier; On the chip internal passivation layer, form blind hole, and blind hole stops at the chip internal layer on surface of metal; In surface of insulating layer and blind hole, optionally form the metallic circuit layer; On insulating barrier and metallic circuit layer, the route protection layer is set optionally; The place of exposing the route protection layer at the metallic circuit layer is provided with soldered ball; The implementation method of said structure comprises following technical process:
1), passes through to apply, makes public, develops, solidifies perhaps simple coating processes at the surperficial separator that forms of euphotic cover plate;
2), through strong method of closing, make separator and chip bulk junction altogether; Before preferred strong the closing on divider wall glue coated, form or increase strong adhesion of closing between back separator and the wafer;
3) method of, removing through wafer abrasive disc and stressor layers obtains the target thickness of chip body;
4), combine the method for silicon etching to form silicon trench through photoetching;
5), the method through photoetching forms insulating barrier;
6), directly carry out reactive ion etching through utilizing the insulating barrier opening, perhaps first photoetching forms opening, carries out reactive ion etching then, the method for removing photoresist at last again forms blind hole;
7), the method through sputter, photoetching, plating or chemical plating forms the metallic circuit layer;
8), the method through photoetching forms the route protection layer;
9), through placing soldered ball or printing solder, the method that refluxes then formation soldered ball.
The present invention does not have the implementation method of silicon through hole high reliability image sensor package structure, and said insulating barrier is at the reservation opening at the interconnected place of needs.
The present invention does not have the implementation method of silicon through hole high reliability image sensor package structure, and the reservation opening at said interconnected place overlaps with blind hole.
The present invention does not have the implementation method of silicon through hole high reliability image sensor package structure, and the reservation opening size at said interconnected place is greater than the blind hole size.
The present invention does not have the implementation method of silicon through hole high reliability image sensor package structure, and when said separator covered photosensitive area, separator was selected light transmissive material for use.
The present invention does not have the implementation method of silicon through hole high reliability image sensor package structure; Said chip internal passivation layer and chip internal metal level are multilayers, and blind hole is formed at ground floor chip internal passivation layer and stops on the chip internal metal level adjacent with the first chip internal passivation layer in this encapsulating structure.
The invention has the beneficial effects as follows:
1,, realizes that through the method that forms filling wiring in insulating barrier, blind hole and the hole chip signal of telecommunication transfers to chip back from chip front side then through forming silicon trench and stopping at the surface of chip internal passivation layer; Compare with the silicon through hole is interconnected, structure is simple relatively; And because the channel bottom size that forms is big and the chip internal passivation layer thickness is thinner, the filling wiring technology difficulty reduces in follow-up blind hole and the hole, has avoided owing to the metal filled unreal bad problem of reliability that causes in the silicon through hole.
2, insulating barrier comprises that its opening forms through the method for photoetching, insulating barrier attaching surface relatively flat, and technology is fairly simple; Form insulation and the silicon through hole is interconnected because the nonisulated sexual needs of silicon are inner in the silicon hole, and form opening, the technology more complicated.
3, owing to avoid adopting silicon through hole interconnection technique, packaging technology is simplified, and packaging cost reduces.
Description of drawings
Fig. 1 is the tangent plane sketch map of the no silicon through hole high reliability image sensor package structure that the present invention relates to, and diagram separator 5 is not covered in photosensitive area 4, thereby forms cavity 7.
Fig. 2 is the tangent plane sketch map of the no silicon through hole high reliability image sensor package structure that the present invention relates to, and separator 5 is covered in photosensitive area 4 in the diagram.
Fig. 3 is the tangent plane sketch map of the no silicon through hole high reliability image sensor package structure that the present invention relates to, and the insulating barrier opening overlaps with blind hole in the diagram.
Fig. 4 is the tangent plane sketch map of the no silicon through hole high reliability image sensor package structure that the present invention relates to, and the insulating barrier opening size is greater than blind hole in the diagram.
Reference numeral among the figure:
Embodiment
Referring to Fig. 1, Fig. 1 is the tangent plane sketch map of the no silicon through hole high reliability image sensor package structure (band cavity type) that the present invention relates to.Can find out by Fig. 1; The present invention does not have silicon through hole high reliability image sensor package structure; Comprise the chip body 1 that is provided with chip internal passivation layer 2, chip internal metal level 3 and photosensitive area 4; Chip internal passivation layer, chip internal metal level and photosensitive area all are structures that image sensor chip itself has, and do not belong to the encapsulation category that patent of the present invention relates to.Upper surface at chip body 1 is provided with separator 5, and separator 5 does not cover chip photosensitive area 4.Euphotic cover plate 6 is set on separator 5.Form cavity 7 between euphotic cover plate 6, separator 5 and the chip body 1.On chip body 1, form silicon trench 8, and silicon trench 8 bottoms directly stop at the lower surface of chip internal passivation layer 2, make chip internal passivation layer 2 lower surfaces expose out.Depend on that this body structure of chip, chip internal passivation layer thickness are usually less than 5 μ m.Lower surface at chip body 1 lower surface, silicon trench 8 sidewalls and the chip internal passivation layer 2 that exposes optionally is provided with insulating barrier 9.On chip internal passivation layer 2 and chip internal metal level 3, form blind hole 10, and blind hole 10 stops at separator 5 inside.Because the chip internal passivation layer of imageing sensor and chip internal metal level be multilayer normally, blind hole 10 is formed at ground floor chip internal passivation layer and stops on the chip internal metal level adjacent with the first chip internal passivation layer in this optional encapsulating structure.In insulating barrier 9 surfaces and blind hole 10, optionally form metallic circuit layer 11, thereby the electric signal of chip is redistributed chip back from the chip internal metal level.On insulating barrier 9 and metallic circuit layer 11, route protection layer 12 is set optionally.The place of exposing route protection layer 12 at metallic circuit layer 11 is provided with soldered ball 13.
Said insulating barrier 9 is at the reservation opening at the interconnected place of needs.
Fig. 2 is the tangent plane sketch map of the no silicon through hole high reliability image sensor package structure (not with cavity type) that the present invention relates to.Than Fig. 1, the difference of Fig. 2 is that separator 5 is covered in photosensitive area 4, thereby does not form cavity 7.When separator 5 covered photosensitive area 4, preferred, separator 5 was selected light transmissive material for use, and euphotic cover plate is an optical glass.
The starting point of whole encapsulation is the wafer of being made up of the chip body 1 of integrated chip internal passivation layer 2, chip internal metal level 3 and photosensitive area 4, obtains not having silicon through hole high reliability image sensor package structure through processes:
1), passes through to apply, makes public, develops, solidifies perhaps simple coating processes at the surperficial separator that forms of euphotic cover plate;
2), through strong method of closing, make separator and chip bulk junction altogether; Before preferred strong the closing on divider wall glue coated, form or increase strong adhesion of closing between back separator and the wafer;
3) method of, removing through wafer abrasive disc and stressor layers obtains the target thickness of chip body;
4), combine the method for silicon etching to form silicon trench through photoetching;
5), the method through photoetching forms insulating barrier;
6), directly carry out reactive ion etching through utilizing the insulating barrier opening, perhaps first photoetching forms opening, carries out reactive ion etching then, the method for removing photoresist at last again forms blind hole;
7), the method through sputter, photoetching, plating or chemical plating forms the metallic circuit layer;
8), the method through photoetching forms the route protection layer;
9), through placing soldered ball or printing solder, the method that refluxes then formation soldered ball.
Referring to Fig. 3, Fig. 3 is the tangent plane sketch map of the implementation method of the no silicon through hole high reliability image sensor package structure that the present invention relates to, and the insulating barrier opening overlaps with blind hole in the diagram.
Referring to Fig. 4, Fig. 4 is the tangent plane sketch map of the implementation method of the no silicon through hole high reliability image sensor package structure that the present invention relates to, and the insulating barrier opening size is greater than blind hole in the diagram.
Claims (7)
1. implementation method of not having silicon through hole high reliability image sensor package structure; Comprise the chip body (1) that is provided with chip internal passivation layer (2), chip internal metal level (3) and photosensitive area (4); It is characterized in that: the upper surface at chip body (1) is provided with separator (5), and separator (5) does not cover or be covered in chip photosensitive area (4); Euphotic cover plate (6) is set on separator (5), when separator (5) is not covered in chip photosensitive area (4), forms cavity 7 between euphotic cover plate 6, separator 5 and the chip body 1; Go up formation silicon trench (8) at chip body (1), and directly stop at the lower surface of chip internal passivation layer (2) bottom the silicon trench (8), make chip internal passivation layer (2) lower surface expose out; Lower surface at chip body (1) lower surface, silicon trench (8) sidewall and the chip internal passivation layer (2) that exposes optionally is provided with insulating barrier (9); Go up formation blind hole (10) at chip internal passivation layer (2), and blind hole (10) stops at chip internal metal level (3) surface; In insulating barrier (9) surface and blind hole (10), optionally form metallic circuit layer (11); On insulating barrier (9) and metallic circuit layer (11), route protection layer (12) is set optionally; The place of exposing route protection layer (12) at metallic circuit layer (11) is provided with soldered ball (13); The implementation method of said structure comprises following technical process:
1), passes through to apply, makes public, develops, solidifies perhaps simple coating processes at the surperficial separator that forms of euphotic cover plate;
2), through strong method of closing, make separator and chip bulk junction altogether; Before preferred strong the closing on divider wall glue coated, form or increase strong adhesion of closing between back separator and the wafer;
3) method of, removing through wafer abrasive disc and stressor layers obtains the target thickness of chip body;
4), combine the method for silicon etching to form silicon trench through photoetching;
5), the method through photoetching forms insulating barrier;
6), directly carry out reactive ion etching through utilizing the insulating barrier opening, perhaps first photoetching forms opening, carries out reactive ion etching then, the method for removing photoresist at last again forms blind hole;
7), the method through sputter, photoetching, plating or chemical plating forms the metallic circuit layer;
8), the method through photoetching forms the route protection layer;
9), through placing soldered ball or printing solder, the method that refluxes then formation soldered ball.
2. a kind of implementation method of not having silicon through hole high reliability image sensor package structure according to claim 1, it is characterized in that: said insulating barrier (9) is at the reservation opening at the interconnected place of needs.
3. a kind of implementation method of not having silicon through hole high reliability image sensor package structure according to claim 2, it is characterized in that: the reservation opening at said interconnected place overlaps with blind hole (10).
4. a kind of implementation method of not having silicon through hole high reliability image sensor package structure according to claim 2, it is characterized in that: the reservation opening size at said interconnected place is greater than blind hole (10) size.
5. according to claim 1 or 2 or 3 or 4 described a kind of implementation methods of not having silicon through hole high reliability image sensor package structure, it is characterized in that: when said separator (5) covered photosensitive area (4), separator (5) was selected light transmissive material for use.
6. according to claim 1 or 2 or 3 or 4 described a kind of implementation methods of not having silicon through hole high reliability image sensor package structure; It is characterized in that: said chip internal passivation layer (2) and chip internal metal level (3) are multilayers, and blind hole in this encapsulating structure (10) is formed at ground floor chip internal passivation layer and stops on the chip internal metal level adjacent with the first chip internal passivation layer.
7. according to claim 1 or 2 or 3 or 4 described a kind of implementation methods of not having silicon through hole high reliability image sensor package structure, it is characterized in that: said step 2), before strong the closing on divider wall glue coated.
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| CN2011102947286A CN102339842A (en) | 2011-10-08 | 2011-10-08 | Implementation method of TSV (Through Silicon Via)-free high-reliability image sensor encapsulation structure |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102637713A (en) * | 2012-03-31 | 2012-08-15 | 江阴长电先进封装有限公司 | Method for packaging image sensor comprising metal micro-bumps |
| CN105742301A (en) * | 2014-12-29 | 2016-07-06 | 爱思开海力士有限公司 | Embedded image sensor package and method of fabricating the same |
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Application publication date: 20120201 |