CN102339746B - Form the method for flat dielectric layer - Google Patents
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- CN102339746B CN102339746B CN201110298227.5A CN201110298227A CN102339746B CN 102339746 B CN102339746 B CN 102339746B CN 201110298227 A CN201110298227 A CN 201110298227A CN 102339746 B CN102339746 B CN 102339746B
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Abstract
Form a method for flat dielectric layer, comprising: wafer is provided; Described wafer is formed first medium layer, and the thickness at the edge of described dielectric layer is greater than the thickness of core; Chemico-mechanical polishing is carried out to described first medium layer; Described first medium layer forms second dielectric layer, and the thickness at the edge of described second dielectric layer is greater than the thickness of core.The first medium layer formed by the embodiment of the present invention, it is effectively reduced in the difference in thickness at crystal circle center's part and edge, and the rate of finished products being formed at the resulting devices of crystal round fringes is effectively improved.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly relate to a kind of method forming flat dielectric layer.
Background technology
Semiconductor fabrication process utilizes batch process technology, can form a large amount of complex devices on same wafer.Along with developing rapidly of very lagre scale integrated circuit (VLSIC), the integrated level of chip is more and more higher, and the size of components and parts is more and more less, also more and more higher to the requirement of semiconductor fabrication process accuracy.
In integrated circuit fabrication process, after wafer is produced the plain conductor of component structure or patterning, need first to deposit one deck dielectric layer thereon, and then carry out the deposition of follow-up metal level.According to the difference of function, being used for the dielectric layer of isolating metal wire and element is commonly called interlayer dielectric layer (Inter-LayerDielectric; ILD), being used for the dielectric layer of isolating metal wire and other plain conductors is commonly called metal interlamination medium layer (Inter-MetalDielectric; IMD).
In prior art, described dielectric layer is oxide skin(coating), usual employing as common silicon dioxide, through doping silicon dioxide (as BSG, BPSG, PSG), or more novel low-k (low-K) material in recent years, as carbon-doped silicon oxide (SiOC), mix the oxygen containing materials such as fluorodioxy SiClx (SiOF).Described dielectric layer is normally by chemical vapour deposition technique (ChemicalVaporDeposition; CVD) formed.In recent years, due to high density plasma CVD (HighDensityPlasmaCVD; HDP-CVD) oxide skin(coating) formed has good ditch and fills (GapFilling) ability and lower dielectric constant, and HDP-CVD has become the common method forming described dielectric layer in high integration element.
By depositing the in uneven thickness of the described dielectric layer of formation.And along with the height of crystal column surface pattern rises and falls, described dielectric layer surface has certain difference in height (StepHeight; SH).Therefore, prior art can use chemico-mechanical polishing (ChemicalMechanicalPolishing; CMP) technique carries out planarization to described dielectric layer.Prior art provides a kind of CMP method, if publication number is the application for a patent for invention of CN101934494A.Please refer to Fig. 1, treat that the wafer 4 polished 3 of planarization is pressed on grinding pad 2, grinding head 3 drives wafer 4 to rotate, abrasive disk 1 drives grinding pad 2 to rotate, ground slurry Filling Pipe (SlurryArm) 5 injects ground slurry, under the acting in conjunction of chemical grinding and mechanical lapping, the surface of wafer 4 is flattened.
But after above-mentioned technique, the rate of finished products being formed at the resulting devices of wafer edge portion is lower, is only about 38.76%.
Therefore, for above-mentioned technical problem, need to improve the rate of finished products being formed at the resulting devices of wafer edge portion.
Summary of the invention
The problem that the present invention solves is to provide a kind of method forming flat dielectric layer, improves the rate of finished products being formed at the resulting devices of wafer edge portion.
For solving the problem, the invention provides a kind of method forming flat dielectric layer, comprising:
Wafer is provided;
Described wafer is formed first medium layer, and the thickness at the edge of described first medium layer is greater than the thickness of core;
Chemico-mechanical polishing is carried out to described first medium layer;
Described first medium layer forms second dielectric layer.
Alternatively, the thickness at the edge of described second dielectric layer is greater than the thickness of core.
Alternatively, the thickness difference of the margin and center part of described second dielectric layer equals at the described core of first medium layer carried out after described chemico-mechanical polishing and the thickness difference of marginal portion.
Alternatively, described first medium layer and second dielectric layer are silica.
Alternatively, when forming described first medium layer and/or described second dielectric layer, the distance of described wafer and air inlet is 180 mil ~ 220 mils.
Alternatively, PECVD device is adopted to form described first medium layer, predecessor comprises SiH4, the scope of radio-frequency power is 200 watts ~ 1000 watts, the scope of pressure is that 5 holder ~ 10 are held in the palm, the scope of temperature is 350 degrees Celsius ~ 450 degrees Celsius, and the scope of gas flow is 1000 milli gram/minute ~ 2000 milli gram/minute.
Alternatively, PECVD is adopted to form described first medium layer, predecessor comprises TEOS, the scope of radio-frequency power is 200 watts ~ 1000 watts, the scope of pressure is that 5 holder ~ 10 are held in the palm, the scope of temperature is 350 degrees Celsius ~ 450 degrees Celsius, the scope of gas flow be 200 standard milliliters/minute ~ 800 standard milliliters/minute.
Alternatively, the pre-thickness of described first medium layer is no more than 10K dust.
Alternatively, the scope of the thickness of described second dielectric layer is 800 dusts ~ 2K dust.
Alternatively, PECVD device is adopted to form described second dielectric layer, predecessor comprises SiH4, the scope of radio-frequency power is 200 watts ~ 1000 watts, the scope of pressure is that 5 holder ~ 10 are held in the palm, the scope of temperature is 350 degrees Celsius ~ 450 degrees Celsius, and the scope of gas flow is 1000 milli gram/minute ~ 2000 milli gram/minute.
Alternatively, PECVD is adopted to form described second dielectric layer, predecessor comprises TEOS, the scope of radio-frequency power is 200 watts ~ 1000 watts, the scope of pressure is that 5 holder ~ 10 are held in the palm, the scope of temperature is 350 degrees Celsius ~ 450 degrees Celsius, the scope of gas flow be 200 standard milliliters/minute ~ 800 standard milliliters/minute.
Alternatively, when carrying out described chemico-mechanical polishing, the scope of barrier film (membrane) pressure is 2 pounds/square inch ~ 3 pounds/square inch, the scope of inner tube pressure is 3 pounds/square inch ~ 4 pounds/square inch, the scope keeping pressure is 3 pounds/square inch ~ 4 pounds/square inch, the scope of lap speed is 90 revs/min ~ 140 revs/min, and the scope of grinding head rotating speed is 90 revs/min ~ 140 revs/min.
Compared with prior art, the method for formation flat dielectric layer that the embodiment of the present invention provides has the following advantages:
First, by forming centre portion thinner, first medium layer that edge is thick, CMP (Chemical Mechanical Polishing) process is carried out to it, because the grinding rate of crystal round fringes is higher than the grinding rate of core, therefore, it is possible to the thickness difference of the crystal circle center's part reduced because chemico-mechanical polishing causes and marginal portion.
Further, by covering on first medium layer, edge is thick, the second dielectric layer of centre portion thinner, can reduce the thickness difference at crystal circle center's part and the edge caused because of chemico-mechanical polishing further, thus obtain comparatively smooth dielectric layer.
Further, by reducing the pre-thickness of the first medium layer formed, reduce the thickness needing to be polished, thus reduce the thickness offset because crystal circle center partly brings with the grinding rate difference at edge.
Further, by optimizing CMP (Chemical Mechanical Polishing) process, reduce crystal circle center's part and the grinding rate difference at edge.
By the dielectric layer that the embodiment of the present invention is formed, it is effectively reduced in the difference in thickness at crystal circle center's part and edge, and the rate of finished products being formed at the resulting devices of crystal round fringes is effectively improved.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of the CMP (Chemical Mechanical Polishing) process of prior art;
Fig. 2 is the schematic flow sheet of the method for the formation flat dielectric layer of one embodiment of the present of invention;
Fig. 3 to Fig. 5 is the cross-sectional view of the method for the formation flat dielectric layer of one embodiment of the present of invention.
Embodiment
From background technology, the method for existing formation dielectric layer is, first by process deposits one deck dielectric layers such as chemical vapour deposition (CVD)s, then by the surface of chemico-mechanical polishing (CMP) technique planarized dielectric layer.
Inventor finds, the rate of finished products being usually formed in the resulting devices of crystal round fringes is lower than the rate of finished products of the resulting devices being formed in crystal circle center's part.After further research, inventor finds to utilize after prior art carries out polishing to described dielectric layer, and the thickness of described dielectric layer is also uneven, and the thickness that the Thickness Ratio being positioned at the described dielectric layer of crystal round fringes is positioned at the described dielectric layer of crystal circle center's part is little.Such as, after chemico-mechanical polishing is carried out to the wafers of 8 inches, because grinding head is different to wafer each several part applied pressure, and the linear velocity of crystal round fringes is greater than the linear velocity of core when grinding head rotates, it is larger than the grinding rate of the described dielectric layer being positioned at crystal circle center's part to cause the grinding rate of the described dielectric layer being positioned at crystal round fringes, finally causes little 200 dust ~ 500 dusts of thickness of the described dielectric layer being positioned at crystal circle center's part in distance 80 millimeters, the wafer center of circle with the Thickness Ratio of the described dielectric layer locating region.When the material of described dielectric layer is phosphosilicate glass (PhosphosilicateGlass; PSG), time, the difference of above-mentioned thickness can be more obvious.The marginal portion of wafer can cause two kinds of results than the phenomenon of centre portion thinner: one is the electric capacity that electric capacity between the upper and lower double layer of metal in crystal round fringes place can be greater than crystal circle center, and this can exert an adverse impact to the back segment speed (backendRCdelay) of product; Two is when the thickness of dielectric layers of wafer edge portion is inadequate, can produce electric leakage between its upper and lower double layer of metal, and even the dielectric layer of this part may be removed completely by CMP, then up and down can direct short-circuit between double layer of metal.Above-mentioned two situations finally all can make the electrical property of the device of formation be affected.Therefore, the rate of finished products being positioned at the resulting devices of crystal round fringes is lower.
For improving the rate of finished products being positioned at the resulting devices of crystal round fringes, the invention provides a kind of method forming flat dielectric layer, please refer to Fig. 2, comprising: step S1: wafer is provided; Step S2: form first medium layer on described wafer, the thickness at the edge of described first medium layer is greater than the thickness of core; Step S3: chemico-mechanical polishing is carried out to described first medium layer; And step S4: on described first medium layer, form second dielectric layer.
Adopt the method that the embodiment of the present invention provides, by first forming centre portion thinner, the first medium layer that edge is thick, chemico-mechanical polishing is carried out to described first medium layer, then on described first medium layer, second dielectric layer is formed again, comparatively smooth dielectric layer can be formed, improve the electrical property of resulting devices, thus improve the rate of finished products being positioned at the resulting devices of crystal round fringes.
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, are described in detail embodiments of the invention below in conjunction with accompanying drawing.A lot of detail has been set forth so that fully understand the present invention in description below.But the present invention can implement to be much different from other modes described here, those skilled in the art can when without prejudice to doing similar popularization when intension of the present invention, therefore the present invention is by the restriction of following public specific embodiment.
Referring to figs. 2 and 3, perform step S1, wafer 11 is provided.
The surface of described wafer 11 can be formed with various component structure or plain conductor (not shown).
Referring to figs. 2 and 3, perform step S2, described wafer is formed first medium layer 12, and the thickness at the edge of described first medium layer 12 is greater than the thickness of core.
Core of the present invention refers to crystal circle center to be the center of circle, and radius is the region of the circle of 75 millimeters ~ 80 millimeters, edge of the present invention refers to the region beyond described core.
The material of described first medium layer 12 comprises: silicon dioxide, through doping silicon dioxide (as BSG, BPSG, PSG), or more novel low-k (low-K) material in recent years, as carbon-doped silicon oxide (SiOC), mix the oxygen containing materials such as fluorodioxy SiClx (SiOF).The method forming described first medium layer 12 comprises: chemical vapour deposition (CVD), high-density plasma vapour deposition etc.The formation method of dielectric layer is well known to those skilled in the art, and does not repeat them here.
The first medium layer 12 formed by methods such as chemical vapour deposition (CVD)s is not smooth, and can rise and fall by height along with the various components and parts on wafer 11 surface, plain conductor and groove etc., there is certain difference in height (not shown), therefore need to adopt chemico-mechanical polishing (CMP) equipment to carry out planarization to it.But the grinding rate of usual described CMP equipment to the edge of described first medium layer 12 is greater than the grinding rate to its core, makes after the cmp process, and the thickness at the edge of described first medium layer 12 is less than the thickness of its core usually.For this reason, the present invention forms the thick and first medium layer 12 of centre portion thinner in edge by deposition, it is in uneven thickness that the difference that compensate for above-mentioned grinding rate to a certain extent causes, and makes described first medium layer 12 can obtain comparatively smooth surface after the cmp process.
In the present embodiment, when forming described first medium layer 12, by the size at interval (spacer) between wafer and air inlet (showerhead) described in adjustment settling chamber, to form centre portion thinner, described first medium layer 12 that edge is thick.Alternatively, the distance range of described wafer and described air inlet is 180 mil ~ 220 mils (1 mil equals 25.39999918 microns).
Described first medium layer 12 comprises silica, silicon nitride, silicon oxynitride or its combination in any.
CVD (PlasmaEnhancedCVD can be strengthened by using plasma; PECVD) depositing operation forms described first medium layer 12, and when described first medium layer 12 is silica, the predecessor of the described first medium layer 12 of formation comprises tetraethoxysilane (TEOS) or SiH
4deng.When adopting predecessor TEOS or SiH4, concrete technological parameter is: the scope of radio-frequency power is 200 watts ~ 1000 watts, and the scope of pressure is that 5 holder ~ 10 are held in the palm, and the scope of temperature is 350 degrees Celsius ~ 450 degrees Celsius.
Again particularly, when predecessor adopts TEOS, the scope of gas flow be 200 standard milliliters/minute ~ 800 standard milliliters/minute.
When predecessor adopts SiH
4during technique, the scope of gas flow is 1000 milli gram/minute ~ 2000 milli gram/minute.
As one embodiment of the invention, first medium layer 12 adopts silica, and using plasma strengthens CVD (PlasmaEnhancedCVD; PECVD) depositing operation is formed, and during deposition, the distance of described wafer and described air inlet is 195 mils, predecessor employing TEOS, and radio-frequency power is 600 watts, and pressure is 6 holders, and temperature is 400 degrees Celsius, the flow of TEOS be 500 standard milliliters/minute.
As another embodiment of the present invention, first medium layer 12 adopts silica, and using plasma strengthens CVD (PlasmaEnhancedCVD; PECVD) depositing operation is formed, and during deposition, the distance of described wafer and described air inlet is 205 mils, and predecessor adopts SiH
4, radio-frequency power is 600 watts, and pressure is 7 holders, and temperature is 400 degrees Celsius, SiH
4flow be 1500 milli gram/minute.
Adopt above-mentioned technique, can form intermediate thin, first medium layer 12 that edge is thick, the thickness difference scope of mid portion and marginal portion is 100 dust ~ 500 dusts, so as the removal edge making up subsequent CMP process fast, remove in the middle of slow effect.Further, the effect that removal edge dielectric layer is fast, removal middle dielectric layer is slow of subsequent CMP process can be made up by the pre-thickness (Pre-Thickness) reducing described first medium layer 12.Owing to will carry out CMP to described first medium layer 12 in subsequent step, the thickness of the described first medium layer 12 before CMP is carried out is pre-thickness.Inventor finds, due to the reduction of pre-thickness, need the thickness of the described first medium layer 12 removed in a cmp process also to reduce, therefore, after subsequent CMP process, the edge of described dielectric layer 12 and the thickness difference of core also can reduce thereupon.As an embodiment, described pre-thickness is no more than 10K dust.
With reference to figure 2 and Fig. 4, perform step S3, chemico-mechanical polishing is carried out to described first medium layer 12.
One skilled in the art will appreciate that the grinding head of the chemical-mechanical polisher that this area is commonly used comprises: wafer is pressed in the barrier film (Membrane) on abrasive disk, contact barrier film manages (InnerTube) and by securing for crystal round fringes maintaining part clasp (RetainerRing) to provide in the pressure fluids such as air.Therefore, grinding head comprises described wafer applied pressure: barrier film pressure (MembranePressure), inner tube pressure (InnerTubePressure) and maintenance pressure (RetainingPressure).Wafer to be pressed on grinding pad and to drive wafer to rotate by grinding head, and grinding pad is attached on abrasive disk and rotation in polished dribbling.
Inventor finds through research, and the basic reason that traditional CMP can make crystal circle center's part and edge form thickness difference is: in the polishing mechanical that this area is conventional, and the pressure of grinding head to crystal circle center's part is less than the pressure of edge; When grinding, although wafer each several part rotates with identical angular speed, the linear velocity of crystal circle center's part is less than the linear velocity of marginal portion, different from the relative speed difference of grinding pad.Therefore, by regulating grinding head to the velocity of rotation of the pressure of wafer and grinding head, abrasive disk, the thickness difference reduction at crystal circle center's part and edge after CMP can be made.
In the present embodiment, when carrying out described CMP, the scope of barrier film pressure is 2 pounds/square inch ~ 3 pounds/square inch, the scope of inner tube pressure is 3 pounds/square inch ~ 4 pounds/square inch, the scope of maintaining part pressure is 3 pounds/square inch ~ 4 pounds/square inch, the scope of lap speed is 90 revs/min ~ 140 revs/min, and the scope of grinding head rotating speed is 90 revs/min ~ 140 revs/min.
Through optimizing the glossing of CMP, the speed difference to the core of wafer and the grinding of marginal portion in flatening process can be reduced further, forming first medium layer 12 '.
Referring to figs. 2 and 5, perform step S4, the first medium layer 12 ' after described CMP is upper forms second dielectric layer 13.
As shown in Figure 4, described CMP can cause scratches (MicroScratch, not shown) on the surface of described first medium layer 12 '.In order to improve the surface of the first medium layer 12 ' after CMP, the surface of usual first medium layer 12 ' after the cmp process forms second dielectric layer 13 to cover described scratches, the material of described second dielectric layer can be identical with first medium layer 12, can be such as silica, silicon nitride, silicon oxynitride or its combination in any.Alternatively, the scope of the thickness of described second dielectric layer is 800 dusts ~ 2K dust.
Further, the edge of described second dielectric layer 13 is thick, centre portion thinner, namely has the profile similar with described first medium layer 12, so both can cover described scratches, can reduce again the thickness difference of the final dielectric layer formed.
Again further, the thickness difference of the margin and center part of described second dielectric layer 13 equals at the described core of first medium layer 12 ' carried out after described chemico-mechanical polishing and the thickness difference of marginal portion.
In the present embodiment, when forming described second dielectric layer 13, by adjustment in settling chamber, the size at the interval (spacer) between described wafer and air inlet (showerhead), centre portion thinner can be formed, the described second dielectric layer 13 that edge is thick.Alternatively, the distance range of described wafer and described air inlet is 180 mil ~ 220 mils.
If described second dielectric layer 13 is identical with described first medium layer material, similar method can be adopted to form second dielectric layer 13 on first medium layer 12 ' surface.
Particularly, pecvd process can be adopted to form described second dielectric layer 13, when described second dielectric layer 13 is silica, the predecessor of the described second dielectric layer 13 of formation comprises TEOS or SiH
4deng.As employing predecessor TEOS or SiH
4time, concrete technological parameter is: the scope of radio-frequency power is 200 watts ~ 1000 watts, and the scope of pressure is that 5 holder ~ 10 are held in the palm, and the scope of temperature is 350 degrees Celsius ~ 450 degrees Celsius.
Again particularly, when predecessor adopts TEOS, the scope of gas flow be 200 standard milliliters/minute ~ 800 standard milliliters/minute.
When predecessor adopts SiH
4time, the scope of gas flow is 1000 milli gram/minute ~ 2000 milli gram/minute.
Through above-mentioned technique, crystal circle center's part of the second dielectric layer 13 of formation is 100 dust ~ 500 dusts with the thickness difference scope of marginal portion.
To sum up, embodiments of the invention have the following advantages:
First, by forming centre portion thinner, first medium layer that edge is thick, CMP (Chemical Mechanical Polishing) process is carried out to it, because the grinding rate of crystal round fringes is higher than the grinding rate of core, therefore, it is possible to the thickness difference of the crystal circle center's part reduced because chemico-mechanical polishing causes and marginal portion.
Further, by covering on first medium layer, edge is thick, the second dielectric layer of centre portion thinner, can reduce the thickness difference at crystal circle center's part and the edge caused because of chemico-mechanical polishing further, thus obtain smooth dielectric layer.
Further, by reducing the pre-thickness of the first medium layer formed, reduce the thickness needing to be polished, thus reduce the thickness offset because crystal circle center partly brings with the grinding rate difference at edge.
Further, by optimizing CMP (Chemical Mechanical Polishing) process, reduce crystal circle center's part and the grinding rate difference at edge.
By the dielectric layer that the embodiment of the present invention is formed, it is effectively reduced in the difference in thickness at crystal circle center's part and edge, and the rate of finished products being formed at the resulting devices of crystal round fringes is effectively improved.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; the Method and Technology content of above-mentioned announcement can be utilized to make possible variation and amendment to technical solution of the present invention; therefore; every content not departing from technical solution of the present invention; the any simple modification done above embodiment according to technical spirit of the present invention, equivalent variations and modification, all belong to the protection range of technical solution of the present invention.
Claims (10)
1. form a method for flat dielectric layer, comprising:
Wafer is provided;
Described wafer is formed first medium layer, and the thickness at the edge of described first medium layer is greater than the thickness of core;
Chemico-mechanical polishing is carried out to described first medium layer;
Described first medium layer forms second dielectric layer, and the thickness at the edge of described second dielectric layer is greater than the thickness of core; The thickness difference of the margin and center part of described second dielectric layer equals at the described core of first medium layer carried out after described chemico-mechanical polishing and the thickness difference of marginal portion.
2. the method forming flat dielectric layer as claimed in claim 1, is characterized in that: described first medium layer and second dielectric layer are silica.
3. the method forming flat dielectric layer as claimed in claim 2, is characterized in that: when forming described first medium layer and/or described second dielectric layer, the distance of described wafer and air inlet is 180 mil ~ 220 mils.
4. the method forming flat dielectric layer as claimed in claim 3, is characterized in that: adopt PECVD device to form described first medium layer, predecessor comprises SiH
4, the scope of radio-frequency power is 200 watts ~ 1000 watts, and the scope of pressure is that 5 holder ~ 10 are held in the palm, and the scope of temperature is 350 degrees Celsius ~ 450 degrees Celsius, and the scope of gas flow is 1000 milli gram/minute ~ 2000 milli gram/minute.
5. the method forming flat dielectric layer as claimed in claim 3, it is characterized in that: adopt PECVD to form described first medium layer, predecessor comprises TEOS, the scope of radio-frequency power is 200 watts ~ 1000 watts, the scope of pressure is that 5 holder ~ 10 are held in the palm, the scope of temperature is 350 degrees Celsius ~ 450 degrees Celsius, the scope of gas flow be 200 standard milliliters/minute ~ 800 standard milliliters/minute.
6. the method forming flat dielectric layer as claimed in claim 1, is characterized in that: the pre-thickness of described first medium layer is no more than 10K dust.
7. the method forming flat dielectric layer as claimed in claim 1, is characterized in that: the scope of the thickness of described second dielectric layer is 800 dusts ~ 2K dust.
8. the method forming flat dielectric layer as claimed in claim 3, is characterized in that: adopt PECVD device to form described second dielectric layer, predecessor comprises SiH
4, the scope of radio-frequency power is 200 watts ~ 1000 watts, and the scope of pressure is that 5 holder ~ 10 are held in the palm, and the scope of temperature is 350 degrees Celsius ~ 450 degrees Celsius, and the scope of gas flow is 1000 milli gram/minute ~ 2000 milli gram/minute.
9. the method forming flat dielectric layer as claimed in claim 3, it is characterized in that: adopt PECVD to form described second dielectric layer, predecessor comprises TEOS, the scope of radio-frequency power is 200 watts ~ 1000 watts, the scope of pressure is that 5 holder ~ 10 are held in the palm, the scope of temperature is 350 degrees Celsius ~ 450 degrees Celsius, the scope of gas flow be 200 standard milliliters/minute ~ 800 standard milliliters/minute.
10. the method forming flat dielectric layer as claimed in claim 1, it is characterized in that: when carrying out described chemico-mechanical polishing, the scope of barrier film pressure is 2 pounds/square inch ~ 3 pounds/square inch, the scope of inner tube pressure is 3 pounds/square inch ~ 4 pounds/square inch, the scope keeping pressure is 3 pounds/square inch ~ 4 pounds/square inch, the scope of lap speed is 90 revs/min ~ 140 revs/min, and the scope of grinding head rotating speed is 90 revs/min ~ 140 revs/min.
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| CN104900512A (en) * | 2014-03-04 | 2015-09-09 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and semiconductor structure forming method |
| CN104392921B (en) * | 2014-11-25 | 2018-10-16 | 上海华虹宏力半导体制造有限公司 | The device and method of the uniformity after dielectric layer is milled between a kind of raising plain conductor |
| CN106558503B (en) * | 2015-09-24 | 2019-03-29 | 中芯国际集成电路制造(上海)有限公司 | Wafer bonding method |
| CN107398825B (en) * | 2017-08-28 | 2018-10-19 | 睿力集成电路有限公司 | The surface flat method of interlayer dielectric layer and the semiconductor structure based on it |
| CN108122751A (en) * | 2017-11-30 | 2018-06-05 | 上海华虹宏力半导体制造有限公司 | Chemical and mechanical grinding method |
| CN112366134B (en) * | 2021-01-15 | 2021-05-25 | 晶芯成(北京)科技有限公司 | Chemical mechanical polishing method |
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| TW569377B (en) * | 2002-03-20 | 2004-01-01 | Taiwan Semiconductor Mfg | Improvement method for thickness uniformity of super-thin nitridation gate dielectric |
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| CN102074479A (en) * | 2009-11-24 | 2011-05-25 | 中国科学院微电子研究所 | Semiconductor device and method for manufacturing the same |
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| US6627510B1 (en) * | 2002-03-29 | 2003-09-30 | Sharp Laboratories Of America, Inc. | Method of making self-aligned shallow trench isolation |
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| TW569377B (en) * | 2002-03-20 | 2004-01-01 | Taiwan Semiconductor Mfg | Improvement method for thickness uniformity of super-thin nitridation gate dielectric |
| CN101599454A (en) * | 2008-06-05 | 2009-12-09 | 联华电子股份有限公司 | Semiconductor element isolating structure and forming method thereof |
| CN102074479A (en) * | 2009-11-24 | 2011-05-25 | 中国科学院微电子研究所 | Semiconductor device and method for manufacturing the same |
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