CN102332408B - Chip scale package and production method thereof - Google Patents

Chip scale package and production method thereof Download PDF

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Publication number
CN102332408B
CN102332408B CN201010229640.1A CN201010229640A CN102332408B CN 102332408 B CN102332408 B CN 102332408B CN 201010229640 A CN201010229640 A CN 201010229640A CN 102332408 B CN102332408 B CN 102332408B
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chip
layer
coating layer
making
acting surface
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CN102332408A (en
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张江城
柯俊吉
黄建屏
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The invention discloses a chip scale package and a production method thereof. A protective layer is arranged on an acting surface of a chip, a non-acting surface of the chip is fixed on a rigid carrier, a package mold pressing process is performed and the protective layer is removed, and then a wire rearrangement technology is performed; therefore, the problems, such as adhesive film softening, package colloid overflow or warpage, chip displacement and pollution, and even waste product generation due to bad contact between a circuit layer and a chip solder pad in a subsequent wire rearrangement technology, caused by directly adhering the acting surface of the chip on the adhesive film in the prior art can be avoided; furthermore, the carrier can be repeatedly used in the production technology so that the production cost is saved.

Description

Chip size package and method for making thereof
Technical field
The present invention relates to a kind of semiconductor package part and method for making thereof, particularly relate to a kind of chip size package and method for making thereof.
Background technology
Along with the evolution of semiconductor technology, semiconductor product has developed different encapsulating products kenel, and be the compact of pursuit semiconductor package part, thus a kind of chip size package (chip scale package is developed, CSP), it is characterized in that this kind of chip size package only has the size equal or bigger with chip size.
United States Patent (USP) the 5th, 892,179,6,103,552,6,287,893,6,350,668 and 6,433, No. 427 patent discloses a kind of traditional CSP structure, be directly formed to increase layer and without the need to using as the chip bearing member such as substrate or lead frame on chip, and utilize the weld pad rerouted on (redistribution layer, RDL) technology reprovision chip to institute's wish position.
But the shortcoming of above-mentioned CSP structure is that the enforcement of the technology of rerouting uses or the conductive trace be laid on chip is often limited to the size of chip or the size of its acting surface, especially when chip integrated level promote and chip size increasingly reduce when, chip even cannot provide enough surface with settles the soldered ball of greater number come with the external world be electrically connected.
In view of this, United States Patent (USP) the 6th, 271, No. 469 patents disclose the method for making of a kind of crystal wafer chip dimension encapsulation part WLCSP (Wafer Level CSP), be on chip, form the packaging part increasing layer, the surf zone of comparatively abundance can be provided to carry more input/output terminal or soldered ball.
As shown in Figure 1A, prepare a glued membrane 11, and be pasted on this glued membrane 11 by multiple chip 12 with acting surface 121, this glued membrane 11 is such as thermoinduction glued membrane; As shown in Figure 1B, carry out Encapsulation Moulds compression technology, utilize the packing colloid 13 just like epoxy resin to envelope non-active face 122 and the side of chip 12, then heating removes this glued membrane 11, to expose outside this chip acting surface 121; As shown in Figure 1 C, then (RDL) technology that reroutes is utilized, lay a dielectric layer 14 on the acting surface 121 of chip and the surface of packing colloid 13, and offer multiple opening running through dielectric layer 14 with the weld pad 120 on exposed chip, then on this dielectric layer 14, line layer 15 is formed, and make line layer 15 be electrically connected to weld pad 120, then lay on line layer 15 refuse layer 16 and line layer precalculated position implanting soldered ball 17, carry out cutting operation afterwards.
By aforementioned manufacturing process, the surface because of the packing colloid of coating chip can provide the surf zone large compared with chip acting surface and more soldered ball can be settled effectively to reach the electric connection with the external world.
But, the shortcoming of above-mentioned manufacturing process is chip to be pasted on mode fixing on glued membrane with acting surface, often there is telescoping problem because glued membrane is heated in process, the sticky chip position be placed on glued membrane is caused to offset, even cause chip displacement when encapsulating mold pressing because glued membrane is subject to thermal softening, so cause follow-up when rerouting technique, line layer cannot be connected to chip pad causes electrically bad.Moreover, in this manufacturing process use glued membrane for expendable material, cause the increase of manufacturing cost.
In addition, refer to Fig. 2, when aforementioned encapsulation mold pressing, because glued membrane 11 heat is softened, easily there is glue 130 to the chip acting surface 121 that overflows in packing colloid 13, even pollute weld pad 120, cause line layer and the chip pad loose contact of the follow-up technique that reroutes, and cause waste product problem.
Moreover, refer to Fig. 3 A, aforementioned encapsulation mould pressing process supports multiple chip 12 by means of only glued membrane 11, easily there is serious warpage (warpage) 110 problem in this glued membrane 11 and packing colloid 13, especially when the very thin thickness of packing colloid 13, warpage issues is even more serious, thus cause follow-up reroute technique time, chip has uneven thickness problem during dielectric layer; So namely additionally must reoffer a hard carrier 18 (as shown in Figure 3 B), flatten so that packing colloid 13 is fixed on this hard carrier 18 by a viscose glue 19; So not only cause manufacturing process complicated, and increase many manufacturing costs, simultaneously complete reroute technique and remove this carrier time, easily occur in adhesive residue 190 problem (as shown in Figure 3 C) packing colloid having and is previously fixed on carrier.The disclosure of other related art as United States Patent (USP) the 6th, 498,387,6,586,822,7,019,406 and 7,238, No. 602.
Therefore, how to provide a kind of chip size package and method for making, thus the electric connection quality between line layer and weld pad can be guaranteed, and the reliability of improving product, reducing manufacturing cost, is an important technical problem in fact.
Summary of the invention
Because the shortcoming of above-mentioned prior art, the object of this invention is to provide a kind of chip size package and method for making, to guarantee the electric connection quality between line layer and weld pad, and the reliability of improving product, reduce manufacturing cost.
For achieving the above object, the invention provides a kind of method for making of chip size package, comprise: chip and a carrier that multiple tool relativity face and non-active face are provided, this chip acting surface is provided with multiple weld pad, this chip acting surface is coated with protective layer and is provided with the first coating layer in this carrier surface, so that this chip is fixed on this first coating layer by its non-active face; With the second coating layer this chip coated and the protective layer exposed outside on this chip acting surface; Remove this protective layer to expose outside this chip acting surface; This chip acting surface and the second coating layer arrange dielectric layer, and makes this dielectric layer form opening to expose outside this weld pad; This dielectric layer forms line layer, and makes this line layer be electrically connected to this weld pad; And arrange on this dielectric layer and line layer and refuse layer, and make this refuse layer to form multiple opening to plant soldered ball.Follow-up i.e. this carrier removable, and carry out cutting operation to form multiple crystal wafer chip dimension encapsulation part (WLCSP).
For thinning packaging part and lifting chip cooling effect also this first coating layer removable.Separately can utilize the technology of rerouting on this line layer, form circuit and increase layer (build-up) structure.In the method for making of chip size package of the present invention, adhesive force because of this second coating layer and the first coating layer is greater than the adhesive force of the first coating layer and carrier, and this carrier can be removed easily in subsequent manufacturing procedures, manufacturing process efficiency is provided thus, reuse this carrier, and then save manufacturing cost.
By aforementioned method for making, the present invention also provides a kind of chip size package, comprising: chip, and this chip has relative acting surface and non-active face, and is provided with multiple weld pad at this chip acting surface; Second coating layer, is coated on this chip circumference, and the height of this second coating layer is greater than the height of this chip; Dielectric layer, is located on this chip acting surface and the second coating layer, and the multiple opening of this dielectric layer tool is to expose this weld pad; And line layer, to be located on this dielectric layer and to be electrically connected to this weld pad.
This packaging part also includes: refuse layer, is located on this dielectric layer and line layer, and this is refused layer and has multiple opening to expose outside line layer predetermined portions; And soldered ball, be located on this line layer predetermined portions.
In addition, this packaging part also can establish the first coating layer on this chip non-active face and the second coating layer.
Therefore, chip size package of the present invention and method for making mainly establish a protective layer on chip acting surface, and make chip be fixed on hard carrier with non-active face, then carry out Encapsulation Moulds compression technology and remove this protective layer, then carry out rerouting technique again, use avoid existing by chip acting surface directly sticky being placed on glued membrane there is glued membrane by thermal softening, packing colloid overflows glue and chip offset and pollution problem, even cause line layer and the chip pad loose contact of the follow-up technique that reroutes, cause waste product problem, and in the present invention this carrier in a manufacturing process because the adhesive force of the second coating layer and the first coating layer is greater than the adhesive force of the first coating layer and carrier, and can easy removal and reusing, to save manufacturing cost, the present invention simultaneously does not need to use glued membrane, therefore can avoid using glued membrane in existing manufacturing process and warpage issues occurring, and need additionally to provide carrier to be caused manufacturing process complicated by solving this warpage issues, cost increases and packing colloid has the problems such as cull.
Accompanying drawing explanation
Figure 1A to Fig. 1 C is US Patent No. 6,271, and the method for making schematic diagram of the crystal wafer chip dimension encapsulation part disclosed in 469;
Fig. 2 is US Patent No. 6,271, and there is the schematic diagram of excessive glue problem in the crystal wafer chip dimension encapsulation part disclosed in 469;
Fig. 3 A to Fig. 3 C is US Patent No. 6,271, the crystal wafer chip dimension encapsulation part generation packing colloid warpage disclosed in 469, set up the schematic diagram of carrier and packing colloid surface cull problem;
Fig. 4 A to Fig. 4 H is chip size package of the present invention and method for making first embodiment schematic diagram thereof;
Fig. 5 is chip size package of the present invention and method for making second embodiment schematic diagram thereof;
Fig. 6 is chip size package of the present invention and method for making the 3rd embodiment schematic diagram thereof;
Fig. 7 A to Fig. 7 D is chip size package of the present invention and method for making the 4th embodiment schematic diagram thereof.
Main element symbol description:
11 glued membrane 12 chips
13 packing colloid 14 dielectric layers
15 line layers 16 refuse layer
17 soldered ball 18 carriers
19 viscose glue 21 protective layers
22 chip 22A wafers
23 carrier 24 viscose glues
25 second coating layer 26 dielectric layers
26a second dielectric layer 27 line layer
27a second line layer 28 refuses layer
29 soldered ball 31 protective layers
32 chip 33 carriers
34 viscose glue 35 second coating layers
36 dielectric layer 37 line layers
38 refuse layer 39 soldered ball
110 warpage 120 weld pads
121 acting surface 122 non-active faces
130 excessive glue 190 adhesive residue
220 weld pad 221 acting surfaces
222 non-active face 230 first coating layers
330 first coating layer 333 any enhanced protection layers
Embodiment
Below by way of particular specific embodiment, embodiments of the present invention are described, those skilled in the art can understand other advantages of the present invention and effect easily by content disclosed in the present specification.
Referring to Fig. 4 A to Fig. 4 H, is the schematic diagram of chip size package of the present invention and method for making first embodiment thereof.
As shown in fig. 4 a and fig. 4b; the wafer 22A of the multiple chip 22 of one tool is provided; this wafer 22A and chip 22 have relative acting surface 221 and non-active face 222; and this chip acting surface 221 is provided with multiple weld pad 220; and on this wafer acting surface 221, lay the protective layer 21 of thick about 3 to 20 microns; then wafer 22A cutting is carried out, to form the chip 22 that multiple acting surface 221 is provided with protective layer 21.
As shown in Figure 4 C; one hard carrier 23 is separately provided; and on carrier 23, be coated with the first coating layer 230; thus the multiple chips 22 aforementioned acting surface 221 being provided with protective layer 21 are placed on this first coating layer 230 so that its non-active 222 is sticky by viscose glue 24, and it is fixing to carry out toasting (cure).This first coating layer 230 is such as the epoxy resin of ink.
As shown in Figure 4 D, this chip 22 coated of the second coating layer 25 as epoxy resin encapsulating material is made and the protective layer 21 exposed outside on this chip acting surface 221 with such as press moulding mode.This second coating layer 25 is such as the encapsulating material of epoxy resin, wherein the Material selec-tion of this carrier 23, first coating layer 230 and the second coating layer 25 need make the adhesive force of this second coating layer 25 and the first coating layer 230 be greater than the adhesive force of the first coating layer 230 and carrier 23, follow-uply removes this carrier 23 to facilitate.
As shown in Figure 4 E, exposed chip acting surface 221 beyond this protective layer is removed in the mode of such as chemical agent.So namely the height of this second coating layer 25 is greater than the height of this chip acting surface 221.
As illustrated in figure 4f, chip acting surface 221 and the second coating layer 25 arrange dielectric layer 26, and utilize such as gold-tinted (photo-lithography) technique or laser technology, make this dielectric layer be formed with multiple opening to expose outside this weld pad 220.This dielectric layer 26 is the Seed Layer (seed layer) with adhering to for follow-up line layer on it.
Then, utilize (RDL) technology that reroutes to form line layer 27 on this dielectric layer 26, and make this line layer 27 be electrically connected to this weld pad 220.
As shown in Figure 4 G, this dielectric layer 26 and line layer 27 are arranged and refuses layer 28, and make this refuse layer 28 to form multiple opening to expose outside this line layer 27 predetermined portions, thus for implanting soldered ball 29 in this line layer predetermined portions.
As shown at figure 4h, afterwards because the adhesive force of this second coating layer 25 and the first coating layer 230 is greater than the adhesive force of the first coating layer 230 and carrier 23, get final product this carrier 23 of easy removal, then carry out cutting operation, to form multiple crystal wafer chip dimension encapsulation part (WLCSP).
By aforementioned method for making, the present invention also provides a kind of chip size package, comprising: chip 22, and this chip 22 has relative acting surface 221 and non-active face 222, and is provided with multiple weld pad 220 at this chip acting surface 221; Second coating layer 25, be coated on around this chip 22, the height of this second coating layer 25 is greater than the height of this chip 22; Dielectric layer 26, is located on this chip 22 acting surface and the second coating layer 25, and this dielectric layer 26 has multiple opening to expose this weld pad 220; Line layer 27, to be located on this dielectric layer 26 and to be electrically connected to this weld pad 220; Refuse layer 28, be located on this dielectric layer 26 and line layer 27, this is refused layer 28 and has multiple opening to expose outside line layer 27 predetermined portions; Soldered ball 29, is located on this line layer 27 predetermined portions.In addition, this packaging part establishes the first coating layer 230 on this chip non-active face 222 and the second coating layer 25.
Therefore, chip size package of the present invention and method for making mainly establish a protective layer on chip acting surface, and make chip be fixed on hard carrier with non-active face, then carry out Encapsulation Moulds compression technology and remove this protective layer, then carry out rerouting technique again, use avoid prior art by chip acting surface directly sticky being placed on glued membrane there is glued membrane by thermal softening, packing colloid overflows glue and chip offset and pollution problem, even cause line layer and the chip pad loose contact of the follow-up technique that reroutes, cause waste product problem, and in the present invention this carrier in a manufacturing process because the adhesive force of the second coating layer and the first coating layer is greater than the adhesive force of the first coating layer and carrier, and can easy removal and reusing, to save manufacturing cost, the present invention simultaneously does not need to use glued membrane, therefore can avoid using glued membrane in existing manufacturing process and warpage issues occurring, and need additionally to provide carrier to be caused manufacturing process complicated by solving this warpage issues, cost increases and packing colloid has the problems such as cull.
Referring to Fig. 5, is the generalized section of display chip size package of the present invention and method for making second embodiment thereof.As shown in the figure, it is roughly the same that this chip size package and previous embodiment provide, its difference to be in follow-up for thinning packaging part also removable first coating layer, contributes to dissipation chip 32 simultaneously and runs the heat that produces to extraneous, the radiating efficiency of enhancement packaging part.
Refer to Fig. 6 again, for showing the generalized section of chip size package of the present invention and method for making the 3rd embodiment thereof.As shown in the figure, it is roughly the same that this chip size package and previous embodiment provide, its difference is in the technology that reroutes can be utilized to continue to form layer reinforced structure on previous formed dielectric layer and line layer, such as on previous formed dielectric layer 26 and line layer 27, form the second dielectric layer 26a and the second line layer 27a, and make this second line layer 27a be electrically connected to this first line layer 27, then, lay on the second line layer 27a again and refuse layer 28, and offer and multiplely run through the opening refusing layer 28, to expose outside the predetermined portions of the second line layer 27a, then on the predetermined portions of the second line layer 27a, soldered ball 29 is planted, using the input/output terminal as packaging part, for being electrically connected with external device.The elasticity of route arrangement in packaging part so can be promoted by the increasing number of layers increased on chip.
Refer to Fig. 7 A to Fig. 7 D, for showing the generalized section of chip size package of the present invention and method for making the 4th embodiment thereof.As shown in the figure, it is roughly the same that the present embodiment and previous embodiment provide, and Main Differences can set up an any enhanced protection layer with protect IC on chip non-active face.
As shown in Figure 7 A, one hard carrier 33 is provided, and on carrier 33, be coated with the first coating layer 330, formed as epoxy resin encapsulating material (EMC with such as press moulding mode on this first coating layer 330 again, Epoxy Molding Compound) any enhanced protection layer 333, wherein the adhesive force of this any enhanced protection layer 333 and the first coating layer 330 is greater than the adhesive force of this first coating layer 330 and carrier 33.
As shown in Figure 7 B, the chip 32 acting surface being provided with protective layer 31 is placed on this any enhanced protection layer 333 so that its non-active face is sticky by viscose glue 34.
As seen in figure 7 c, this chip 32 coated of the second coating layer 35 as epoxy resin encapsulating material is made and the protective layer 31 exposed outside on this chip acting surface with such as press moulding mode; Then remove this protective layer 31 to expose outside this chip acting surface, then dielectric layer 36 is set on this chip acting surface and the second coating layer 35, and form line layer 37 on this dielectric layer 36.
Then arrange on this dielectric layer 36 and line layer 37 and refuse layer 38, and plant soldered ball 39.
As illustrated in fig. 7d, be this carrier 33 removable afterwards, and carry out cutting operation.
Namely the non-active face of this chip 32 like this is provided with an any enhanced protection layer 333, to provide chip better protection.
Above-described embodiment is only illustrative principle of the present invention and effect thereof, but not for limiting the present invention.Any those skilled in the art all without prejudice under spirit of the present invention and category, can carry out modifying to above-described embodiment and change.Therefore, the scope of the present invention, should with the scope of claims for foundation.

Claims (12)

1. a method for making for chip size package, is characterized in that, comprising:
There is provided chip and a carrier in multiple tool relativity face and non-active face, this chip acting surface is provided with multiple weld pad; This chip acting surface is coated with protective layer; Be provided with the first coating layer in this carrier surface, and this first coating layer is formed with any enhanced protection layer by press moulding mode; Chip is fixed on this any enhanced protection layer by its non-active face;
Form the second coating layer on this any enhanced protection layer, with this second coating layer this chip coated and the protective layer exposed outside on this chip acting surface;
Remove this protective layer to expose outside this chip acting surface;
This chip acting surface and the second coating layer arrange dielectric layer, and makes this dielectric layer form opening to expose outside this weld pad; And
This dielectric layer forms line layer, and makes this line layer be electrically connected to this weld pad.
2. the method for making of chip size package according to claim 1, is characterized in that, also comprises: arrange on this dielectric layer and line layer and refuse layer, and make this refuse layer to form multiple opening to plant soldered ball.
3. the method for making of chip size package according to claim 2, is characterized in that, also comprises: remove this carrier, and carries out cutting operation.
4. the method for making of chip size package according to claim 1, is characterized in that, the adhesive force of this second coating layer and the first coating layer is greater than the adhesive force of the first coating layer and carrier.
5. the method for making of chip size package according to claim 1, is characterized in that, the height of this second coating layer is greater than the height of this chip.
6. the method for making of chip size package according to claim 3, is characterized in that, also comprises: remove this first coating layer.
7. the method for making of chip size package according to claim 1, is characterized in that, also comprises: on this dielectric layer and line layer, form layer reinforced structure with the technology of rerouting.
8. the method for making of chip size package according to claim 1; it is characterized in that; the manufacturing process of this chip and carrier comprises: the wafer providing the multiple chip of a tool; this wafer and chip have relative acting surface and non-active face; to lay protective layer on this wafer acting surface; then wafer cutting is carried out, to form the chip that multiple acting surface is provided with protective layer, to be fixed on the first coating layer of carrier by its non-active face by this chip.
9. the method for making of chip size package according to claim 1, is characterized in that, this any enhanced protection layer is epoxide resin material.
10. the method for making of chip size package according to claim 1, is characterized in that, the adhesive force of this any enhanced protection layer and the first coating layer is greater than the adhesive force of this first coating layer and carrier.
The method for making of 11. chip size package according to claim 1, is characterized in that, this second coating layer makes encapsulating material this chip coated by press moulding mode.
The method for making of 12. chip size package according to claim 1, is characterized in that, this first coating layer is the ink containing epoxy resin.
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