CN102332299A - SRAM (System Random Access Memory) unit - Google Patents
SRAM (System Random Access Memory) unit Download PDFInfo
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- CN102332299A CN102332299A CN201110213098A CN201110213098A CN102332299A CN 102332299 A CN102332299 A CN 102332299A CN 201110213098 A CN201110213098 A CN 201110213098A CN 201110213098 A CN201110213098 A CN 201110213098A CN 102332299 A CN102332299 A CN 102332299A
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Abstract
The embodiment of the invention provides an SRAM (System Random Access Memory) unit comprising a writing-in unit, a storage unit and a reading-out unit, wherein the writing-in unit is electrically connected with a writing line and a writing bit line and used for controlling the state of writing-in information of the SRAM unit; the storage unit is electrically connected with the writing-in unit, and used for reversing the writing-in information to form storage information and providing with a storage node for storing the storage information; and the reading-out unit is electrically connected with a reading word line, a reading bit line and the storage unit and used for reading out the storage information. According to the embodiment of the invention, the area of a chip occupied by the SRAM unit is reduced.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly sram cell.
Background technology
Along with the continuous development that with the electronic communication technology is the Modern high-tech industry of representative; World's IC industry gross output value is to surpass 30% speed development every year, and SRAM (SRAM) is widely used in numeral and the communicating circuit design as a kind of important memory device.SRAM is a kind of vitals in the logical circuit, and it is because to have power consumption little, reading speed advantages of higher and be widely used in the storage of data.
Prior art provides a kind of sram cell, please refer to the electrical block diagram of the sram cell of prior art shown in Figure 1.Comprise:
The first nmos pass transistor N1 and the 4th nmos pass transistor N4, grid connect and write word line WWL, and source electrode connects and writes bit line WBL, and drain electrode is as writing ingress;
The one CMOS transistor 101 and the 2nd CMOS transistor 102; A said CMOS transistor 101 comprises a PMOS transistor P1 and the 6th nmos pass transistor N6; Said the 2nd CMOS transistor 102 comprises the 2nd PMOS transistor P2 and the second nmos pass transistor N2; The grounded drain of said PMOS transistor P1 drain electrode and the 2nd PMOS crystal P2, the drain electrode (being the said write node) of the drain electrode of the source electrode of the drain electrode of said the 6th nmos pass transistor N6, a said PMOS transistor P1 and the source electrode of said the 2nd PMOS transistor P2, the second nmos pass transistor N2 and the said first nmos pass transistor N1 is electrically connected; The drain electrode (being the said write node) of the grid of the grid of a said PMOS transistor P1, the grid of the 6th nmos pass transistor N6, the 2nd PMOS transistor P2, the grid of the second nmos pass transistor N2 and the 4th nmos pass transistor N4 is electrically connected, and the source electrode of the source electrode of said the 6th nmos pass transistor N6 and the second nmos pass transistor N2 meets electronegative potential Vss;
The 3rd nmos pass transistor N3 and the 5th nmos pass transistor N5, the grid of said the 3rd nmos pass transistor N3 meets read operation word line RWL; The drain electrode of the 3rd nmos pass transistor N3 meets read operation bit line RBL, and the source electrode of the 3rd nmos pass transistor N3 connects the source electrode of the 5th nmos pass transistor N5, and the source electrode of the 5th nmos pass transistor N5 meets electronegative potential Vss.
, publication number can find more information in being the one Chinese patent application of CN 101425332A about existing 8T type sram cell.
Find that in reality owing to need to use 8 transistors, the chip area that makes existing sram cell take is bigger.
Summary of the invention
The problem that the embodiment of the invention solves has provided a kind of sram cell, the area of chip that the sram cell that reduces greatly takies.
For addressing the above problem, the embodiment of the invention provides a kind of sram cell, comprising:
Writing unit is electrically connected with write word line and write bit line, is used to control the state to this sram cell writing information;
Storage unit is electrically connected with the said write unit, is used for said write information oppositely, forms canned data, provides memory node that said canned data is preserved;
Sensing element is electrically connected with readout word line, sense bit line and said storage unit, is used to read said canned data.
Alternatively; Said reverse unit is a cmos cell, and said cmos cell is made up of second type of transistor and first kind transistor, and the drain electrode of said second type of transistor connects high potential signal; Said first kind transistor connects low-potential signal; The source electrode of said second type of transistor and first kind transistor drain are electrically connected, and form memory node, and said second type of transistor and the transistorized grid of the first kind are electrically connected with the said write unit.
Alternatively; The said write unit is for writing transistor; The transistorized grid of said write is electrically connected with said write word line, and the transistorized source electrode of said write is electrically connected with said write bit line, and the said write transistor drain is electrically connected with said second type of transistor and the transistorized grid of the first kind; Ingress is write in formation, and the conduction type of the transistorized charge carrier of said write is identical with the conduction type of the transistorized charge carrier of the said first kind.
Alternatively; Also comprise: current potential is kept transistor; Grid is electrically connected with said memory node, and drain electrode is electrically connected with noble potential, and source electrode is electrically connected with the said write node; Said current potential is kept the current potential that transistor is used for keeping said memory node and is kept stable, and the conduction type that said current potential is kept transistorized charge carrier is identical with the conduction type of the charge carrier of said second type of transistor.
Alternatively, the transistorized threshold voltage of said write is kept the little 0.05～0.2v of transistorized threshold voltage than said voltage.
Alternatively, said sensing element is for reading transistor, saidly reads transistorized grid and is electrically connected with readout word line, and drain electrode is electrically connected with sense bit line, and source electrode is electrically connected with said memory node.
Alternatively, said second type of transistor is the PMOS transistor, and said first kind transistor is a nmos pass transistor.
Compared with prior art, the embodiment of the invention has the following advantages:
The sram cell that the embodiment of the invention provides is made up of 5 transistors, and utilizes 5 transistorized sram cells of the embodiment of the invention can realize and existing 8T type sram cell identical functions, thus the area of chip that the sram cell that reduces takies;
Alternatively; The transistorized threshold voltage of said write is kept the little 0.05～0.2v of transistorized threshold voltage than said voltage; Thereby make when holding state; The transistorized leakage current of said write is kept transistorized threshold voltage greater than said voltage, helps improving the stability of the electronegative potential in the said write node.
Description of drawings
Fig. 1 is the electrical block diagram of the sram cell of prior art;
Fig. 2 is the electrical block diagram of the 5T type sram cell of one embodiment of the invention.
Embodiment
The area that existing sram cell needs 8 transistors therefore to take is bigger.In order under the situation of realization and 8T type identical function, to reduce the chip area that sram cell takies, the inventor proposes a kind of sram cell and comprises:
Writing unit is electrically connected with write word line and write bit line, is used to control the state to this sram cell writing information;
Storage unit is electrically connected with the said write unit, is used for said write information oppositely, forms canned data, provides memory node that said canned data is preserved;
Sensing element is electrically connected with readout word line, sense bit line and said storage unit, is used to read said canned data.
Below in conjunction with specific embodiment technical scheme of the present invention is at length explained.For technical scheme of the present invention is described better, please refer to the electrical block diagram of the sram cell of one embodiment of the present of invention shown in Figure 2.Said sram cell comprises:
Writing unit; As an embodiment; The said write unit is made up of a transistor, and the conduction type of this transistorized charge carrier is identical with the conduction type of the charge carrier of first kind transistor (said first kind transistor can be nmos pass transistor or PMOS transistor); In the present embodiment, the said write unit is made up of the first nmos pass transistor N1, and the grid of the said first nmos pass transistor N1 connects and writes word line WWL, and source electrode connects and writes bit line WBL, and drain electrode is as writing ingress;
Storage unit is electrically connected with the ingress of writing of said write unit, is used for the current potential of said write node reverse; Obtain canned data, and provide memory node that said canned data is preserved, said storage unit is made up of reverse unit; Said reverse unit is a cmos cell; As an embodiment, said cmos cell is made up of second type of transistor and first kind transistor, the conductivity type opposite of said second type of transistor and the transistorized charge carrier of the first kind; The drain electrode of said second type of transistor meets high potential signal Vdd; Said first kind transistor meets low-potential signal Vss; The source electrode of said second type of transistor and first kind transistor drain are electrically connected; And the formation memory node, said second type of transistor and the transistorized grid of the first kind are electrically connected with said write unit (i.e. the drain electrode of the first nmos pass transistor N1); As an embodiment, said second type of transistor is the PMOS transistor, and said first kind transistor is a nmos pass transistor; As shown in Figure 2; Said second type of transistor is the 2nd PMOS transistor P2, and said first kind transistor is the second nmos pass transistor N2, still with reference to figure 2; The drain electrode of said the 2nd PMOS transistor P2 meets noble potential Vdd; The source electrode of said the 2nd PMOS transistor P2 is electrically connected with the drain electrode of the second nmos pass transistor N2, and forms memory node, and the grid of said the 2nd PMOS transistor P2 and the grid N2 of second nmos pass transistor are electrically connected with the drain electrode (being the said write node) of the first nmos pass transistor N1;
As an embodiment, said storage unit also comprises: current potential is kept transistor, as an embodiment; It is second type of transistor that said current potential is kept transistor; In the present embodiment, it is a PMOS transistor P1 that said current potential is kept transistor, and the grid of a said PMOS transistor P1 is electrically connected with said memory node; Drain electrode is electrically connected with noble potential; Source electrode is electrically connected with the said write node, and the electronegative potential that a said PMOS transistor P1 is used for keeping said memory node keeps stable, and concrete principle describes follow-up;
Sensing element, as an embodiment, said sensing element is for reading transistor; The said conduction type of reading transistorized charge carrier is identical with the conduction type of the transistorized charge carrier of the said first kind; As an embodiment, the said transistor of reading is the 3rd nmos pass transistor N3, and the grid of said the 3rd nmos pass transistor N3 is electrically connected with readout word line; Drain electrode is electrically connected with sense bit line, and source electrode is electrically connected with said memory node.
Of the present inventionly write transistorized threshold voltage should to keep transistorized threshold voltage than said voltage little; For example the transistorized threshold voltage of said write can be kept the little 0.05～0.2v of transistorized threshold voltage than said voltage; Thereby make when holding state; The transistorized leakage current of said write is kept transistorized threshold voltage greater than said voltage, helps improving the stability of the electronegative potential in the said write node.In the present embodiment, the threshold voltage of the said first nmos pass transistor N1 is than the little 0.05～0.2v of voltage of a said PMOS transistor P1, thereby helps improving the stability of the electronegative potential of writing ingress.
Need to prove that in other embodiments of the invention, said first kind transistor can be the P transistor npn npn, said second type of transistor can be the N transistor npn npn.The sram cell that utilizes the embodiment of the invention to provide can be realized the sram cell identical functions with existing 8T type, but the embodiment of the invention only needs 5 transistors, so the embodiment of the invention has reduced transistorized number.
Principle of work in the face of above-mentioned sram cell describes down.
At first, when said sram cell was carried out write operation, the current potential of sense word line RWL was an electronegative potential, and the current potential of readout bit line RBL is a noble potential, and the 3rd nmos pass transistor N3 turn-offs; Write the current potential noble potential of word line WWL; Write the defeated content that will write of bit line WBL, the said current potential that will write can be noble potential or electronegative potential, is example to write bit line WBL input noble potential; The first nmos pass transistor N1 conducting; The drain electrode of the said first nmos pass transistor N1 (being the said write node) current potential is consistent with the current potential that writes bit line WBL, and in the present embodiment, the drain potential of the said first nmos pass transistor N1 is a noble potential;
Because the drain electrode of the said first nmos pass transistor N1 is electrically connected with the grid of said the 2nd PMOS transistor P2 and the grid of the second nmos pass transistor N2, therefore, said the 2nd PMOS transistor P2 turn-offs; The said second nmos pass transistor N2 conducting; Because the source ground of the said second nmos pass transistor N2, the drain electrode of the said second nmos pass transistor N2 (being memory node) is ground connection also, therefore; The drain potential of the second nmos pass transistor N2 is an electronegative potential, thereby current potential is an electronegative potential in the said memory node;
As another embodiment of the present invention, when said sram cell was carried out write operation, the current potential of sense word line RWL was an electronegative potential, and the current potential of readout bit line RBL is a noble potential, and the 3rd nmos pass transistor N3 turn-offs; The current potential that writes word line WWL is a noble potential; When the current potential of said write bit line WBL is electronegative potential; The current potential of the drain electrode of the said first nmos pass transistor N1 (promptly writing ingress) is an electronegative potential, and the said second nmos pass transistor N2 turn-offs, said the 2nd PMOS transistor P2 conducting; Because the drain electrode of said the 2nd PMOS transistor P2 meets noble potential Vdd, thereby the current potential of the source electrode of said the 2nd PMOS transistor P2 (being memory node) is a noble potential.
When the current potential in the memory node is electronegative potential; A said PMOS transistor P1 is conducting, and the drain electrode of a PMOS transistor P1 meets noble potential Vdd, therefore; The source electrode of a said PMOS transistor P1 (promptly writing ingress) current potential is a noble potential; Thereby a said PMOS transistor P1 makes the current potential write ingress be maintained at noble potential, and the noble potential of having avoided writing ingress can't be kept, the problem that the electronegative potential that finally causes storing in the memory node can't the position.
When said sram cell was carried out read operation, the current potential of said write word line WWL was an electronegative potential, and the current potential of said write bit line WBL is an electronegative potential, and the therefore said first nmos pass transistor N1 turn-offs; The current potential of said readout word line RWL is a noble potential; The current potential of said sense bit line RBL is a noble potential; Said the 3rd nmos pass transistor N3 conducting; Electric current between source electrode through testing said the 3rd nmos pass transistor N3 and the drain electrode can obtain the current potential of the source electrode (being said memory node) that the 3rd nmos pass transistor N3 promptly can obtain the 3rd nmos pass transistor N3; Concrete principle is: if the current potential of the source electrode of said the 3rd nmos pass transistor N3 is a noble potential, then because the current potential between the source electrode of said the 3rd nmos pass transistor N3 and the drain electrode is identical, so electric current between the two is zero; If the current potential of the source electrode of said the 3rd nmos pass transistor N3 is an electronegative potential, then, therefore can form electric current between the two owing to have potential difference (PD) between the source electrode of said the 3rd nmos pass transistor N3 and the drain electrode.
When the said sram cell of needs is in holding state; Said write word line WWL, the current potential that writes bit line bit line WBL, sense word line RWL are electronegative potential; The current potential of said readout bit line RBL is a noble potential, and at this moment, said first nmos pass transistor N1 and the 3rd nmos pass transistor N3 are off state; When holding state; Because the threshold voltage of the first nmos pass transistor N1 is less than the threshold voltage of a PMOS transistor P1; Both differences are 0.05～0.2v; Thereby make the leakage current of the said first nmos pass transistor N1 greater than the leakage current of a said PMOS transistor P1, thereby help keeping the stability of the electronegative potential of writing ingress, thereby help improving the stability of the noble potential of memory node.
To sum up; The sram cell that the embodiment of the invention provides is made up of 5 transistors; And said sram cell can realize and existing 8T type sram cell identical functions that still with 8T type SRAM transistor, sram cell of the present invention has significantly reduced the area of chip that sram cell takies;
The transistorized threshold voltage of said write is kept the little 0.05～0.2v of transistorized threshold voltage than said voltage; Thereby make when holding state; The transistorized leakage current of said write is kept transistorized threshold voltage greater than said voltage, helps improving the stability of the electronegative potential in the said write node.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art are not breaking away from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (7)
1. a sram cell is characterized in that, comprising:
Writing unit is electrically connected with write word line and write bit line, is used to control the state to this sram cell writing information;
Storage unit is electrically connected with the said write unit, is used for said write information oppositely, forms canned data, provides memory node that said canned data is preserved;
Sensing element is electrically connected with readout word line, sense bit line and said storage unit, is used to read said canned data.
2. sram cell as claimed in claim 1; It is characterized in that; Said reverse unit is a cmos cell, and said cmos cell is made up of second type of transistor and first kind transistor, and the drain electrode of said second type of transistor connects high potential signal; Said first kind transistor connects low-potential signal; The source electrode of said second type of transistor and first kind transistor drain are electrically connected, and form memory node, and said second type of transistor and the transistorized grid of the first kind are electrically connected with the said write unit.
3. sram cell as claimed in claim 2; It is characterized in that; The said write unit is for writing transistor; The transistorized grid of said write is electrically connected with said write word line, and the transistorized source electrode of said write is electrically connected with said write bit line, and the said write transistor drain is electrically connected with said second type of transistor and the transistorized grid of the first kind; Ingress is write in formation, and the conduction type of the transistorized charge carrier of said write is identical with the conduction type of the transistorized charge carrier of the said first kind.
4. sram cell as claimed in claim 3; It is characterized in that, also comprise: current potential is kept transistor, and grid is electrically connected with said memory node; Drain electrode is electrically connected with noble potential; Source electrode is electrically connected with the said write node, and said current potential is kept the current potential that transistor is used for keeping said memory node and kept stable, and the conduction type that said current potential is kept transistorized charge carrier is identical with the conduction type of the charge carrier of said second type of transistor.
5. sram cell as claimed in claim 4 is characterized in that, the transistorized threshold voltage of said write is kept the little 0.05～0.2v of transistorized threshold voltage than said voltage.
6. sram cell as claimed in claim 2 is characterized in that, said sensing element is for reading transistor, saidly reads transistorized grid and is electrically connected with readout word line, and drain electrode is electrically connected with sense bit line, and source electrode is electrically connected with said memory node.
7. sram cell as claimed in claim 2 is characterized in that, said second type of transistor is the PMOS transistor, and said first kind transistor is a nmos pass transistor.
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| CN201110213098A CN102332299A (en) | 2011-07-28 | 2011-07-28 | SRAM (System Random Access Memory) unit |
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| CN201110213098A CN102332299A (en) | 2011-07-28 | 2011-07-28 | SRAM (System Random Access Memory) unit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015158305A1 (en) * | 2014-04-17 | 2015-10-22 | Tsinghua University | Cell structure of random access memory, random access memory and operation methods |
| CN103956182B (en) * | 2014-04-17 | 2017-02-15 | 清华大学 | Random access storage device unit structure, random access storage device and operation method of random access storage device |
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| US5670803A (en) * | 1995-02-08 | 1997-09-23 | International Business Machines Corporation | Three-dimensional SRAM trench structure and fabrication method therefor |
| US20070201273A1 (en) * | 2006-02-27 | 2007-08-30 | International Business Machines Corporation | Back-gate controlled asymmetrical memory cell and memory using the cell |
| CN101840728A (en) * | 2010-05-28 | 2010-09-22 | 上海宏力半导体制造有限公司 | Dual-end static random access memory (SRMA) unit |
| CN101877243A (en) * | 2010-04-22 | 2010-11-03 | 上海宏力半导体制造有限公司 | Static random access memory |
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2011
- 2011-07-28 CN CN201110213098A patent/CN102332299A/en active Pending
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US5670803A (en) * | 1995-02-08 | 1997-09-23 | International Business Machines Corporation | Three-dimensional SRAM trench structure and fabrication method therefor |
| US20070201273A1 (en) * | 2006-02-27 | 2007-08-30 | International Business Machines Corporation | Back-gate controlled asymmetrical memory cell and memory using the cell |
| CN101877243A (en) * | 2010-04-22 | 2010-11-03 | 上海宏力半导体制造有限公司 | Static random access memory |
| CN101840728A (en) * | 2010-05-28 | 2010-09-22 | 上海宏力半导体制造有限公司 | Dual-end static random access memory (SRMA) unit |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2015158305A1 (en) * | 2014-04-17 | 2015-10-22 | Tsinghua University | Cell structure of random access memory, random access memory and operation methods |
| CN103956182B (en) * | 2014-04-17 | 2017-02-15 | 清华大学 | Random access storage device unit structure, random access storage device and operation method of random access storage device |
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