CN102323532B - Multichip stack parameter-extracting test plate based on LTCC (Low Temperature Co-Fired Ceramic) substrate - Google Patents
Multichip stack parameter-extracting test plate based on LTCC (Low Temperature Co-Fired Ceramic) substrate Download PDFInfo
- Publication number
- CN102323532B CN102323532B CN 201110154868 CN201110154868A CN102323532B CN 102323532 B CN102323532 B CN 102323532B CN 201110154868 CN201110154868 CN 201110154868 CN 201110154868 A CN201110154868 A CN 201110154868A CN 102323532 B CN102323532 B CN 102323532B
- Authority
- CN
- China
- Prior art keywords
- substrate
- group
- layer
- chip
- stacked chips
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 82
- 238000012360 testing method Methods 0.000 title claims abstract description 50
- 239000000919 ceramic Substances 0.000 title abstract description 3
- 229910052751 metal Inorganic materials 0.000 claims description 20
- 239000002184 metal Substances 0.000 claims description 20
- 241000208340 Araliaceae Species 0.000 claims description 19
- 235000005035 Panax pseudoginseng ssp. pseudoginseng Nutrition 0.000 claims description 19
- 235000003140 Panax quinquefolius Nutrition 0.000 claims description 19
- 235000008434 ginseng Nutrition 0.000 claims description 19
- 230000001939 inductive effect Effects 0.000 claims description 4
- 229910052709 silver Inorganic materials 0.000 claims description 3
- 239000004332 silver Substances 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 5
- 238000011161 development Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 239000000284 extract Substances 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 241000567030 Ampulloclitocybe clavipes Species 0.000 description 1
- RPNUMPOLZDHAAY-UHFFFAOYSA-N Diethylenetriamine Chemical compound NCCNCCN RPNUMPOLZDHAAY-UHFFFAOYSA-N 0.000 description 1
- 206010043101 Talipes Diseases 0.000 description 1
- 201000011228 clubfoot Diseases 0.000 description 1
- 238000005056 compaction Methods 0.000 description 1
- 238000012938 design process Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
Images
Landscapes
- Tests Of Electronic Circuits (AREA)
Abstract
The invention discloses a multichip stack parameter-extracting test plate based on an LTCC (Low Temperature Co-Fired Ceramic) substrate, which comprises the substrate, a first group of chip stack modules, a second group of chip stack modules, a third group of chip stack modules and a fourth group of chip stack modules, wherein the first group of chip stack modules, the second group of chip stack modules, the third group of chip stack modules and the fourth group of chip stack modules are arranged on the substrate; and the substrate, the first group of chip stack modules, the second group of chip stack modules, the third group of chip stack modules and the fourth group of chip stack modules are connected through a bonding wire. The parameter-extracting test plate breaks through the scheme of the traditional LTCC parameter-extracting test plate, thus quantity and complexity of multichip stack layers are increased, model types which can be tested and extracted by the parameter-extracting test plate based on the LTCC substrate are perfected, innovated multichip stack technical levels are verified, especially, the multichip stack parameter-extracting test plate has important significance and reference value for the design and the manufacture of high-complexity multichip stacks.
Description
Technical field:
The present invention relates to a kind of based on LTCC (LTCC) carry the ginseng test board, be applicable to the design parameter test of multi-chip stacking on ltcc substrate and the foundation of respective design parameter model.
Background technology:
High speed SiP (system in package) module has adopted extensive high speed bare chip lamination and the little package technique of high density in Design and manufacturing process, the design of SiP module needs the design parameter model bank of ltcc substrate and bondwire (bonding line).At present, about the modeling of bondwire design parameter seldom, mostly these model banies are to carry out for the bondwire between ltcc substrate and monolithic chip, can't satisfy the design requirement of multi-chip stacking.In the present invention, we have designed and have made nearly that 4 layers of chip-stacked LTCC carry the ginseng test board, this test board has improved the number of plies of multi-chip stacking, first the chip-stacked number of plies 4 layers have been brought up to, this test board is for the design parameter that extracts multi-chip stacking, and the design parameter model bank of setting up multi-chip stacking has good practical value.
Summary of the invention:
Carry the ginseng test board based on the multi-chip stacking of ltcc substrate, in order to extract under special process the design parameter of the design parameter of multi-chip stacking and bondwire on ltcc substrate, and set up the design parameter model bank for the design of SiP module and development, improve the validity of SiP modular design.
Technology of the present invention is dealt with problems and is: that has made a multi-chip stacking based on ltcc substrate carries the ginseng test board, broken through the mode of traditional multi-chip stacking based on ltcc substrate, improved the chip-stacked number of plies, greatly expanded the SiP design parameter version that to test, carry the mould of taking part in building based on ltcc substrate, the development of SiP module and the checking tool of SiP production technology have been of great significance.
What the invention provides a kind of multi-chip stacking based on ltcc substrate carries the ginseng test board, comprises substrate, is arranged on first group of chip stacking module on substrate, second group of chip stacking module, the 3rd group of chip stacking module and the 4th group of chip stacking module; Described first group of chip stacking module is made of the ground floor stacked chips; Described second group of chip stacking module is by the ground floor stacked chips and second layer stacked chips is stacking from the bottom to top consists of; Described the 3rd group of chip stacking module is by ground floor stacked chips, second layer stacked chips and the three level stack chip is stacking from the bottom to top consists of; Described the 4th group of chip stacking module is by ground floor stacked chips, second layer stacked chips, three level stack chip and the 4th layer of stacked chips is stacking from the bottom to top consists of; Described substrate, ground floor stacked chips, second layer stacked chips, three level stack chip and the 4th layer of stacked chips connect by bonding line each other.
Described substrate is divided into 5 layers, and every layer again by metal level with dielectric layer is two-layer forms, and metal level is upper, dielectric layer under.
5 layers of described substrate are respectively first signal layer S1, the first stratum GND, secondary signal layer S2, the 3rd signals layer S3, the second stratum GND from top to bottom.
Described parameter is as follows: the substrate bed thickness is 90 μ m; The specific inductive capacity of substrate media is 7.3 ± 0.2; The substrate metal bed thickness is 7.5 μ m; Substrate cut size: 90 * 90mm
2
Described substrate metal layer is made of silver.
Described ground floor stacked chips, second layer stacked chips, three level stack chip and the 4th layer of stacked chips are that thickness is 0.25mm, the film that is of a size of 15.88mm * 15.88mm consists of.
Originally carry the ginseng test board, broken through the scheme that traditional LTCC carries the ginseng test board, the number of plies and the complexity of multi-chip stacking have been increased, but perfect LTCC carries the version of ginseng test board Test extraction, verified the technological level of the multi-chip stacking of innovation, particularly to high complexity multi-chip stacking design and manufacturing, possess significance and reference value.Based on this test board, extracted the bondwire parameter of ltcc substrate parameter and multi-chip stacking, set up ltcc substrate design parameter model bank and bondwire design parameter model bank.The design parameter model of setting up based on this test board will be effectively applied in the SiP module development of follow-up more extensive and complexity.
Description of drawings:
Fig. 1 is the ltcc substrate structural representation of test board of the present invention;
Fig. 2 is the ltcc substrate outside drawing that the present invention places the SMA head;
Fig. 3 is the stacking ginseng test board schematic diagram of carrying of multilayer chiop of the present invention.
Wherein: TOP is substrate; DD1 is first group of chip stacking module; DD2 is second group of chip stacking module; DD3 is the 3rd group of chip stacking module; DD4 is the 4th group of chip stacking module; Die1 is the ground floor stacked chips; Die2 is second layer stacked chips; Die3 is the three level stack chip; Die4 is the 4th layer of stacked chips; S1 is the first signal layer; GND is plane layer; S2 is the secondary signal layer; S3 is the 3rd signals layer; Bondwire is bonding line.
Embodiment:
Below in conjunction with accompanying drawing, the present invention is described in further detail:
Referring to Fig. 1, Fig. 2 and Fig. 3, a kind of multi-chip stacking based on ltcc substrate carry the ginseng test board, comprise substrate, be arranged on first group of chip stacking module on substrate, second group of chip stacking module, the 3rd group of chip stacking module and the 4th group of chip stacking module; Described first group of chip stacking module is made of the ground floor stacked chips; Described second group of chip stacking module is by the ground floor stacked chips and second layer stacked chips is stacking from the bottom to top consists of; Described the 3rd group of chip stacking module is by ground floor stacked chips, second layer stacked chips and the three level stack chip is stacking from the bottom to top consists of; Described the 4th group of chip stacking module is by ground floor stacked chips, second layer stacked chips, three level stack chip and the 4th layer of stacked chips is stacking from the bottom to top consists of; Described substrate, ground floor stacked chips, second layer stacked chips, three level stack chip and the 4th layer of stacked chips connect by bonding line each other.
Described substrate is divided into 5 layers, and every layer again by metal level with dielectric layer is two-layer forms, and metal level is upper, dielectric layer under.
5 layers of described substrate are respectively first signal layer S1, the first stratum GND, secondary signal layer S2, the 3rd signals layer S3, the second stratum GND from top to bottom.
Described parameter is as follows: the substrate bed thickness is 90 μ m; The specific inductive capacity of substrate media is 7.3 ± 0.2; The substrate metal bed thickness is 7.5 μ m; Substrate cut size: 90 * 90mm
2
Described substrate metal layer is made of silver.
Described ground floor stacked chips, second layer stacked chips, three level stack chip and the 4th layer of stacked chips are that thickness is 0.25mm, the film that is of a size of 15.88mm * 15.88mm consists of.
Based on the multi-chip stacking of ltcc substrate carry the ginseng test board, ltcc substrate wherein is after Multi-stacking compaction, metal level can be embedded in ceramic base material, therefore every layer of metal level upper surface can flush with the base material upper level.Ltcc substrate material characteristic parameter used is as follows:
Substrate bed thickness (fired): 90 μ m;
The specific inductive capacity of substrate media: 7.3 ± 0.2;
Substrate metal bed thickness: 7.5 μ m (Ag);
Substrate cut size: 90 * 90 (mm
2).
Substrate is divided into 5 layers, and every layer again by metal level with dielectric layer is two-layer forms, and metal level is upper, dielectric layer under.Consider that substrate thickness may cause the situation of substrate fracture not, carry out multilayer and repeatedly press under minimum dielectric layer, satisfy the be welded requirement of strength of connector of panel edges.5 layers of substrate are respectively signals layer S1, stratum GND, signals layer S2, signals layer S3, stratum GND from top to bottom.
Test needs by the SMA connector, tested ltcc substrate to be connected with testing apparatus, and the SMA connector is evenly arranged in the surrounding of substrate.For convenience of the connecting test cable, between the SMA head, centre distance keeps 1.35 centimetres.Test request is completed test item as much as possible, needs to place SMA head as much as possible, and according to the size of test base and SMA head, this substrate can be put at most 24 SMA.The SMA connector that in the present invention, test board is used is the 142-0761-861 connector of Emerson company.
In the present invention on test board stacking chip replace with film, film thickness 0.25mm, big or small 15.88mm * 15.88mm.Be evenly distributed with 4 multi-chip stacking modules on ltcc substrate, be respectively 1 layer of chip module DD1,2 layers of chip stacking module DD2,3 layers of chip stacking module DD3,4 layers of chip stacking module DD4.Substrate is called TOP, and stacked chips is called Die1, Die2, Die3, Die4 from bottom to top.Between chip, be connected signal by bondwire between chip and substrate.The important purpose of this test board is exactly the parameter of Test extraction bondwire, sets up the bondwire design parameter model bank of multi-chip stacking.
The bondwire type of this test board is: the bondwire on DD1 is Die1 to TOP's; Bondwire on DD2 is divided into Die2 to TOP, and Die2 arrives TOP's again to Die1; Bondwire on DD3 is divided into Die3 to TOP, Die3 arrives TOP again to Die1, and Die3 arrives TOP again to Die2, and Die3 arrives TOP's again to Die2 to Die1; Bondwire on DD4 is divided into Die4 to TOP, Die4 arrives TOP again to Die1, Die4 arrives TOP again to Die2, and Die4 arrive TOP again to Die3 to Die1, and Die4 arrives Die2 to Die3 and arrives Die1 and arrive TOP's again.For bondwire is tested, the SMA head at test board edge all will be guided in the two ends of bondwire, and therefore, every kind of bondwire will be the same two of Parallel Symmetric, two bondwire are at a distance of 500 μ m, are connected with very short bondwire line on the film of top layer.The bondwire that arrives the TOP layer links the SMA head of panel edges with microstrip line or strip line and via hole.
The ltcc substrate structural representation of this test board as shown in Figure 1, S1, S2, S3 are signals layer, GND is the stratum, the most beneath is the dielectric layer that adds for satisfying ltcc substrate intensity.
| S1 | Metal | Signals layer | 7.5μm |
| Medium | Bottom | 82.5μm | |
| GND | Metal | Plane layer | 7.5μm |
| Medium | Bottom | 82.5μm | |
| S2 | Metal | Signals layer | 7.5μm |
| Medium | Bottom | 82.5μm | |
| S3 | Metal | Signals layer | 7.5μm |
| Medium | Bottom | 82.5μm | |
| GND | Metal | Plane layer | 7.5μm |
| Medium | Bottom | Manufacturing process determination |
The SMA connector distribution schematic diagram at this test board edge as shown in Figure 2, peripheral box indicating LTCC test base in figure, the blockage of edge black is the SMA connector, the centre distance of two SMA connectors is 1.35cm.
As shown in figure as left in Fig. 3, for the carrying of multi-chip stacking based on ltcc substrate joined the test board schematic diagram.Outmost large square frame is ltcc substrate, represents with TOP, and the blockage of the inside is all that the identical film of size is chip, and N layer chip represents with DieN.Broken line is bondwire, and for example bondwire2-1-TOP is that Die2 arrives the bondwire of TOP again to Die1.The right figure of Fig. 3 is the cross sectional representation of bondwire.Wherein l, m, n are the length of each section of bondwire, and (r1, θ 1) and (r2, θ 2) is respectively radius and the opening angle of two clubfoot arcs of bondwire.
The present invention design and produce based on the multi-chip stacking of ltcc substrate carry the ginseng test board, can extract ltcc substrate parameter and bondwire parameter by test, set up ltcc substrate design parameter model bank and bondwire design parameter model bank.
Above content is in conjunction with concrete preferred implementation further description made for the present invention; can not assert that the specific embodiment of the present invention only limits to this; for the general technical staff of the technical field of the invention; without departing from the inventive concept of the premise; can also make some simple deduction or replace, all should be considered as belonging to the present invention and determine scope of patent protection by claims of submitting to.
Claims (6)
- One kind based on the multi-chip stacking of ltcc substrate carry the ginseng test board, it is characterized in that: comprise substrate, be arranged on first group of chip stacking module on substrate, second group of chip stacking module, the 3rd group of chip stacking module and the 4th group of chip stacking module; Described first group of chip stacking module is made of the ground floor stacked chips; Described second group of chip stacking module is by the ground floor stacked chips and second layer stacked chips is stacking from the bottom to top consists of; Described the 3rd group of chip stacking module is by ground floor stacked chips, second layer stacked chips and the three level stack chip is stacking from the bottom to top consists of; Described the 4th group of chip stacking module is by ground floor stacked chips, second layer stacked chips, three level stack chip and the 4th layer of stacked chips is stacking from the bottom to top consists of; Described substrate, ground floor stacked chips, second layer stacked chips, three level stack chip and the 4th layer of stacked chips connect by bonding line each other.
- As claimed in claim 1 a kind of multi-chip stacking based on ltcc substrate carry the ginseng test board, it is characterized in that: described substrate is divided into 5 layers, every layer again by metal level with dielectric layer is two-layer forms, metal level is upper, dielectric layer under.
- As claimed in claim 2 a kind of multi-chip stacking based on ltcc substrate carry the ginseng test board, it is characterized in that: 5 layers of described substrate are respectively first signal layer S1, the first stratum GND, secondary signal layer S2, the 3rd signals layer S3, the second stratum GND from top to bottom.
- As claimed in claim 2 a kind of multi-chip stacking based on ltcc substrate carry the ginseng test board, it is characterized in that, the substrate bed thickness is 90 μ m; The specific inductive capacity of substrate media is 7.3 ± 0.2; The substrate metal bed thickness is 7.5 μ m; Substrate cut size: 90 * 90mm 2
- As claimed in claim 2 a kind of multi-chip stacking based on ltcc substrate carry the ginseng test board, it is characterized in that: described substrate metal layer is made of silver.
- As claimed in claim 2 a kind of multi-chip stacking based on ltcc substrate carry the ginseng test board, it is characterized in that: described ground floor stacked chips, second layer stacked chips, three level stack chip and the 4th layer of stacked chips are that thickness is 0.25mm, the film that is of a size of 15.88mm * 15.88mm consists of.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201110154868 CN102323532B (en) | 2011-06-10 | 2011-06-10 | Multichip stack parameter-extracting test plate based on LTCC (Low Temperature Co-Fired Ceramic) substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201110154868 CN102323532B (en) | 2011-06-10 | 2011-06-10 | Multichip stack parameter-extracting test plate based on LTCC (Low Temperature Co-Fired Ceramic) substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102323532A CN102323532A (en) | 2012-01-18 |
| CN102323532B true CN102323532B (en) | 2013-06-05 |
Family
ID=45451313
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201110154868 Active CN102323532B (en) | 2011-06-10 | 2011-06-10 | Multichip stack parameter-extracting test plate based on LTCC (Low Temperature Co-Fired Ceramic) substrate |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102323532B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8972918B2 (en) * | 2012-01-27 | 2015-03-03 | Taiwan Semiconductor Manufacturing Co. Ltd. | System and method for functional verification of multi-die 3D ICs |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1949468A (en) * | 2006-09-01 | 2007-04-18 | 中国航天时代电子公司第七七一研究所 | Method for interconnecting and packaging 3-D multi-chip module |
| CN201215805Y (en) * | 2007-11-02 | 2009-04-01 | 中国电子科技集团公司第十研究所 | LTCC integrated package millimeter wave component |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060162844A1 (en) * | 2005-01-26 | 2006-07-27 | Needes Christopher R | Multi-component LTCC substrate with a core of high dielectric constant ceramic material and processes for the development thereof |
-
2011
- 2011-06-10 CN CN 201110154868 patent/CN102323532B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1949468A (en) * | 2006-09-01 | 2007-04-18 | 中国航天时代电子公司第七七一研究所 | Method for interconnecting and packaging 3-D multi-chip module |
| CN201215805Y (en) * | 2007-11-02 | 2009-04-01 | 中国电子科技集团公司第十研究所 | LTCC integrated package millimeter wave component |
Non-Patent Citations (1)
| Title |
|---|
| JP特开2006-253117A 2006.09.21 |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102323532A (en) | 2012-01-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102074540B (en) | Matrix dual in-line package (DIP) lead frame, integrated circuit (IC) packages based on frame and production method of IC packages | |
| HK1087534A1 (en) | Impedance matching along vertical path of microwave vias in multilayer packages | |
| CN103140058A (en) | Glue overflow control method of laminar structure | |
| CN104054172A (en) | Interposer For Stacked Semiconductor Devices | |
| CN102323532B (en) | Multichip stack parameter-extracting test plate based on LTCC (Low Temperature Co-Fired Ceramic) substrate | |
| CN104538311B (en) | A kind of ltcc substrate 3D laminated construction | |
| CN107666768A (en) | Aligning degree monitoring method between PCB layer | |
| CN108235602A (en) | The processing method that second order buries copper billet circuit board | |
| CN208158980U (en) | A kind of welt double step groove pcb board structure for bare chip test | |
| CN109996400A (en) | A method of improving asymmetric folded structure pcb board and sticks up | |
| CN101404279A (en) | Multi-chip 3D stacking and packaging structure | |
| CN101699930A (en) | Glue filling and laminating method of circuit board | |
| CN201315319Y (en) | Multichip 3D stacked encapsulating structure | |
| CN205657905U (en) | Modularization multilayer circuit board of accuracy of counterpointing | |
| CN107340464A (en) | Stack type test interface plate and manufacturing method thereof | |
| CN101840774A (en) | Small-area transformer with on-chip laminated structure | |
| CN201853700U (en) | Array type double in-line package (DIP) lead frame and integrated circuit (IC) encapsulating piece of frame | |
| Xie et al. | A 3D package design with cavity substrate and stacked die | |
| CN206292352U (en) | Stack type test interface plate | |
| CN205140976U (en) | Package substrate | |
| CN201812817U (en) | Adapter substrate of integrated circuit package | |
| CN101944512A (en) | Switching base plate packaged by integrated circuit | |
| CN104517934A (en) | Method for manufacturing interconnected and stacked semiconductor devices | |
| CN205149058U (en) | Prevent off normal laminate assembly | |
| CN203775518U (en) | PCB multilayer board with through hole |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20221221 Address after: 451161 Tower C, Xinggang Building, No. 16, Huhang Road, Zhengzhou Airport Economic Comprehensive Experimental Zone, Zhengzhou City, Henan Province Patentee after: Zhengzhou Xinghang Technology Co.,Ltd. Address before: 710054 Shaanxi province Xi'an Taiyi Road No. 189 Patentee before: NO.771 INSTITUTE OF NO.9 RESEARCH INSTITUTE, CHINA AEROSPACE SCIENCE AND TECHNOLOGY Corp. |
|
| TR01 | Transfer of patent right |