CN102315156A - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
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- CN102315156A CN102315156A CN2010102282220A CN201010228222A CN102315156A CN 102315156 A CN102315156 A CN 102315156A CN 2010102282220 A CN2010102282220 A CN 2010102282220A CN 201010228222 A CN201010228222 A CN 201010228222A CN 102315156 A CN102315156 A CN 102315156A
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Abstract
The invention provides a method for manufacturing a semiconductor device. The method comprises the steps of: preparing a semiconductor chip, and sequentially forming an etching stopping layer, an interlayer dielectric layer and a patterned photoresist layer on the top layer of the semiconductor chip; etching the interlayer dielectric layer by taking the photoresist layer as a mask until the etching stopping layer is exposed in a first process reaction cavity (401A); delivering the semiconductor chip to a second process reaction cavity (401B); removing the photoresist layer in the second process reaction cavity (401B); delivering the semiconductor chip back to the first process reaction cavity (401A); and etching the etching stopping layer by taking the etched interlayer dielectric layer as a mask in the first process reaction cavity (401A). According to the method for manufacturing the semiconductor device, residual fluorine from etching treatment can be prevented from damaging a low-k material layer in subsequent treatment, so that the shape of a channel profile is improved and the electrical performance of the semiconductor device is increased.
Description
Technical field
The present invention relates to a kind of method that is used for producing the semiconductor devices, and in particular to a kind of technology that can improve the ditch grooved profile pattern in the interlayer dielectric layer (ILD) that constitutes by low-k materials.
Background technology
At present, plasma etch process is widely used in defining the structure of silicon integrated circuit as a kind of semiconductor fabrication process.In copper wiring technique because the more difficult etching of copper, so utilize usually plasma etch process at interlayer dielectric layer (ILD) thus in etch through hole or groove is wherein realized conductivity interconnection (Damascus method) so that metal is inserted.Generally speaking, ILD is made up of the material based on silicon dioxide.
As IC is made to inferior 45nm and following development, and interconnect delay becomes the speed of raising integrated circuit (IC) and a key constraints of performance.As everyone knows, one of mode that in semiconductor fabrication process, minimizes interconnect delay is during making IC, to use low-k (low k) material to reduce interconnection capacitance.Thereby in recent years, low-k materials has replaced the higher relatively insulating material of dielectric constant (like, silicon dioxide etc.) gradually and has been used as the metal level interlayer dielectric layer or the layer inner-dielectric-ayer (IMD) of semiconductor device.In addition, wherein form porose porous low k dielectric material in order further to reduce the dielectric constant of insulating material, can to use, for example, black brill (BD) etc.This low-k materials layer can form through being similar to the spin-coating method or the chemical vapor deposition (CVD) method that apply photoresist (PR).Thereby the use of low-k materials is easy to the conventional semiconductor manufacturing process compatible.
Yet,, use the semiconductor technology of this low-k materials still to have many problems although low-k materials is widely used in semiconductor fabrication process owing to having above-mentioned plurality of advantages.At first, during semiconductor was made, the low-k materials layer compares to traditional dielectric layer usually will be easy to occur damage, and for example, it is impaired during etch process that is used for dielectric layer is carried out composition and plasma ashing technology easily.In addition, some low-k materials when impaired, especially after composition technology, suction or can change the technology pollutant reaction of the electrical properties of dielectric layer easily with other, thereby cause the dielectric constant of low-k materials to increase and thereby lose the advantage of its low k.
Conventionally; The general dry plasma cineration technics that adopts is removed PR residual after the etching etc. and employing (all-in-one) technology that integrates entirely from the semiconductor device with low-k materials layer; That is etching ,-PR mask layer peels off-and etching stopping layer etching three process all carries out in same technological reaction chamber.Figure 1A shows the profile of the groove before the etching stopping layer etching, and Figure 1B shows the profile of the groove after the etching stopping layer etching.Shown in Figure 1A, in ILD 102, a plurality of grooves have been formed with through etch processes.It is that mask is removed the part in said a plurality of grooves of etching stopping layer 101 through etching that the etching stopping layer etching processing is meant with the ILD layer, and said etching stopping layer 101 formed before forming ILD 102 and is positioned at below the ILD 102, and it is for example by SiO
2Constitute.Fig. 2 shows the top view Figure 200 according to the control technology board process semiconductor wafers of prior art.As shown in Figure 2; Normally used multi-cavity integrated equipment mainly comprise a plurality of technological reactions chamber 201 (as, 201A and 201B), a plurality of digital flow controller (DFC) 202, wafer handling chamber 203, chip oriented device 204, horse vacuum lock 205 and platform 206.In a plurality of technological reactions chamber 201 each all be isolated from each other, separate and be respectively equipped with DFC 202, and the flow velocity of each source gas in the corresponding technological reaction of each DFC 202 control chamber.Horse vacuum lock 205 is inlets that wafer gets into the multi-cavity integrated equipment, and it isolates inside and external environment condition, and vacuum degree is locked into the technological reaction chamber from the horse vacuum and improves gradually.Platform 206 has numeral or graphic user interface (not shown) in its oriented manipulation person's a side; During etch process; The operator controls the various etch process parameters in whole etching process procedure through this user interface; For example, control the flow velocity of each source gas in each technological reaction chamber through control DFC 202.
Particularly; During the etch process of low-k materials layer; To treat that at first etched wafer is loaded on the platform 206; Then make the wafer that is loaded be sent to a technological reaction chamber in a plurality of technological reactions chamber 201 via wafer handling chamber 203 through chip oriented device 204; For example 201A carries out etch processes, PR mask layer lift-off processing and etching stopping layer etching processing then successively in this technological reaction chamber, will accomplish the wafer of handling in whole three roads at last and send back platform 206 via wafer handling chamber 203.Wherein, the operator is through controlling whole technical process with above-mentioned user interface interaction, and in the whole technical process flow process control of wafer shown in arrow among Fig. 2.
Traditionally, the dry plasma cineration technics adopts O
2Peel off.As stated, in the technology that integrates entirely, adopt O
2Carrying out the PR mask layer peels off; All in same technological reaction chamber, carry out owing to all handle; So in the etch processes step residual fluorine will be in subsequent P R mask layer lift-off processing as in the etch processes, continuing the etching low-k materials, thereby it is caused damage (hereinafter being called " memory effect (memory effect) ").
On the other hand; Because low-k materials commonly used (as; BD etc.) contain carbon and protium in, and these elements easily with plasma in oxygen react and generate the gaseous state product, so modification can take place or bounce back (pull-back) at the sidewall of low-k materials; Thereby cause ditch grooved profile pattern not good, influence the electric property of semiconductor device.Therefore, replace O
2Stripping technology, the dry plasma cineration technics has begun to adopt CO
2Peel off.Adopt CO
2Peeling off is to react owing to the oxygen and the carbon in the low-k materials that itself contain carbon and can suppress in the plasma according to chemical equilibrium theory, thereby can reduce the sidewall damage in the PR mask layer stripping process.Yet, because carbon content increases formation-CH
2The high molecular probability of-long-chain increases thereupon, by the fluorine generation-CHF-and-CF that remain in after the preceding road etch processes in the technological reaction chamber
2The ratio of-group also increases thereupon.If adopt the technology that integrates entirely; Then the fluorine in these fluoro containing polymers carbochains that in etch processes and PR mask layer lift-off processing, generate follow-up processing (as; PR mask layer lift-off processing and etching stopping layer etching processing) in will be dissociated out once more and wafer reacts, thereby cause " memory effect " more serious.Though before PR mask layer lift-off processing, having increased by a step emptying (pump down) in the prior art handles; But emptying process can only be got rid of gaseous products; And most fluorine be with the form of this type of macromolecule carbochain solid residue attached on the inwall in technological reaction chamber, thereby emptying process can not significantly reduce " memory effect ".
Fig. 3 A to 3C shows the SEM profile of the groove of the technology making of integrating entirely of adopting prior art.Shown in Fig. 3 A, before PR mask layer lift-off processing, ditch grooved profile pattern is good, no top rounding or obvious retraction.Yet, can not remove fluorine-containing macromolecule carbochain solid residue because peel off the PR mask layer, so the isotropic etching that produces owing to " memory effect " can cause serious low-k materials damage through the high pressure plasma ashing treatment.Shown in Fig. 3 B, obviously greater than the width of its underpart, obviously retraction appears to the width on groove top in trenched side-wall.In addition; Since in the actual process process in order due care to be carried out on its surface when the etching low-k materials; Usually can on the low-k materials layer, form the TEOS protective layer; So after the further etch damage low-k materials of residual fluorine layer, can form TEOS " cap (cap) " at the groove top, like the indicated part of circle among Fig. 3 B.In Fig. 3 C, illustrated after etch processes through low pressure and peeled off the PR mask layer and the ditch grooved profile that forms; Under the low pressure condition; Long-time high-octane plasma bombardment makes that the TEOS protective layer is exhausted prematurely, thereby because the isotropic etching that " memory effect " produces causes the trenched side-wall top rounding in the low-k materials layer.This shows whether ditch grooved profile pattern well depends primarily on PR mask layer lift-off processing but not etch processes.
In sum, in order to improve ditch grooved profile pattern, press for a kind of method, semi-conductor device manufacturing method that can significantly reduce " memory effect ".
Summary of the invention
In the summary of the invention part, introduced the notion of a series of reduced forms, this will further explain in the embodiment part.Summary of the invention part of the present invention does not also mean that key feature and the essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range of attempting to confirm technical scheme required for protection.
For addressing the above problem; The present invention provides a kind of method that is used for producing the semiconductor devices; Comprise the following steps: a) the preparation semiconductor wafer, be formed with etching stopping layer, interlayer dielectric layer in order and have the photoresist layer of pattern at the top layer of said semiconductor wafer; B) in the first technological reaction chamber, be that the said interlayer dielectric layer of mask etching is to exposing said etching stop layer with said photoresist layer; C) said semiconductor wafer is sent to the second technological reaction chamber; D) in the said second technological reaction chamber, remove said photoresist layer; E) said semiconductor wafer is sent back the said first technological reaction chamber; F) in the said first technological reaction chamber, be the said etching stopping layer of mask etching with the interlayer dielectric layer after the said etching.
Preferably, between step b) and step e), comprise the following steps: gas is passed in the said first technological reaction chamber and purge or carry out emptying process.Said gas for example is N
2Or Ar
2
Preferably, said interlayer dielectric layer is made up of low-k materials.
Preferably, said low-k materials is black boring.
Preferably, comprise fluorine-containing residue in the said first technological reaction chamber.
Preferably, do not comprise fluorine-containing residue in the said second technological reaction chamber.
Preferably, said photoresist stripping technology adopts and is selected from O
2, O
2/ H
2O and CO
2In at least a gas peel off.
The present invention further provides a kind of integrated circuit that comprises the semiconductor device of handling through aforesaid method, and wherein said integrated circuit is selected from random access memory, dynamic random access memory, synchronous RAM, static RAM, read-only memory, programmable logic array, application-specific integrated circuit (ASIC), buried type DRAM and radio circuit.
The present invention further provides a kind of electronic equipment that comprises the semiconductor device of handling through aforesaid method, and wherein said electronic equipment is selected from personal computer, portable computer, game machine, cellular phone, personal digital assistant, video camera and digital camera.
The method that is used for producing the semiconductor devices according to the present invention is carried out in two different processes reaction chambers respectively through making photoresist layer lift-off processing and etch processes and etching stopping layer remove processing; Can prevent that fluorine residual in the etch processes from causing damage to the low-k materials layer in subsequent technique, thereby improve ditch grooved profile pattern and improve the electric property of semiconductor device.
Description of drawings
Attached drawings of the present invention is used to understand the present invention at this as a part of the present invention.Embodiments of the invention and description thereof have been shown in the accompanying drawing, have been used for explaining principle of the present invention.In the accompanying drawings:
Figure 1A and 1B show etching stopping layer respectively and remove before the processing and the profile of groove afterwards;
Fig. 2 shows the top view Figure 200 according to the control technology board process semiconductor wafers of prior art;
Fig. 3 A to 3C shows scanning electron microscopy (SEM) profile of the groove of the technology making of integrating entirely of adopting prior art; Wherein, Fig. 3 A shows after etch processes and the ditch grooved profile before PR mask layer lift-off processing; Fig. 3 B shows after etch processes through high pressure and peels off the PR mask layer and the ditch grooved profile that forms, and Fig. 3 C shows after etch processes through low pressure and peels off the PR mask layer and the ditch grooved profile that forms;
Fig. 4 shows the top view 400 according to control technology board process semiconductor wafers of the present invention;
Fig. 5 shows the flow chart 500 according to the method that is used for producing the semiconductor devices of the present invention;
Fig. 6 A to 6B shows the SEM profile of employing according to the groove of method making of being used for producing the semiconductor devices according to the present invention; Wherein, Fig. 6 A shows after etch processes and the ditch grooved profile before PR mask layer lift-off processing, and Fig. 6 B shows after etch processes through low pressure and peels off the PR mask layer and the ditch grooved profile that forms.
Embodiment
In the description hereinafter, a large amount of concrete details have been provided so that more thorough understanding of the invention is provided.Yet, it will be apparent to one skilled in the art that the present invention can need not one or more these details and be able to enforcement.In other example,, describe for technical characterictics more well known in the art for fear of obscuring with the present invention.
In order thoroughly to understand the present invention, will in following description, detailed steps be proposed, thereby so that how explanation the present invention handles damage during low-k materials layer and improve the ditch grooved profile through adopting the technology that partly integrates to prevent to remove at etching stopping layer.Obviously, execution of the present invention is not limited to the specific details that the technical staff had the knack of of semiconductor applications.Preferred embodiment of the present invention is described in detail as follows, yet except these were described in detail, the present invention can also have other execution modes.
Fig. 4 shows the top view 400 according to control technology board process semiconductor wafers of the present invention.As shown in Figure 4, normally used multi-cavity integrated equipment mainly comprise a plurality of technological reactions chamber 401 (as, 401A and 401B), digital flow controller (DFC) 402, wafer handling chamber 403, chip oriented device 404, horse vacuum lock 405 and platform 406.In a plurality of technological reactions chamber 401 each all be isolated from each other, separate and be respectively equipped with DFC 402, and the flow velocity of each source gas in the corresponding technological reaction of each DFC 402 control chamber.Horse vacuum lock 405 is inlets that semiconductor wafer gets into the multi-cavity integrated equipment, and it isolates inside and external environment condition, and vacuum degree is locked into the technological reaction chamber from the horse vacuum and improves gradually.Platform 406 has numeral or graphic user interface (not shown) in its oriented manipulation person's a side; During etch process; The operator controls the various etch process parameters in the whole etching process procedure through this user interface; For example, control the flow velocity of each source gas in each technological reaction chamber through control DFC 402.
Particularly; During the etch process of low-k materials layer; To treat that at first etched semiconductor wafer is loaded on the platform 406; Wherein, be formed with etching stopping layer, interlayer dielectric layer and photoresist layer in order at the top layer of said semiconductor wafer, and said photoresist layer has and will be transferred to the pattern on the said interlayer dielectric layer through said etch processes.Then; Make through chip oriented device 404 semiconductor wafer that loaded via wafer handling chamber 403 be sent to a technological reaction chamber in a plurality of technological reactions chamber 401 (as; Technological reaction chamber 401A); And in this technological reaction chamber, carry out etch processes, with the said photoresist layer that has pattern as mask etching interlayer dielectric layer, to exposing said etching stop layer.Then, the semiconductor wafer that will pass through etch processes is transferred to another technological reaction chamber in a plurality of technological reactions chamber 401 (like, technological reaction chamber 401B), and in this technological reaction chamber, carries out PR mask layer lift-off processing.Then, with peeling off the technological reaction chamber that semiconductor wafer behind the PR is carried out etch processes before sending back to, and be the etching processing that mask is carried out etching stopping layer with the interlayer dielectric layer after the etching therein.At last, send back platform 406 with accomplishing the semiconductor wafer of handling in whole three roads via wafer handling chamber 403.Wherein, the operator is through controlling whole technical process with above-mentioned user interface interaction, and in the whole technical process flow process control of semiconductor wafer shown in arrow among Fig. 4.In addition; There is fluorine-containing macromolecule carbochain solid residue in a said technological reaction chamber thereby is called as the fluorine chamber hereinafter owing to residual therein after etch processes; And said another technological reaction chamber is not fluorine-containing owing to the etch processes of not carrying out the fluorine-containing source of any use gas before therein, thereby is called as non-fluorine chamber hereinafter.In addition, after accomplishing etch processes and carry out etching stopping layer remove handle before, can in the fluorine chamber, increase by one and go on foot emptying process and perhaps gas is passed into and purges (flush) in the fluorine chamber, with the fluoro-gas in the evacuation chamber.Described purge gas for example is N
2Or Ar
2
Next, will the technological process according to the method that is used for producing the semiconductor devices of the present invention be described with reference to Fig. 5.
Fig. 5 shows the flow chart 500 according to the method that is used for producing the semiconductor devices of the present invention.
At first, in step 501, on the topsheet surface of front end device, form etching stopping layer, interlayer dielectric layer and photoresist layer in order and this photoresist layer is carried out composition, treat etched semiconductor device with preparation.Here, said interlayer dielectric layer can use and wherein form porose porous low k dielectric material (like, BD etc.) and form through spin-coating method or CVD method.Then, the semiconductor wafer for preparing is sent to the first technological reaction chamber 401A in the multi-cavity integrated equipment via wafer handling chamber 403.
Then, in step 502, in the first technological reaction chamber 401A, be that mask is carried out etch processes to semiconductor wafer with said photoresist layer, with the etching interlayer dielectric layer to exposing said etching stop layer.Here, etched source gas for example can comprise Cl
2, BCl
3And CHF
3Alternatively, etched source gas also can comprise CF
4, CH
2F
2, CH
3F and CH
4In one or more.
Then, in step 503, the semiconductor wafer after etch processes is sent to the second technological reaction chamber 401B that is different from the first technological reaction chamber 401A in the multi-cavity integrated equipment via wafer handling chamber 403.
Then, in step 504, in the second technological reaction chamber 401B, semiconductor wafer is carried out PR mask layer lift-off processing.Simultaneously, can feed for example N
2Or Ar
2Gas in the first technological reaction chamber 401A, purge or carry out emptying process, to remove residual etching source gas in the reaction chamber.
Then, in step 505, will send back the first technological reaction chamber 401A through the semiconductor wafer after the PR mask layer lift-off processing.
At last, in step 506, in the first technological reaction chamber 401A, be the etching stopping layer of mask etching semiconductor wafer with the interlayer dielectric layer after the etching.Here, etched source gas for example can comprise Cl
2, BCl
3And CHF
3Alternatively, etched source gas also can comprise CF
4, CH
2F
2, CH
3F and CH
4In one or more.
[advantageous effects of the present invention]
Next, with describing fluorine chamber and non-fluorine chamber Different Effects, thereby further specify advantageous effects according to the method that is used for producing the semiconductor devices of the present invention to etch-rate.
Adopt identical technological parameter in fluorine chamber and non-fluorine chamber, to carry out PR mask layer lift-off processing, for example, pressure is 40mT, CO
2Flow velocity be 300sccm, wherein, sccm is under the standard state, just 1 atmospheric pressure, 1 cubic centimetre of (1cm of 25 degrees centigrade of following per minutes
3/ min) flow.Obtain two groups of experimental result statistical data analysis through repeatedly testing, shown in the following table 1.
Form 1
In form 1,3 σ are three times of mean square deviations, the uniformity coefficient that its reaction statistics distributes, and the dispersion degree of scope reaction statistics, and it is obtained through following equality 1:
Scope=0.5 * (maximum-minimum value)/mean value
From form 1, can find out, at the CO that adopts the same process parameter
2Under the situation of plasma ashing technology, the mean value of the etch-rate in the fluorine chamber almost is two sesquialters of the mean value of the etch-rate in the non-fluorine chamber.This shows, compares with non-fluorine chamber, in the fluorine chamber, shows significant " memory effect ".
Therefore, the method that is used for producing the semiconductor devices according to the present invention is carried out through PR mask layer lift-off processing is transferred to the non-fluorine chamber from the fluorine chamber, can prevent using CO
2The dry plasma cineration technics during generate the fluorine-containing solid-state attachment of macromolecule carbochain, thereby can significantly reduce " memory effect ".
Fig. 6 A to 6B shows the SEM profile of employing according to the groove of method making of being used for producing the semiconductor devices according to the present invention, is used to explain the advantageous effects according to the method that is used for producing the semiconductor devices of the present invention.Wherein, Fig. 6 A shows after etch processes and the ditch grooved profile before PR mask layer lift-off processing, and Fig. 6 B shows after etch processes through low pressure and peels off the PR mask layer and the ditch grooved profile that forms.Shown in Fig. 6 A, before PR mask layer lift-off processing, ditch grooved profile pattern is good, no top rounding or obvious retraction.Shown in Fig. 6 B; Through the method that is used for producing the semiconductor devices according to the present invention; After PR mask layer lift-off processing, the good ditch grooved profile pattern before the PR mask layer lift-off processing is able to keep, trenched side-wall comparatively vertically, do not present obvious retraction and the top does not have obvious rounding.Compare with the ditch grooved profile pattern of the prior art shown in Fig. 3 C, the ditch grooved profile pattern according to the present invention shown in Fig. 6 B obviously improves.
In addition; Because being removed processing, etch processes, PR mask layer lift-off processing and etching stopping layer separately carry out in two different process reaction chambers in the multi-cavity integrated equipment, so can also when preceding bulk of semiconductor crystal chips is carried out PR mask layer lift-off processing, in the fluorine chamber, continue the next group semiconductor wafer is carried out etch processes.Therefore, the method that is used for producing the semiconductor devices according to the present invention not only need not to increase the technology number but also can boost productivity.
In sum; The method that is used for producing the semiconductor devices according to the present invention is carried out in two different processes reaction chambers respectively through making PR mask layer lift-off processing and etch processes and etching stopping layer remove processing; Can prevent that fluorine residual in the etch processes from causing damage to the low-k materials layer in subsequent technique, thereby improve ditch grooved profile pattern and improve the electric property of semiconductor device.
[industrial usability of the present invention]
Semiconductor device according to aforesaid embodiment manufacturing can be applicable in the multiple integrated circuit (IC).According to IC of the present invention for example is memory circuitry, like random-access memory (ram), dynamic ram (DRAM), synchronous dram (SDRAM), static RAM (SRAM) (SRAM) or read-only memory (ROM) or the like.According to IC of the present invention can also be logical device, like programmable logic array (PLA), application-specific integrated circuit (ASIC) (ASIC), combination type DRAM logical integrated circuit (buried type DRAM), radio circuit or other circuit devcies arbitrarily.IC chip according to the present invention can be used for for example consumer electronic products; In various electronic products such as personal computer, portable computer, game machine, cellular phone, personal digital assistant, video camera, digital camera, mobile phone, especially in the radio frequency products.
The present invention is illustrated through the foregoing description, but should be understood that, the foregoing description just is used for for example and illustrative purposes, but not is intended to the present invention is limited in the described scope of embodiments.In addition, it will be appreciated by persons skilled in the art that the present invention is not limited to the foregoing description, can also make more kinds of variants and modifications according to instruction of the present invention, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by appended claims book and equivalent scope thereof.
Claims (10)
1. a method that is used for producing the semiconductor devices comprises the following steps:
A) preparation semiconductor wafer is formed with etching stopping layer, interlayer dielectric layer in order and has the photoresist layer of pattern at the top layer of said semiconductor wafer;
B) in the first technological reaction chamber, be that the said interlayer dielectric layer of mask etching is to exposing said etching stop layer with said photoresist layer;
C) said semiconductor wafer is sent to the second technological reaction chamber;
D) in the said second technological reaction chamber, remove said photoresist layer;
E) said semiconductor wafer is sent back the said first technological reaction chamber;
F) in the said first technological reaction chamber, be the said etching stopping layer of mask etching with the interlayer dielectric layer after the said etching.
2. method according to claim 1 wherein, also comprises the following steps: gas is passed in the said first technological reaction chamber between step b) and step e) and purges or carry out emptying process.
3. method according to claim 2, wherein, said gas is N
2Or Ar
2
4. method according to claim 1, wherein, said interlayer dielectric layer is made up of low-k materials.
5. method according to claim 4, wherein, said low-k materials is black boring.
6. method according to claim 1 wherein, comprises fluorine-containing residue in the said first technological reaction chamber.
7. method according to claim 6 wherein, does not comprise fluorine-containing residue in the said second technological reaction chamber.
8. method according to claim 1, wherein, the removal of said photoresist is adopted and is selected from O
2, O
2/ H
2O and CO
2In at least a gas peel off.
9. integrated circuit that comprises the semiconductor device of making through method according to claim 1, wherein said integrated circuit is selected from random access memory, dynamic random access memory, synchronous RAM, static RAM, read-only memory, programmable logic array, application-specific integrated circuit (ASIC), buried type DRAM and radio circuit.
10. electronic equipment that comprises the semiconductor device of making through method according to claim 1, wherein said electronic equipment is selected from personal computer, portable computer, game machine, cellular phone, personal digital assistant, video camera and digital camera.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111628022A (en) * | 2019-02-28 | 2020-09-04 | 中国科学院物理研究所 | GaAs-based photoelectric device and preparation method of array thereof |
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| CN1643651A (en) * | 2002-03-19 | 2005-07-20 | 应用材料股份有限公司 | In-situ integrated dielectric etch process particularly useful for multi-chamber substrate treatment system |
| US20040256351A1 (en) * | 2003-01-07 | 2004-12-23 | Hua Chung | Integration of ALD/CVD barriers with porous low k materials |
| CN1851871A (en) * | 2005-12-07 | 2006-10-25 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Polycrystalline silicon etching process capable of removing residual gas |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111628022A (en) * | 2019-02-28 | 2020-09-04 | 中国科学院物理研究所 | GaAs-based photoelectric device and preparation method of array thereof |
| CN111628022B (en) * | 2019-02-28 | 2022-07-15 | 中国科学院物理研究所 | GaAs-based photoelectric device and preparation method of array thereof |
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