CN102314215B - Low power consumption optimization method of decimal multiplier in integrated circuit system - Google Patents
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Abstract
The invention discloses a low power consumption optimization method of a decimal multiplier in an integrated circuit system, which mainly solves the problem that extra logic is introduced into the system in a low power consumption design so that the system power consumption is affected. The method mainly comprises the steps that: (1) a multiplier module is constructed; (2) coefficients are integerized; (3) digital quantity with regular symbols are optimized; (4) optimization results are extracted; (5) Horner optimization is carried out; and (6) the decimal multiplier is replaced. The low power consumption optimization method of the decimal multiplier in the integrated circuit system has the advantages of high operation speed, few occupied resources, simplicity and easiness, can greatly reduce the power consumption and the area of the system without reducing the working efficiency and losing the operation precision of the system, and is applicable to systems containing a large number of decimal multipliers, such as digital signal processing systems, digital filters and the like.
Description
Technical field
The invention belongs to electronic technology field, further relate to the low power consumption optimization method of decimal multiplier in technical field of integrated circuits.The present invention is based on canonic signed digit algorithm (CSD) and Huo Na algorithm (Horner Scheme), the Low Power Optimization of the system that can be used for containing multiplication of decimals device in integrated circuit.
Background technology
In Design of Digital Circuit, reducing redundant signals upset is a kind of common methods that reduces system power dissipation, but the method need to increase extra control circuit in system, and this can make system introduce extra power consumption and area that this control circuit brings.
The patented technology that Langchao Electronic Industry Group Corp has " a kind of method for designing of the dynamic multi-clock low power consumption AHB bus for SOC " (application number: CN200910014266.0, notification number: disclose a kind of gated clock method for designing CN101493717), be used for reducing system power dissipation.The performing step of the method is: introduce a plurality of ahb bus, to to frequency of operation, require different peripheral hardwares to be connected on different ahb bus, each ahb bus different to clock frequency are connected by AHB-AHB bridge, to reduce the clock frequency of some low speed peripheral hardware, thereby reduce its dynamic power consumption; By APB bus, dynamically multi-clock gate register is read and write, controlled corresponding door controling clock signal, open the gated clock of the module that needs work, close the gated clock that does not need operational module.The weak point of the method is, need in system, introduce the steering logics such as extra ahb bus and AHB-AHB bridge and reduce or reduce the dynamic upset of clock when not working, when reducing system dynamic power consumption, introduce power consumption and the area that extra steering logic is brought.
The patented technology that Huawei Tech Co., Ltd has " a kind of implementation method of dynamic shared storage storage space " (application number: CN200510066582.4, notification number: disclose the implementation method that a kind of storer divides block access CN1855881).The performing step of the method is: the first, and the storage space of storer is divided into several memory partitionings, and distributes corresponding address pointer information for each memory partitioning; The second, when there is data storage requirement, dynamically for it distributes a data memory partitioning chain being comprised of based on described address pointer information one or more memory partitionings, and utilize described data memory partitioning chain to carry out the storage of data; The 3rd, the memory partitioning in described data memory partitioning chain during data, is released to the memory partitioning that can distribute to other data storage requirement without storage.The weak point of the method is, need to be additionally that memory partitioning distributes address pointer, thereby therefore the storage demand of each memory partitioning of dynamic assignment has introduced power consumption and the area that extra address pointer brings when reducing system power dissipation.
Summary of the invention
The object of the invention is to the deficiency for above-mentioned prior art, propose a kind of low power consumption optimization method of multiplication of decimals device.The method is based on canonic signed digit algorithm (CSD) and Huo Na algorithm (Horner Scheme), and two kinds of algorithms supplement and complement each other, and act on same multiplication of decimals device simultaneously.For the system that contains multiplication of decimals device, the present invention can significantly reduce its power consumption and area, does not introduce the logical block of algorithm self simultaneously.
To achieve these goals, technical scheme of the present invention is that optimization multiplication module is separated with system, only instantiation in system, and each multiplication of decimals device in replacement system.Inner in multiplication module, first the decimal coefficient being imported into by generic parameter is processed through integer; Next carries out canonic signed digit optimization, optimum results is represented with constant sequence, after comprehensive, multiplication module just can be converted into corresponding totalizer according to these constants, and algorithm logic itself can not introduced in multiplication module, it is the quantity that comprehensive rear multiplication module is converted into totalizer that canonic signed digit is optimized index; Again carry out Huo Na optimization, for totalizers at different levels according to canonic signed digit optimum results, default to subordinate's additive operation the position, addition results at the corresponding levels end without the contribution of any carry, thereby reduce addition results bit wides at different levels; Finally result of calculation decimation processed and kept obtaining final multiplication of decimals result after data width.
The present invention includes following steps:
(1) build multiplication module
With hardware description language, build multiplication module entity, comprise that one for inputting the generic parameter port of former multiplication of decimals device coefficient; Two for inputting the input port of multiplicand and data width; One for exporting the output port of final multiplication result.
(2) coefficient integer is processed
Inner in multiplication module, according to integer, process formula X=B (2
n-1), the multiplication of decimals coefficient of being inputted by module generic parameter is carried out to integer processing, wherein, X is bigit result; B is multiplication of decimals device coefficient; N is data width.
(3) canonic signed digit optimization
Following record and processing are searched for and done to bigit result by lowest order to n-1 position:
3a) meet " 1 " with two variablees, to record respectively its position and symbol;
3b) meet " 0 " to have before judging and there is no continuous " 1 ": if having, get this complement code of " 1 " continuously, maximum successive value in location variable is added to 1, the symbolic variable corresponding with it is for just, in location variable, minimum successive value remains unchanged, the symbolic variable corresponding with it, for negative, deleted location variable and corresponding symbolic variable between these two location variables, execution step 3a); If nothing, directly performs step 3a).
3c) search for to the n-1 position of integer result, all location variables and symbolic variable are formed respectively to position sequence and symbol sebolic addressing.
(4) extract optimum results
In two constant sequences of the inner definition of multiplication module, respectively by position sequence and symbol sebolic addressing assignment in these two constant sequences.
(5) Huo Na optimizes
Location constant sequence and notation constant sequence are multiplied each other, and result and multiplicand carry out Huo Na optimization, the Huo Na optimum results n-n that moves to right
kthe decimation of position is processed, and retains high n position as the net result of multiplication of decimals computing, by multiplication module output port, is exported.
(6) replace multiplication of decimals device
Multiplication module is replaced to each multiplication of decimals device in optimised system, and the generic parameter of multiplication module is set to multiplication of decimals device coefficient; The multiplicand input end of multiplication module is set to the input of multiplication of decimals device; The bit wide input end of multiplication module is set to multiplication of decimals device bit wide; The output terminal assignment of multiplication module is in multiplication of decimals device result.
The present invention compared with prior art tool has the following advantages:
The 1st, the implementation method that the multiplication of decimals device coefficient that the present invention adopts is imported into by the generic parameter of multiplication module, overcome the problem of added logic drawing-in system in prior art low power dissipation design, make multiplication module of the present invention inside only have optimum results to participate in generating totalizer, and the logical block of optimized algorithm self can not be incorporated into multiplier inside.For the system that contains extensive multiplying, avoid power consumption and the area accumulation of the algorithm logic that its inner each multiplier introduces to enter system;
The 2nd, the present invention is based on canonic signed digit algorithm and Huo Na algorithm, the former optimization index is the quantity that multiplier is converted into totalizer, the latter's optimization index is the register bit wide of additive operation result in the middle of deposit multiplier inside.Two kinds of algorithms act on same multiplication of decimals device simultaneously, have promoted the effect of optimization of single algorithm;
The 3rd, the present invention adopts the method that Huo Na optimizes after first canonic signed digit optimization, and the former can be utilized by the latter result of calculation, has saved the latter's amount of calculation, has improved whole design arithmetic speed and operation efficiency;
The 4th, the present invention only needs arrangement and the position of " 1 " in search multiplier coefficients and is recorded and process in calculating process, has travelling speed fast, takies resource few, simple advantage;
The 5th, the present invention can not reduce system works efficiency, not under the condition of loss system operational precision, significantly reduce system power dissipation and area.
Accompanying drawing explanation
Fig. 1 is process flow diagram of the present invention;
Fig. 2 is the vertical figure of multiplication after the processing of multiplication of decimals integer in the present invention;
Fig. 3 is the vertical figure of multiplication after canonic signed digit optimization in the present invention;
Fig. 4 is that in the present invention, Huo Na optimizes the vertical figure of multiplication.
Embodiment
With reference to Fig. 1, specific embodiment of the invention step is as follows:
Step 1, builds multiplication module
With hardware description language, build multiplication module entity, comprise that one for inputting the generic parameter port of former multiplication of decimals device coefficient; Two for inputting the input port of multiplicand and data width; One for exporting the output port of final multiplication result.
In the embodiment of the present invention, by VHDL language, build multiplication module entity, generic parameter port is g, and multiplicand input port is x_i, and data width input port is n, and output port is z_o.
Step 2, coefficient integer is processed
Inner in multiplication module, according to integer, process formula X=B (2
n-1), the multiplication of decimals coefficient of being inputted by module generic parameter is carried out to integer processing, wherein X is that bigit result, B are that multiplication of decimals device coefficient, n are data width.The maximum number that now data width n can give expression to is normalized to " 1 ", and decimal B is represented as shared ratio of being somebody's turn to do " normalization 1 ".
In the embodiment of the present invention, the decimal 119/255 of eight is treated to 119/255 (2 by integer
8-1)=119 (01110111
b), here 255 (11111111
b) be normalized to " 1 ".The multiplication that eight multiplications of decimals 153 * 119/255 carry out after integer processing is as shown in Figure 2 vertical.In figure, multiplicand 153 is shown 10011001 with binary form
b, multiplier is 01110111
b, this multiplying corotation turns to five totalizers, and first order addition results is 111001011
b, bit wide is 9; Second level addition results is 10000101111
b, bit wide is 11; Third level addition results is 110110111111
b, bit wide is 12; Fourth stage addition results is 10000011011111
b, bit wide is 14; Level V addition results is 100011100011111
b, bit wide is 15, eight final multiplication results after decimation is processed are 1000111.0
b.
Step 3, canonic signed digit optimization
Following record and processing are searched for and done to bigit result by lowest order to n-1 position: meet " 1 " with two variablees, to record respectively its position and symbol; Meet " 0 " to have before judging and there is no continuous " 1 ": if having, get the complement code of this continuous " 1 ", the maximum successive value in location variable is added to 1, the symbolic variable corresponding with it is for just; In location variable, minimum successive value remains unchanged, and the symbolic variable corresponding with it, for negative, deleted location variable and corresponding symbolic variable between these two location variables, then continues to a high position to search for; If nothing, directly searches for to a high position; Search for to the n-1 position of integer result, all location variables and symbolic variable are formed respectively to position sequence and symbol sebolic addressing.
In the embodiment of the present invention, the multiplication that eight multiplication of decimals 153 * 119/255 integer results in step 2 are carried out after canonic signed digit optimization is as shown in Figure 3 vertical.In figure, multiplicand 153 is shown 10011001 with binary form
b, multiplier is
wherein
represent-1.After optimization, this multiplying corotation turns to 2 totalizers, and first order addition results is-10101100001
b; Second level addition results is 100011100011111
b, than optimizing front totalizer quantity, reduce 3.
Step 4, extracts optimum results
In two constant sequences of the inner definition of multiplication module, respectively by the position sequence of step 3 and symbol sebolic addressing assignment in these two constant sequences.
Step 5, Huo Na optimizes
Location constant sequence and notation constant sequence are multiplied each other, and result is designated as (n
1, n
2..., n
k); First totalizer is by the multiplicand n that moves to left
lposition adds the multiplicand n that moves to left
2position forms, and the most end n of default addition results
2position is as first intermediate result; Second totalizer is by the multiplicand n that moves to left
3position adds first intermediate result and forms, and the most end n of default addition results
3position is as second intermediate result; I totalizer is by the multiplicand n that moves to left
i+1position adds i-1 intermediate result and forms, and the most end n of default addition results
i+1position is as i intermediate result; Until construct k-1 totalizer.
Because Huo Na optimized algorithm is the default position, end to the addition results at the corresponding levels of subordinate's addition no-carry contribution, thereby reduce the bit wide of addition results at different levels.Therefore inner in multiplication module, except default action, do not introduce any extra computing and logical block.
Owing in step 2, n position decimal coefficient B being multiplied by (2
n-1), be equivalent to the n position that moves to left by B, decimation processing is carried out in the result of the therefore final stage additive operation n position that need to move to right.Yet maximum default position is n in Huo Na optimizing process
k, n has moved to right in optimizing process
kposition, the n-n so the result of final stage totalizer only need move to right
kposition, and retain high n position as the net result of multiplication of decimals computing, by multiplication module output port, exported.
In the embodiment of the present invention, the canonic signed digit optimum results to eight multiplications of decimals 153 * 119/255 in step 3, the multiplication after Huo Na optimizes is as shown in Figure 4 vertical.In figure, multiplicand 153 is shown 10011001 with binary form
b, multiplier is
wherein
represent-1.After optimization, this multiplying corotation turns to 2 totalizers, and first order addition results is-10101100
b, bit wide is 8; Second level addition results is 10001110
b, bit wide is also 8, eight final multiplication results after decimation is processed are 1000111.0
b, with in full accord before optimization, addition results bit wide is saved (9+11+12+14+15)-(8+8)=45 altogether.
Step 6, replaces multiplication of decimals device
By each multiplication of decimals device in multiplication module replacement system, the generic parameter of multiplication module is set to multiplication of decimals device coefficient; The multiplicand input end of multiplication module is set to the input of multiplication of decimals device; The bit wide input end of multiplication module is set to multiplier bit wide; The output terminal assignment of multiplication module is in the result of multiplication of decimals device.
For the system that contains multiplier, once the parameter of system and characteristic are definite, its inner each multiplier coefficients also will be determined.And multiplier coefficients is imported into by generic parameter and the reason do not imported into constant parameter is, constant can only obtain assignment and can not change again from the inside of design entity, and the value of generic can be provided by design entity outside, so deviser can easily change the internal circuit configuration of this module from the outside by resetting of generic parameter.
In the embodiment of the present invention, adopt the Quartus II of ATERA company as synthesis tool, first create project guide, in the toolbar of QuartusII, click File-> New Project Wizard and choose multiplication module; Secondly in toolbar, click Processing-> Start Compilation, start omnidistance compiling; Finally in toolbar, click Tools-> Netlist Viewer-> RTL Viewer, check the comprehensive rear gate level circuit generating of multiplication module.At the comprehensive initial stage, the coefficient of multiplication of decimals device imports multiplication module into by generic parameter, obtain the canonic signed digit optimum results representing with constant sequence, after comprehensive according to these constants, multiplication module just can be converted into corresponding totalizer, Huo Na optimized algorithm is simultaneously for the default position, addition results at the corresponding levels end that subordinate's additive operation is contributed without any carry of totalizers at different levels, thus reduction register bit wide.At this moment canonic signed digit optimization logic itself can not enter in multiplication module, and the Huo Na algorithm of inside modules also only contains default action, can not introduce extra logical block and computing.
In order accurately to test effect of optimization of the present invention, using certain radio-frequency module that contains a large amount of digital filters and digital signal processing as optimised system.Testing tool is the Power Theater of Sequence Design company, and as standard power consumption calculation instrument, it can calculate power consumption and area accurately to the front end RTL code of system.Table 1 is radio-frequency module power consumption and area before optimizing with table 2; Power consumption and the area of table 3 and table 4 radio-frequency module after for the inventive method optimization.The power consumption of optimizing front module is 10.7mW, and logic unit numbers is 95962, and area is 1.479mm
2.After the inventive method is optimized, above parameter is respectively 7.94mW, 74915,1.412mm
2, reduce on year-on-year basis 25.79%, 21.93%, 4.53%.Effect of optimization is fairly obvious.
Table 1 is optimized front radio-frequency module power consumption
Table 2 is optimized front radio-frequency module logic unit numbers and area
The power consumption of the radio-frequency module that table 3 was optimized through the present invention
The logic unit numbers of the radio-frequency module that table 4 was optimized through the present invention and area
In order further to test hardware optimization effect of the present invention, respectively the radio-frequency module before and after optimizing is carried out to FPGA test, test adopts the Stratix IV EP4SE820F43C3 of family model FPGA as test platform, adopts Quartus II as compiling, the synthesis tool of FPGA.Radio-frequency module optimize the resource report accurate recording that generates after the omnidistance compiling of anteroposterior diameter Quartus II in twice test tested object for the occupation condition of this model FPGA.Before optimizing, radio-frequency module is 5.6% to the logic occupancy of this FPGA, generates register and adds up to 18175, and storage unit occupancy is 6.5%; The radio-frequency module of optimizing through the present invention is 3.8% to the logic occupancy of this FPGA, generates register and adds up to 12164, and storage unit occupancy is 4.2%.By FPGA test result, contrast, the shared hardware resource of the latter reduces by 32.14%, 33.07%, 35.38% than the former, and effect of optimization is remarkable.
Claims (2)
1. a low power consumption optimization method for decimal multiplier in integrated circuit system, comprises the following steps:
(1) build multiplication module
With hardware description language, build multiplication module entity, comprise that one for inputting the generic parameter port of former multiplication of decimals device coefficient; Two for inputting the input port of multiplicand and data width; One for exporting the output port of final multiplication result;
(2) coefficient integer is processed
Inner in multiplication module, according to integer, process formula X=B (2
n-1), the multiplication of decimals coefficient of being inputted by module generic parameter is carried out to integer processing, wherein, X is bigit result; B is multiplication of decimals device coefficient; N is data width;
(3) canonic signed digit optimization
Following record and processing are searched for and done to bigit result by lowest order to n-1 position:
3a) meet " 1 " with two variablees, to record respectively its position and symbol;
3b) meet " 0 " to have before judging and there is no continuous " 1 ": if having, get this complement code of " 1 " continuously, maximum successive value in location variable is added to 1, the symbolic variable corresponding with it is for just, in location variable, minimum successive value remains unchanged, the symbolic variable corresponding with it, for negative, deleted location variable and corresponding symbolic variable between these two location variables, execution step 3a); If nothing, directly performs step 3a);
3c) search for to the n-1 position of integer result, all location variables and symbolic variable are formed respectively to position sequence and symbol sebolic addressing;
(4) extract optimum results
In two constant sequences of the inner definition of multiplication module, respectively by position sequence and symbol sebolic addressing assignment in these two constant sequences;
(5) Huo Na optimizes
Location constant sequence and notation constant sequence are multiplied each other, and result and multiplicand carry out Huo Na optimization, the Huo Na optimum results n-n that moves to right
kthe decimation of position is processed, and retains high n position as the net result of multiplication of decimals computing, by multiplication module output port, is exported; The step of described Huo Na optimization method is, the result that location constant sequence and notation constant sequence are multiplied each other is designated as (n
1, n
2..., n
k); First totalizer is by the multiplicand n that moves to left
1position adds the multiplicand n that moves to left
2position forms, the most end n of default addition results
2position after as first intermediate result; Second totalizer is by the multiplicand n that moves to left
3position adds first intermediate result and forms, the most end n of default addition results
3position after as second intermediate result; I totalizer is by the multiplicand n that moves to left
i+1position adds i-1 intermediate result and forms, the most end n of default addition results
i+1position after as i intermediate result; Until construct k-1 totalizer;
(6) replace multiplication of decimals device
Multiplication module is replaced to each multiplication of decimals device in optimised system, and the generic parameter of multiplication module is set to multiplication of decimals device coefficient; The multiplicand input end of multiplication module is set to the input of multiplication of decimals device; The bit wide input end of multiplication module is set to multiplication of decimals device bit wide; The output terminal assignment of multiplication module is in multiplication of decimals device result.
2. the low power consumption optimization method of decimal multiplier in integrated circuit system according to claim 1, is characterized in that, the hardware description language described in step (1) is VHDL language.
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| CN107908389A (en) * | 2017-11-21 | 2018-04-13 | 天津大学 | Small point FFT twiddle factor complex multiplication accelerators |
| CN110378478B (en) * | 2019-08-30 | 2023-09-08 | 上海寒武纪信息科技有限公司 | Multiplier, data processing method, chip and electronic equipment |
| CN110362293B (en) * | 2019-08-30 | 2023-12-19 | 上海寒武纪信息科技有限公司 | Multiplier, data processing method, chip and electronic equipment |
| CN110378477B (en) * | 2019-08-30 | 2023-09-08 | 上海寒武纪信息科技有限公司 | Multiplier, data processing method, chip and electronic equipment |
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| CN1454347A (en) * | 2000-10-16 | 2003-11-05 | 诺基亚公司 | Multiplier and shift device using signed digit representation |
| CN101156130A (en) * | 2005-03-31 | 2008-04-02 | Nxp股份有限公司 | Canonical signed digit multiplier |
| CN101425794A (en) * | 2008-11-27 | 2009-05-06 | 四川虹微技术有限公司 | Digital filter with fixed coefficient |
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|---|---|---|---|---|
| EP0292189A2 (en) * | 1987-05-18 | 1988-11-23 | Advanced Micro Devices, Inc. | Updating cannonic signed digit filter coefficients |
| CN1454347A (en) * | 2000-10-16 | 2003-11-05 | 诺基亚公司 | Multiplier and shift device using signed digit representation |
| CN101156130A (en) * | 2005-03-31 | 2008-04-02 | Nxp股份有限公司 | Canonical signed digit multiplier |
| CN101425794A (en) * | 2008-11-27 | 2009-05-06 | 四川虹微技术有限公司 | Digital filter with fixed coefficient |
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