CN102303842A - Pre-packaging method of cover plate compatible with semiconductor process - Google Patents
Pre-packaging method of cover plate compatible with semiconductor process Download PDFInfo
- Publication number
- CN102303842A CN102303842A CN201110232587A CN201110232587A CN102303842A CN 102303842 A CN102303842 A CN 102303842A CN 201110232587 A CN201110232587 A CN 201110232587A CN 201110232587 A CN201110232587 A CN 201110232587A CN 102303842 A CN102303842 A CN 102303842A
- Authority
- CN
- China
- Prior art keywords
- cover plate
- packaged
- barrier layer
- etching
- area
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Micromachines (AREA)
Abstract
The invention provides a pre-packaging method of a cover plate compatible with a semiconductor process. The method comprises the following steps: providing an apparatus substrate on which a first region required for sealing and a second region required for exposing to an external environment are divided; providing a pre-packaging cover plate, respectively forming a barrier layer on both the frontage and the back; etching the barrier layer on the back to form a plurality of back windows corresponding to the first and second regions on the apparatus substrate; etching the pre-packaging cover plate from the plurality of back windows to form a plurality of back cavities; etching the barrier layer on the frontage to form a plurality of frontage windows corresponding to the second region on the apparatus substrate; etching the pre-packaging cover plate from the plurality of frontage cavities to form a plurality of frontage cavities, wherein only a thin layer is between the frontage cavity bottom and the back cavity bottom; removing the barrier layer on the pre-packaging cover plate; bonding the pre-packaging cover plate and the apparatus substrate; and carving through the thin layer to expose the second region on the apparatus substrate to the external environment. The pre-packing method can meet the different package requirements on the same chip simultaneously.
Description
Technical field
The present invention relates to the semiconductor processing technology field, specifically, the present invention relates to a kind of cover plate pre-packaged method compatible with semiconductor technology.
Background technology
In MEMS (MEMS) application, increasing sensor and actuator are integrated on the same chip to improve performance.Some need realize airtight protection with external environment is isolated these devices, and some need directly contact with outer survey environment and obtain detectable signal.Packaged type form commonly used at present is more single, or with device sealing or outside being exposed to, can not take into account these two kinds different encapsulation requirements simultaneously.
Therefore, need the pre-packaged method of a kind of novel cover plate of exploitation, to adapt to encapsulation requirements different on the same chip.
Summary of the invention
Technical problem to be solved by this invention provides a kind of cover plate pre-packaged method compatible with semiconductor technology, to satisfy encapsulation requirements different on the same chip.
For solving the problems of the technologies described above, the present invention provides a kind of cover plate pre-packaged method compatible with semiconductor technology, comprises step:
Device substrate is provided, and dividing on it has the first area that needs sealing and need be exposed to the outer second area of surveying environment;
Pre-packaged cover plate is provided, forms the barrier layer respectively at its front and back;
The barrier layer at the said pre-packaged cover plate of the etching back side forms a plurality of back sides window, and the size of a plurality of said back sides window is corresponding with first area and second area on the said device substrate with the position;
With said barrier layer is mask, and the said pre-packaged cover plate of etching from the window of a plurality of said back sides forms a plurality of backside cavity in said pre-packaged cover plate;
The positive barrier layer of the said pre-packaged cover plate of etching forms a plurality of front window, and the size of a plurality of said front window is corresponding with the second area on the said device substrate with the position;
With said barrier layer is mask, and the said pre-packaged cover plate of etching from a plurality of said front window forms a plurality of fronts cavity in said pre-packaged cover plate, is separated with thin layer between only between the bottom of a plurality of said fronts cavity and the bottom of a plurality of said backside cavity;
Adopt the wet etching method to remove the barrier layer that said pre-packaged cover plate front and back forms;
Said pre-packaged cover plate and said device substrate are bonded together, and said pre-packaged cover plate all seals first area on the said device substrate and second area;
Adopt the dry etching method to carve and wear said thin layer, the second area on the said device substrate is exposed to the outer environment of surveying.
Alternatively, said pre-packaged cover plate is silicon, germanium, GaAs, pottery, glass, metal or organic material.
Alternatively, said barrier layer is one deck or multilayer stack.
Alternatively, said barrier layer is a passivating material.
Alternatively, said barrier layer is silica and/or silicon nitride.
Alternatively, the technology of a plurality of backside cavity of formation or front cavity is dry etching or wet etching in said pre-packaged cover plate.
Alternatively, adopt binder that said pre-packaged cover plate and said device substrate are bonded together.
Compared with prior art, the present invention has the following advantages:
The present invention adopts etching technics, on pre-packaged cover plate, forms cavity and through hole respectively, adopts bonding technology with pre-packaged cover plate and device substrate bonding.To need the zone of seal protection to be isolated from the outside, and the zone passage through hole that will obtain the external environment signal be communicated with, and on same chip, satisfies different encapsulation requirements simultaneously with the outer environment facies of surveying.
The present invention can also adapt to different chip encapsulation requirements through the distributing position of regulating pre-packaged cover plate upper plenum and through hole.This simple and reliable process, applicability are strong, can be widely used in semiconductor packages and other encapsulation field.
Description of drawings
The above and other features of the present invention, character and advantage will become more obvious through the description below in conjunction with accompanying drawing and embodiment, wherein:
Fig. 1 is flow chart one embodiment of the invention and the pre-packaged method of the cover plate semiconductor technology compatibility;
Fig. 2 to Figure 10 is cross-sectional view one embodiment of the invention and the pre-packaged process of the cover plate semiconductor technology compatibility.
The specific embodiment
Below in conjunction with specific embodiment and accompanying drawing the present invention is described further; Set forth more details in the following description so that make much of the present invention; But the present invention obviously can implement with multiple this description ground alternate manner that is different from; Those skilled in the art can do similar popularization, deduction according to practical situations under the situation of intension of the present invention, therefore should be with content constraints protection scope of the present invention of this specific embodiment.
Fig. 1 is flow chart one embodiment of the invention and the pre-packaged method of the cover plate semiconductor technology compatibility.As shown in the figure, the pre-packaged method of this cover plate can comprise step:
Execution in step S101 provides device substrate, and dividing on it has the first area that needs sealing and need be exposed to the outer second area of surveying environment;
Execution in step S102 provides pre-packaged cover plate, forms the barrier layer respectively at its front and back;
Execution in step S103, the barrier layer at the pre-packaged cover plate of the etching back side forms a plurality of back sides window, and the size of a plurality of back sides window is corresponding with first area and second area on the device substrate with the position;
Execution in step S104 is a mask with the barrier layer, and the pre-packaged cover plate of etching from the window of a plurality of back sides forms a plurality of backside cavity in pre-packaged cover plate;
Execution in step S105, the positive barrier layer of the pre-packaged cover plate of etching forms a plurality of front window, and the size of a plurality of front window is corresponding with the second area on the device substrate with the position;
Execution in step S106 is a mask with the barrier layer, and the pre-packaged cover plate of etching from a plurality of front window forms a plurality of fronts cavity in pre-packaged cover plate, is separated with thin layer between only between the bottom of a plurality of fronts cavity and the bottom of a plurality of backside cavity;
Execution in step S107 adopts the wet etching method to remove the barrier layer that pre-packaged cover plate front and back forms;
Execution in step S108 is bonded together pre-packaged cover plate and device substrate, and pre-packaged cover plate all seals first area on the device substrate and second area;
Execution in step S109 adopts the dry etching method to carve and wears thin layer, and the second area on the device substrate is exposed to the outer environment of surveying.
Fig. 2 to Figure 10 is cross-sectional view one embodiment of the invention and the pre-packaged process of the cover plate semiconductor technology compatibility.It should be noted that these and follow-up other accompanying drawing all only as an example, it is not to be to draw according to the condition of equal proportion, and should not limit as the protection domain formation to the actual requirement of the present invention with this.
As shown in Figure 2, device substrate 101 is provided, dividing on it has the first area 102 that needs sealing and need be exposed to the outer second area 103 of surveying environment.
As shown in Figure 3, pre-packaged cover plate 104 is provided, this pre-packaged cover plate 104 can also can be pottery, glass, metal or organic material for semi-conducting materials such as silicon, germanium and GaAs.
As shown in Figure 4, form barrier layer 105 respectively at pre-packaged cover plate 104 front and backs.This barrier layer 105 can be one deck or multilayer stack, and material can be selected passivating material for use.For example, be silicon materials for pre-packaged cover plate 104, then barrier layer 105 can be silica, silicon nitride or silica (SiO
2) and silicon nitride (Si
3N
4) range upon range of.
Then the barrier layer 105 at the pre-packaged cover plate of etching 104 back sides forms a plurality of back sides window, and the size of a plurality of back sides window is corresponding with second area 103 with the first area 102 on the device substrate 101 of treating bonding with the position.
As shown in Figure 5, be mask with barrier layer 105, the pre-packaged cover plate 104 of etching from the window of a plurality of back sides forms a plurality of backside cavity 106 in pre-packaged cover plate 104.This etching technics can be that dry etching can be a wet etching also, and is not limited to a certain etching agent.When pre-packaged cover plate 104 thickness are big, can select wet etching; And when pre-packaged cover plate 104 thinner thicknesses, also can select dry etching.Those skilled in the art can select suitable technology according to concrete technology difficulty and technology cost.
As shown in Figure 6, the barrier layer 105 in the pre-packaged cover plate of etching 104 fronts forms a plurality of front window, and the quantity of a plurality of front window, size and position are corresponding with the second area 103 on the device substrate 101.If adopt wet etching to leave front window, just need be to the backsizing protection of pre-packaged cover plate 104; But when barrier layer 105 thickness are not too thick, also can adopt dry etching to leave front window.
As shown in Figure 7, be mask with barrier layer 105, the pre-packaged cover plate 104 of etching from a plurality of front window forms a plurality of fronts cavity 107 in pre-packaged cover plate 104.This etching technics can be that dry etching can be a wet etching also, and is not limited to a certain etching agent.When pre-packaged cover plate 104 thickness are big, can select wet etching; And when pre-packaged cover plate 104 thinner thicknesses, also can select dry etching.Those skilled in the art can select suitable technology according to concrete technology difficulty and technology cost.In addition, front cavity 107 is vertically relative with the position of some backside cavity 106, is separated with thin layer 108 between only between the bottom of a plurality of fronts cavity 107 and the bottom of a plurality of backside cavity 106.
As shown in Figure 8, adopt wet etching method for example to remove the barrier layer 105 that pre-packaged cover plate 104 front and backs form.So far, pre-packaged cover plate 104 is accomplished basically.
As shown in Figure 9, pre-packaged cover plate 104 is bonded together with device substrate 101, pre-packaged cover plate 104 all seals first area on the device substrate 101 102 and second area 103.
In the present embodiment, can adopt binder auxiliary at high temperature with pre-packaged cover plate 104 and device substrate 101 completion bondings.But the invention is not restricted to this, the bonding technology that can also adopt other not need binder directly to accomplish.
As shown in figure 10, for example adopt the dry etching method to carve at last and wear thin layer 108, the second area on the device substrate 101 103 is exposed to the outer environment of surveying.At this moment, 102 of the first areas on the device substrate 101 are sealed in the backside cavity 106.
It is pointed out that the present invention need airtight protection and be exposed to the outer zone of surveying environment can be device substrate in whole or in part, also can be that some that in technical process, stay need vestiges of further handling.Such as adopting electroplating technology will produce protruding figure at the alignment mark place; Must remove this protrusion through a step process and just can carry out conventional bonding; If just can save a step process Direct Bonding but adopt the present invention that this protruding figure is classified as airtight protection zone, reduce cost.
The present invention adopts etching technics, on pre-packaged cover plate, forms cavity and through hole respectively, adopts bonding technology with pre-packaged cover plate and device substrate bonding.To need the zone of seal protection to be isolated from the outside, and the zone passage through hole that will obtain the external environment signal be communicated with, and on same chip, satisfies different encapsulation requirements simultaneously with the outer environment facies of surveying.
The present invention can also adapt to different chip encapsulation requirements through the distributing position of regulating pre-packaged cover plate upper plenum and through hole.This simple and reliable process, applicability are strong, can be widely used in semiconductor packages and other encapsulation field.
Though the present invention with preferred embodiment openly as above, it is not to be used for limiting the present invention, and any those skilled in the art are not breaking away from the spirit and scope of the present invention, can make possible change and modification.Therefore, every content that does not break away from technical scheme of the present invention, according to technical spirit of the present invention to any modification, equivalent variations and modification that above embodiment did, within the protection domain that all falls into claim of the present invention and defined.
Claims (7)
1. cover plate pre-packaged method compatible with semiconductor technology comprises step:
Device substrate (101) is provided, and dividing on it has the first area (102) that needs sealing and need be exposed to the outer second area (103) of surveying environment;
Pre-packaged cover plate (104) is provided, forms barrier layer (105) respectively at its front and back;
The barrier layer (105) at the said pre-packaged cover plate of etching (104) back side forms a plurality of back sides window, and the size of a plurality of said back sides window is corresponding with first area (102) and second area (103) on the said device substrate (101) with the position;
With said barrier layer (105) is mask, and the said pre-packaged cover plate of etching (104) from the window of a plurality of said back sides forms a plurality of backside cavity (106) in said pre-packaged cover plate (104);
The barrier layer (105) that the said pre-packaged cover plate of etching (104) is positive forms a plurality of front window, and the size of a plurality of said front window is corresponding with the second area (103) on the said device substrate (101) with the position;
With said barrier layer (105) is mask; The said pre-packaged cover plate of etching (104) from a plurality of said front window; In said pre-packaged cover plate (104), form a plurality of fronts cavitys (107), be separated with thin layer (108) between only between the bottom of the bottom of a plurality of said front cavitys (107) and a plurality of said backside cavity (106);
Adopt the wet etching method to remove the barrier layer (105) that said pre-packaged cover plate (104) front and back forms;
Said pre-packaged cover plate (104) and said device substrate (101) are bonded together, and said pre-packaged cover plate (104) is with the first area (102) on the said device substrate (101) and all sealings of second area (103);
Adopt the dry etching method to carve and wear said thin layer (108), the second area (103) on the said device substrate (101) is exposed to the outer environment of surveying.
2. the pre-packaged method of cover plate according to claim 1 is characterized in that said pre-packaged cover plate (104) is silicon, germanium, GaAs, pottery, glass, metal or organic material.
3. the pre-packaged method of cover plate according to claim 2 is characterized in that, said barrier layer (105) are one deck or multilayer stack.
4. the pre-packaged method of cover plate according to claim 3 is characterized in that said barrier layer (105) are passivating material.
5. the pre-packaged method of cover plate according to claim 4 is characterized in that said barrier layer (105) are silica and/or silicon nitride.
6. the pre-packaged method of cover plate according to claim 5 is characterized in that, the technology that in said pre-packaged cover plate (104), forms a plurality of backside cavity (106) or front cavity (107) is dry etching or wet etching.
7. the pre-packaged method of cover plate according to claim 6 is characterized in that, adopts binder that said pre-packaged cover plate (104) and said device substrate (101) are bonded together.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110232587A CN102303842A (en) | 2011-08-15 | 2011-08-15 | Pre-packaging method of cover plate compatible with semiconductor process |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110232587A CN102303842A (en) | 2011-08-15 | 2011-08-15 | Pre-packaging method of cover plate compatible with semiconductor process |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102303842A true CN102303842A (en) | 2012-01-04 |
Family
ID=45377786
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110232587A Pending CN102303842A (en) | 2011-08-15 | 2011-08-15 | Pre-packaging method of cover plate compatible with semiconductor process |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102303842A (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1108677A1 (en) * | 1999-12-15 | 2001-06-20 | Asulab S.A. | Method of hermetic In Situ encapsulation of microsystems |
| DE19962431A1 (en) * | 1999-12-22 | 2001-07-19 | Micronas Gmbh | Method of manufacturing a semiconductor device |
| CN1576229A (en) * | 2003-07-15 | 2005-02-09 | 惠普开发有限公司 | Fluidic mems device |
| CN1792764A (en) * | 2005-10-27 | 2006-06-28 | 中国科学院上海微***与信息技术研究所 | Disc grade packing tech. for micro mechanical acceleration counter |
| CN101780942A (en) * | 2009-12-11 | 2010-07-21 | 中国电子科技集团公司第十三研究所 | Wafer level vacuum packaging method of MEMS (Micro-electromechanical System) component |
| CN102105389A (en) * | 2008-05-28 | 2011-06-22 | Nxp股份有限公司 | MEMS devices |
-
2011
- 2011-08-15 CN CN201110232587A patent/CN102303842A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1108677A1 (en) * | 1999-12-15 | 2001-06-20 | Asulab S.A. | Method of hermetic In Situ encapsulation of microsystems |
| DE19962431A1 (en) * | 1999-12-22 | 2001-07-19 | Micronas Gmbh | Method of manufacturing a semiconductor device |
| CN1576229A (en) * | 2003-07-15 | 2005-02-09 | 惠普开发有限公司 | Fluidic mems device |
| CN1792764A (en) * | 2005-10-27 | 2006-06-28 | 中国科学院上海微***与信息技术研究所 | Disc grade packing tech. for micro mechanical acceleration counter |
| CN102105389A (en) * | 2008-05-28 | 2011-06-22 | Nxp股份有限公司 | MEMS devices |
| CN101780942A (en) * | 2009-12-11 | 2010-07-21 | 中国电子科技集团公司第十三研究所 | Wafer level vacuum packaging method of MEMS (Micro-electromechanical System) component |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104303262B (en) | For the technique of a portion exposure sealing MEMS device at ambient | |
| JP4708366B2 (en) | Wafer packaging and singulation method | |
| EP1167281A3 (en) | Chip scale surface-mountable packaging method for electronic and MEMS devices | |
| CN102774805B (en) | Wafer encapsulation body and forming method thereof | |
| CN102820264A (en) | Chip package structure and manufacturing method thereof | |
| US20140353772A1 (en) | Microelectronic packages including patterned die attach material and methods for the fabrication thereof | |
| CN103964368A (en) | Mems Device And Method Of Manufacturing A Mems Device | |
| WO2010090798A3 (en) | Substrate bonding with metal germanium silicon material | |
| US9714166B2 (en) | Thin film structure for hermetic sealing | |
| TW200910435A (en) | Method of wafer-level segmenting capable of protecting contact pad | |
| CN104377163A (en) | CMOS compatible wafer bonding layer and process | |
| CN106098717A (en) | high reliability chip packaging method and structure | |
| TW201515240A (en) | Inertial and pressure sensors on single chip | |
| US7655539B2 (en) | Dice by grind for back surface metallized dies | |
| CN101962166B (en) | Packaging structure and packaging method | |
| CN104966676B (en) | eutectic bonding method | |
| US9209047B1 (en) | Method of producing encapsulated IC devices on a wafer | |
| JP2005019966A5 (en) | ||
| CN204424242U (en) | The chip package structure of belt edge buffering and wafer level chip encapsulating structure | |
| CN206767639U (en) | Integrated-semiconductor device | |
| CN103435000B (en) | The wafer-level packaging method of the sensor of integrated MEMS device | |
| CN102339916B (en) | Bonding method and packaging method for light-emitting diode (LED) chip and silicon substrate | |
| CN102259829A (en) | Isolation cavity and manufacturing method thereof | |
| CN102190281A (en) | Chip package and method for forming the same | |
| CN102303842A (en) | Pre-packaging method of cover plate compatible with semiconductor process |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20120104 |