CN102300377A - Timing power output reduction ballast of auto-excitation-type low-frequency ball bulb electrodeless lamp - Google Patents
Timing power output reduction ballast of auto-excitation-type low-frequency ball bulb electrodeless lamp Download PDFInfo
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- CN102300377A CN102300377A CN201110170219A CN201110170219A CN102300377A CN 102300377 A CN102300377 A CN 102300377A CN 201110170219 A CN201110170219 A CN 201110170219A CN 201110170219 A CN201110170219 A CN 201110170219A CN 102300377 A CN102300377 A CN 102300377A
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Abstract
The invention discloses a timing power output reduction ballast of an auto-excitation-type low-frequency ball bulb electrodeless lamp, and relates to the ballast, wherein the ballast comprises a timing power regulating control circuit (1), a rectifier circuit (2), an EMI (electro magnetic interference) circuit (3), a power correction PFC (power factor correction) circuit (4), a driving circuit (5) and a lamp connecting coupler (J1); the timing power regulating control circuit (1) is respectively connected with the rectifier circuit (2) and the power correction PFC circuit (4); the rectifier circuit (2) is respectively connected with the EMI circuit (3) and the power correction PFC circuit (4); and the power correction PFC circuit (4), the driving circuit (5) and the lamp connecting coupler (J1) are sequentially connected. According to the invention, the normal operation of the ballast can be ensured, power reduction output can be realized stably, and not only are energy sources saved, but also the service life of a power supply is prolonged.
Description
Technical field:
The present invention relates to a kind of ballast, relate in particular to a kind of auto-excitation type low frequency ball and steep electrodeless lamp and regularly fall power output ballast.
Background technology:
Traditional low frequency steeps electrodeless lamp high temperature, cold starting performance is poor, the operating frequency of circuit is fixed, can not change the starting frequency automatically, make starting performance poor, and its timed power-regulation control circuit delay time is immutable, the power consumption height, regularly not accurate enough, poor stability can not guarantee the rectifier operate as normal, make power failure rate height, the life-span shortens.
Summary of the invention:
The purpose of this invention is to provide a kind of auto-excitation type low frequency ball and steep electrodeless lamp and regularly fall power output ballast, it can guarantee the ballast operate as normal, can stably realize falling power output again, and both energy savings increased power source life again.
In order to solve the existing problem of background technology, the present invention is by the following technical solutions: it comprises timed power-regulation control circuit 1, rectification circuit 2, EMI circuit 3, capability correction pfc circuit 4, drive circuit 5 and meets lamp coupler J1, timed power-regulation control circuit 1 links to each other with rectification circuit 2, capability correction pfc circuit 4 respectively, rectification circuit 2 links to each other with EMI circuit 3, capability correction pfc circuit 4 respectively, capability correction pfc circuit 4, drive circuit 5 and meet lamp coupler J1 and link to each other successively.
Described timed power-regulation control circuit 1 comprises chip U1, chip U2, voltage stabilizing didoe WD1-WD2, diode D1-D3, capacitor C 1-C6, resistance R 1-R3 and inductance L 1,1 pin of chip U1,2 pin, 3 pin all link to each other with capability correction pfc circuit 4 with rectification circuit 2 with 4 pin, 5 pin of chip U1 and voltage stabilizing didoe WD1 negative pole, capacitor C 2 one ends link to each other with diode D1 negative pole, voltage stabilizing didoe WD1 positive pole links to each other with 6 pin of capacitor C 1 one ends and chip U1,7 pin of chip U1 and 8 pin all with capacitor C 1 other end, capacitor C 2 other ends, inductance L 1 one ends, diode D2 negative pole links to each other, diode D2 plus earth, inductance L 1 other end and diode D1 positive pole, capacitor C 3 positive poles, resistance R 1 one ends, capacitor C 4 one ends, resistance R 2 one ends link to each other, capacitor C 3 negative poles, resistance R 1 other end, the equal ground connection of capacitor C 4 other ends, resistance R 2 other ends link to each other with 2 pin of chip U2,2 pin of chip U2 respectively with capacitor C 6 one ends, capacitor C 5 positive poles, voltage stabilizing didoe WD2 negative pole, resistance R 3 one ends link to each other, capacitor C 6 other ends, capacitor C 5 negative poles, the anodal all ground connection of voltage stabilizing didoe WD2,1 pin of chip U2 and diode D3 positive pole, resistance R 3 other ends link to each other, the 4 pin ground connection of chip U2, diode D3 negative pole links to each other with capability correction pfc circuit 4.
Described rectification circuit 2 adopts bridge rectifier diode ZD1.
Described EMI circuit 3 comprises capacitor C 7-C11, transformer T3, transformer T5, thermistor RT1, fuse F1 and coupler J2, capacitor C 7 one ends link to each other with 1 pin of bridge rectifier diode ZD1 and 1 pin of transformer T5 respectively, capacitor C 7 other ends link to each other with 2 pin of bridge rectifier diode ZD1 and 2 pin of transformer T5 respectively, 3 pin of transformer T5 respectively with capacitor C 8 one ends, 1 pin of capacitor C 10 1 ends and transformer T3 links to each other, capacitor C 8 another termination level, capacitor C 10 other ends and capacitor C 11 1 ends, 4 pin of transformer T5,2 pin of transformer T3 link to each other, capacitor C 11 another termination level, 3 pin of transformer T3 respectively with capacitor C 9 one ends, thermistor RT1 one end, fuse F1 one end links to each other, 4 pin of transformer T3 respectively with capacitor C 9 other ends, the thermistor RT1 other end, 1 pin of coupler J2 links to each other, the fuse F1 other end links to each other with 3 pin of coupler J2, and 2 pin of coupler J2 connect level.
Described capability correction pfc circuit 4 comprises resistance R 4-R17, capacitor C 12-C18, chip U3, voltage stabilizing didoe WD3, diode D4-D5, metal-oxide-semiconductor Q6 and transformer T4, capacitor C 12 1 ends, resistance R 8 one ends, resistance R 9 one ends, 1 pin of transformer T4 all links to each other with 1 pin of bridge rectifier diode ZD1, capacitor C 12 other end ground connection, resistance R 8 other ends respectively with resistance R 4 one ends, capacitor C 14 1 ends, 3 pin of chip U3 link to each other, resistance R 4 other ends, capacitor C 14 other end ground connection, resistance R 9 other ends link to each other with 5 pin of chip U3,2 pin of chip U3 link to each other with capacitor C 15 1 ends, capacitor C 15 other end ground connection, 1 pin of chip U3 respectively with capacitor C 13 1 ends, resistance R 6 one ends, diode D3 negative pole in resistance R 7 one ends and the timed power-regulation control circuit 1 links to each other, capacitor C 13 other end ground connection, resistance R 6 other ends link to each other with resistance R 5 one ends, resistance R 5 other end ground connection, resistance R 7 other ends link to each other with resistance R 10 1 ends, resistance R 10 other ends and diode D5 negative pole, 17 anodal linking to each other of capacitor C, capacitor C 17 is in parallel with resistance R 16, capacitor C 17 negative poles and capacitor C 18 positive poles, resistance R 17 1 ends link to each other, capacitor C 18 negative poles, the equal ground connection of resistance R 17 other ends, 4 pin of chip U3 link to each other with resistance R 15 1 ends, resistance R 15 other ends link to each other with 2 pin and resistance R 14 1 ends of metal-oxide-semiconductor Q6 respectively, resistance R 14 other end ground connection, 1 pin of metal-oxide-semiconductor Q6 links to each other with resistance R 13 1 ends, resistance R 13 other ends link to each other with 6 pin of chip U3, the 7 pin ground connection of chip U3,3 pin of metal-oxide-semiconductor Q6 and diode D5 positive pole, 3 pin of transformer T4 link to each other, the 4 pin ground connection of transformer T4,2 pin of transformer T4 respectively with resistance R 11 1 ends, resistance R 12 1 ends link to each other, resistance R 12 other ends link to each other with 8 pin of chip U3, resistance R 11 other ends link to each other with diode D4 is anodal, diode D4 negative pole respectively with voltage stabilizing didoe WD3 negative pole, capacitor C 16 is anodal continuous, voltage stabilizing didoe WD3 positive pole, the equal ground connection of capacitor C 16 negative poles.
Described drive circuit 5 comprises starting circuit MK1, resistance R 18-R22, voltage stabilizing didoe WD4-WD8, metal-oxide-semiconductor Q1, metal-oxide-semiconductor Q4, transformer T1, thyristor Q2, diode D6 and inductance L 2,4 pin of starting circuit MK1,1 pin of metal-oxide-semiconductor Q4 all links to each other with resistance R 16 1 ends in the capability correction pfc circuit 4,3 pin of starting circuit MK1 link to each other with resistance R 18 1 ends with 5 pin, resistance R 18 other ends respectively with voltage stabilizing didoe WD4 positive pole, 3 pin of metal-oxide-semiconductor Q4 link to each other, voltage stabilizing didoe WD4 negative pole links to each other with voltage stabilizing didoe WD5 negative pole, 2 pin and 6 pin of voltage stabilizing didoe WD5 positive pole and starting circuit MK1,1 pin of transformer T2,2 pin of metal-oxide-semiconductor Q4 link to each other with 1 pin of metal-oxide-semiconductor Q1, the 1 pin ground connection of starting circuit MK1, link to each other respectively, 3 pin of metal-oxide-semiconductor Q1 respectively with inductance L 2 one ends, voltage stabilizing didoe WD7 positive pole, thyristor Q2 anode, resistance R 19 1 ends link to each other, resistance R 19 other ends link to each other with 3 pin of transformer T1, voltage stabilizing didoe WD7 negative pole links to each other with voltage stabilizing didoe WD6 negative pole, 2 pin of metal-oxide-semiconductor Q1, inductance L 2 other ends, voltage stabilizing didoe WD6 positive pole, the equal ground connection of 2 pin of thyristor Q2 negative electrode and transformer T1,4 pin of transformer T1 link to each other with capacitor C 19 1 ends, capacitor C 19 another termination level, 1 pin of transformer T1 links to each other with capacitor C 24 1 ends, capacitor C 24 other ends link to each other with capacitor C 23 1 ends, capacitor C 23 other ends respectively with 3 pin of transformer T2, capacitor C 25 1 ends, resistance R 22 1 ends, capacitor C 26 1 ends link to each other, resistance R 22 other ends, capacitor C 25 other ends all link to each other with 1 pin that meets lamp coupler J1, capacitor C 26 other ends link to each other with capacitor C 27 1 ends, capacitor C 27 other end ground connection, the 4 pin ground connection of transformer T2,2 pin of transformer T2 link to each other with diode D6 is anodal, diode D6 negative pole respectively with resistance R 20 1 ends, resistance R 21 1 ends link to each other, resistance R 20 other end ground connection, resistance R 21 other ends respectively with voltage stabilizing didoe WD8 negative pole, capacitor C 22 positive poles, capacitor C 21 1 ends link to each other, capacitor C 22 negative poles, the equal ground connection of capacitor C 21 other ends, voltage stabilizing didoe WD8 positive pole respectively with capacitor C 20 1 ends, the controlled end of thyristor Q2 links to each other, capacitor C 20 other end ground connection, capacitor C 28 1 ends, connect the equal ground connection of 2 pin of lamp coupler J1, capacitor C 28 another termination level.
Described chip U3 adopts control chip MC33262.
Described chip U1 adopts chip VIPER12A.
Described chip U2 adopts chip STC15F104E.
Timed power-regulation control circuit 1 of the present invention adopts the programming of STC15F series monolithic, its characteristics are: delay time can easily be changed, low in energy consumption, regularly accurately, circuit is succinct, reliable and stable, by the control chip MC33262 in the capability correction pfc circuit 4 is stopped, change pfc circuit major loop 400V voltage and drop to the output of 300V voltage, thereby realize regularly falling power output, power is compared and is reduced 30%, and power supply, light-source temperature all lower greatly.
The present invention can guarantee the ballast operate as normal, can stably realize falling power output again, and both energy savings increased power source life again.
Description of drawings:
Fig. 1 is a structural representation of the present invention.
Embodiment:
With reference to Fig. 1, this embodiment is by the following technical solutions: it comprises timed power-regulation control circuit 1, rectification circuit 2, EMI circuit 3, capability correction pfc circuit 4, drive circuit 5 and meets lamp coupler J1, timed power-regulation control circuit 1 links to each other with rectification circuit 2, capability correction pfc circuit 4 respectively, rectification circuit 2 links to each other with EMI circuit 3, capability correction pfc circuit 4 respectively, capability correction pfc circuit 4, drive circuit 5 and meet lamp coupler J1 and link to each other successively.
Described timed power-regulation control circuit 1 comprises chip U1, chip U2, voltage stabilizing didoe WD1-WD2, diode D1-D3, capacitor C 1-C6, resistance R 1-R3 and inductance L 1,1 pin of chip U1,2 pin, 3 pin all link to each other with capability correction pfc circuit 4 with rectification circuit 2 with 4 pin, 5 pin of chip U1 and voltage stabilizing didoe WD1 negative pole, capacitor C 2 one ends link to each other with diode D1 negative pole, voltage stabilizing didoe WD1 positive pole links to each other with 6 pin of capacitor C 1 one ends and chip U1,7 pin of chip U1 and 8 pin all with capacitor C 1 other end, capacitor C 2 other ends, inductance L 1 one ends, diode D2 negative pole links to each other, diode D2 plus earth, inductance L 1 other end and diode D1 positive pole, capacitor C 3 positive poles, resistance R 1 one ends, capacitor C 4 one ends, resistance R 2 one ends link to each other, capacitor C 3 negative poles, resistance R 1 other end, the equal ground connection of capacitor C 4 other ends, resistance R 2 other ends link to each other with 2 pin of chip U2,2 pin of chip U2 respectively with capacitor C 6 one ends, capacitor C 5 positive poles, voltage stabilizing didoe WD2 negative pole, resistance R 3 one ends link to each other, capacitor C 6 other ends, capacitor C 5 negative poles, the anodal all ground connection of voltage stabilizing didoe WD2,1 pin of chip U2 and diode D3 positive pole, resistance R 3 other ends link to each other, the 4 pin ground connection of chip U2, diode D3 negative pole links to each other with capability correction pfc circuit 4.
Described rectification circuit 2 adopts bridge rectifier diode ZD1.
Described EMI circuit 3 comprises capacitor C 7-C11, transformer T3, transformer T5, thermistor RT1, fuse F1 and coupler J2, capacitor C 7 one ends link to each other with 1 pin of bridge rectifier diode ZD1 and 1 pin of transformer T5 respectively, capacitor C 7 other ends link to each other with 2 pin of bridge rectifier diode ZD1 and 2 pin of transformer T5 respectively, 3 pin of transformer T5 respectively with capacitor C 8 one ends, 1 pin of capacitor C 10 1 ends and transformer T3 links to each other, capacitor C 8 another termination level, capacitor C 10 other ends and capacitor C 11 1 ends, 4 pin of transformer T5,2 pin of transformer T3 link to each other, capacitor C 11 another termination level, 3 pin of transformer T3 respectively with capacitor C 9 one ends, thermistor RT1 one end, fuse F1 one end links to each other, 4 pin of transformer T3 respectively with capacitor C 9 other ends, the thermistor RT1 other end, 1 pin of coupler J2 links to each other, the fuse F1 other end links to each other with 3 pin of coupler J2, and 2 pin of coupler J2 connect level.
Described capability correction pfc circuit 4 comprises resistance R 4-R17, capacitor C 12-C18, chip U3, voltage stabilizing didoe WD3, diode D4-D5, metal-oxide-semiconductor Q6 and transformer T4, capacitor C 12 1 ends, resistance R 8 one ends, resistance R 9 one ends, 1 pin of transformer T4 all links to each other with 1 pin of bridge rectifier diode ZD1, capacitor C 12 other end ground connection, resistance R 8 other ends respectively with resistance R 4 one ends, capacitor C 14 1 ends, 3 pin of chip U3 link to each other, resistance R 4 other ends, capacitor C 14 other end ground connection, resistance R 9 other ends link to each other with 5 pin of chip U3,2 pin of chip U3 link to each other with capacitor C 15 1 ends, capacitor C 15 other end ground connection, 1 pin of chip U3 respectively with capacitor C 13 1 ends, resistance R 6 one ends, diode D3 negative pole in resistance R 7 one ends and the timed power-regulation control circuit 1 links to each other, capacitor C 13 other end ground connection, resistance R 6 other ends link to each other with resistance R 5 one ends, resistance R 5 other end ground connection, resistance R 7 other ends link to each other with resistance R 10 1 ends, resistance R 10 other ends and diode D5 negative pole, 17 anodal linking to each other of capacitor C, capacitor C 17 is in parallel with resistance R 16, capacitor C 17 negative poles and capacitor C 18 positive poles, resistance R 17 1 ends link to each other, capacitor C 18 negative poles, the equal ground connection of resistance R 17 other ends, 4 pin of chip U3 link to each other with resistance R 15 1 ends, resistance R 15 other ends link to each other with 2 pin and resistance R 14 1 ends of metal-oxide-semiconductor Q6 respectively, resistance R 14 other end ground connection, 1 pin of metal-oxide-semiconductor Q6 links to each other with resistance R 13 1 ends, resistance R 13 other ends link to each other with 6 pin of chip U3, the 7 pin ground connection of chip U3,3 pin of metal-oxide-semiconductor Q6 and diode D5 positive pole, 3 pin of transformer T4 link to each other, the 4 pin ground connection of transformer T4,2 pin of transformer T4 respectively with resistance R 11 1 ends, resistance R 12 1 ends link to each other, resistance R 12 other ends link to each other with 8 pin of chip U3, resistance R 11 other ends link to each other with diode D4 is anodal, diode D4 negative pole respectively with voltage stabilizing didoe WD3 negative pole, capacitor C 16 is anodal continuous, voltage stabilizing didoe WD3 positive pole, the equal ground connection of capacitor C 16 negative poles.
Described drive circuit 5 comprises starting circuit MK1, resistance R 18-R22, voltage stabilizing didoe WD4-WD8, metal-oxide-semiconductor Q1, metal-oxide-semiconductor Q4, transformer T1, thyristor Q2, diode D6 and inductance L 2,4 pin of starting circuit MK1,1 pin of metal-oxide-semiconductor Q4 all links to each other with resistance R 16 1 ends in the capability correction pfc circuit 4,3 pin of starting circuit MK1 link to each other with resistance R 18 1 ends with 5 pin, resistance R 18 other ends respectively with voltage stabilizing didoe WD4 positive pole, 3 pin of metal-oxide-semiconductor Q4 link to each other, voltage stabilizing didoe WD4 negative pole links to each other with voltage stabilizing didoe WD5 negative pole, 2 pin and 6 pin of voltage stabilizing didoe WD5 positive pole and starting circuit MK1,1 pin of transformer T2,2 pin of metal-oxide-semiconductor Q4 link to each other with 1 pin of metal-oxide-semiconductor Q1, the 1 pin ground connection of starting circuit MK1, link to each other respectively, 3 pin of metal-oxide-semiconductor Q1 respectively with inductance L 2 one ends, voltage stabilizing didoe WD7 positive pole, thyristor Q2 anode, resistance R 19 1 ends link to each other, resistance R 19 other ends link to each other with 3 pin of transformer T1, voltage stabilizing didoe WD7 negative pole links to each other with voltage stabilizing didoe WD6 negative pole, 2 pin of metal-oxide-semiconductor Q1, inductance L 2 other ends, voltage stabilizing didoe WD6 positive pole, the equal ground connection of 2 pin of thyristor Q2 negative electrode and transformer T1,4 pin of transformer T1 link to each other with capacitor C 19 1 ends, capacitor C 19 another termination level, 1 pin of transformer T1 links to each other with capacitor C 24 1 ends, capacitor C 24 other ends link to each other with capacitor C 23 1 ends, capacitor C 23 other ends respectively with 3 pin of transformer T2, capacitor C 25 1 ends, resistance R 22 1 ends, capacitor C 26 1 ends link to each other, resistance R 22 other ends, capacitor C 25 other ends all link to each other with 1 pin that meets lamp coupler J1, capacitor C 26 other ends link to each other with capacitor C 27 1 ends, capacitor C 27 other end ground connection, the 4 pin ground connection of transformer T2,2 pin of transformer T2 link to each other with diode D6 is anodal, diode D6 negative pole respectively with resistance R 20 1 ends, resistance R 21 1 ends link to each other, resistance R 20 other end ground connection, resistance R 21 other ends respectively with voltage stabilizing didoe WD8 negative pole, capacitor C 22 positive poles, capacitor C 21 1 ends link to each other, capacitor C 22 negative poles, the equal ground connection of capacitor C 21 other ends, voltage stabilizing didoe WD8 positive pole respectively with capacitor C 20 1 ends, the controlled end of thyristor Q2 links to each other, capacitor C 20 other end ground connection, capacitor C 28 1 ends, connect the equal ground connection of 2 pin of lamp coupler J1, capacitor C 28 another termination level.
Described chip U3 adopts control chip MC33262.
Described chip U1 adopts chip VIPER12A.
Described chip U2 adopts chip STC15F104E.
The timed power-regulation control circuit 1 of this embodiment adopts the programming of STC15F series monolithic, its characteristics are: delay time can easily be changed, low in energy consumption, regularly accurately, circuit is succinct, reliable and stable, by the control chip MC33262 in the capability correction pfc circuit 4 is stopped, change pfc circuit major loop 400V voltage and drop to the output of 300V voltage, thereby realize regularly falling power output, power is compared and is reduced 30%, and power supply, light-source temperature all lower greatly.
This embodiment can guarantee the ballast operate as normal, can stably realize falling power output again, and both energy savings increased power source life again.
Claims (6)
1. auto-excitation type low frequency ball steeps electrodeless lamp and regularly falls power output ballast, it is characterized in that it comprises timed power-regulation control circuit (1), rectification circuit (2), EMI circuit (3), capability correction pfc circuit (4), drive circuit (5) and connects lamp coupler (J1), timed power-regulation control circuit (1) links to each other with rectification circuit (2), capability correction pfc circuit (4) respectively, rectification circuit (2) links to each other with EMI circuit (3), capability correction pfc circuit (4) respectively, capability correction pfc circuit (4), drive circuit (5) and connect lamp coupler (J1) and link to each other successively.
2. auto-excitation type low frequency ball according to claim 1 steeps electrodeless lamp and regularly falls power output ballast, it is characterized in that described timed power-regulation control circuit (1) comprises chip (U1), chip (U2), voltage stabilizing didoe (WD1)-(WD2), diode (D1)-(D3), electric capacity (C1)-(C6), resistance (R1)-(R3) and inductance (L1), 1 pin of chip (U1), 2 pin, 3 pin all link to each other with capability correction pfc circuit (4) with rectification circuit (2) with 4 pin, 5 pin of chip (U1) and voltage stabilizing didoe (WD1) negative pole, electric capacity (C2) end links to each other with diode (D1) negative pole, voltage stabilizing didoe (WD1) is anodal to link to each other with 6 pin of electric capacity (C1) end and chip (U1), 7 pin of chip (U1) and 8 pin all with electric capacity (C1) other end, electric capacity (C2) other end, inductance (L1) end, diode (D2) negative pole links to each other, diode (D2) plus earth, inductance (L1) other end and diode (D1) positive pole, electric capacity (C3) positive pole, resistance (R1) end, electric capacity (C4) end, resistance (R2) end links to each other, electric capacity (C3) negative pole, resistance (R1) other end, the equal ground connection of electric capacity (C4) other end, resistance (R2) other end links to each other with 2 pin of chip (U2), 2 pin of chip (U2) respectively with electric capacity (C6) end, electric capacity (C5) positive pole, voltage stabilizing didoe (WD2) negative pole, resistance (R3) end links to each other, electric capacity (C6) other end, electric capacity (C5) negative pole, the anodal all ground connection of voltage stabilizing didoe (WD2), 1 pin of chip (U2) and diode (D3) positive pole, resistance (R3) other end links to each other, 4 pin ground connection of chip (U2), diode (D3) negative pole links to each other with capability correction pfc circuit (4).
3. auto-excitation type low frequency ball according to claim 1 steeps electrodeless lamp and regularly falls power output ballast, it is characterized in that described rectification circuit (2) adopts bridge rectifier diode (ZD1).
4. auto-excitation type low frequency ball according to claim 1 steeps electrodeless lamp and regularly falls power output ballast, it is characterized in that described EMI circuit (3) comprises electric capacity (C7)-(C11), transformer (T3), transformer (T5), thermistor (RT1), fuse (F1) and coupler (J2), electric capacity (C7) end links to each other with 1 pin of bridge rectifier diode (ZD1) and 1 pin of transformer (T5) respectively, electric capacity (C7) other end links to each other with 2 pin of bridge rectifier diode (ZD1) and 2 pin of transformer (T5) respectively, 3 pin of transformer (T5) respectively with electric capacity (C8) end, 1 pin of electric capacity (C10) end and transformer (T3) links to each other, another termination level of electric capacity (C8), electric capacity (C10) other end and electric capacity (C11) end, 4 pin of transformer (T5), 2 pin of transformer (T3) link to each other, another termination level of electric capacity (C11), 3 pin of transformer (T3) respectively with electric capacity (C9) end, thermistor (RT1) end, fuse (F1) end links to each other, 4 pin of transformer (T3) respectively with electric capacity (C9) other end, thermistor (RT1) other end, 1 pin of coupler (J2) links to each other, fuse (F1) other end links to each other with 3 pin of coupler (J2), and 2 pin of coupler (J2) connect level.
5. auto-excitation type low frequency ball according to claim 1 steeps electrodeless lamp and regularly falls power output ballast, it is characterized in that described capability correction pfc circuit (4) comprises resistance (R4)-(R17), electric capacity (C12)-(C18), chip (U3), voltage stabilizing didoe (WD3), diode (D4)-(D5), metal-oxide-semiconductor (Q6) and transformer (T4), electric capacity (C12) end, resistance (R8) end, resistance (R9) end, 1 pin of transformer (T4) all links to each other with 1 pin of bridge rectifier diode (ZD1), electric capacity (C12) other end ground connection, resistance (R8) other end respectively with resistance (R4) end, electric capacity (C14) end, 3 pin of chip (U3) link to each other, resistance (R4) other end, electric capacity (C14) other end ground connection, resistance (R9) other end links to each other with 5 pin of chip (U3), 2 pin of chip (U3) link to each other with electric capacity (C15) end, electric capacity (C15) other end ground connection, 1 pin of chip (U3) respectively with electric capacity (C13) end, resistance (R6) end, diode (D3) negative pole in resistance (R7) end and the timed power-regulation control circuit 1 links to each other, electric capacity (C13) other end ground connection, resistance (R6) other end links to each other with resistance (R5) end, resistance (R5) other end ground connection, resistance (R7) other end links to each other with resistance (R10) end, resistance (R10) other end and diode (D5) negative pole, electric capacity (C17) is anodal to link to each other, electric capacity (C17) is in parallel with resistance (R16), electric capacity (C17) negative pole and electric capacity (C18) positive pole, resistance (R17) end links to each other, electric capacity (C18) negative pole, the equal ground connection of resistance (R17) other end, 4 pin of chip (U3) link to each other with resistance (R15) end, resistance (R15) other end links to each other with 2 pin and resistance (R14) end of metal-oxide-semiconductor (Q6) respectively, resistance (R14) other end ground connection, 1 pin of metal-oxide-semiconductor (Q6) links to each other with resistance (R13) end, resistance (R13) other end links to each other with 6 pin of chip (U3), 7 pin ground connection of chip (U3), 3 pin of metal-oxide-semiconductor (Q6) and diode (D5) positive pole, 3 pin of transformer (T4) link to each other, 4 pin ground connection of transformer (T4), 2 pin of transformer (T4) respectively with resistance (R11) end, resistance (R12) end links to each other, resistance (R12) other end links to each other with 8 pin of chip (U3), resistance (R11) other end links to each other with diode (D4) is anodal, diode (D4) negative pole respectively with voltage stabilizing didoe (WD3) negative pole, electric capacity (C16) is anodal to link to each other voltage stabilizing didoe (WD3) positive pole, the equal ground connection of electric capacity (C16) negative pole.
6. auto-excitation type low frequency ball according to claim 1 steeps electrodeless lamp and regularly falls power output ballast, it is characterized in that described drive circuit (5) comprises starting circuit (MK1), resistance (R18)-(R22), voltage stabilizing didoe (WD4)-(WD8), metal-oxide-semiconductor (Q1), metal-oxide-semiconductor (Q4), transformer (T1), thyristor (Q2), diode (D6) and inductance (L2), 4 pin of starting circuit (MK1), 1 pin of metal-oxide-semiconductor (Q4) all links to each other with resistance (R16) end in the capability correction pfc circuit (4), 3 pin of starting circuit (MK1) link to each other with resistance (R18) end with 5 pin, resistance (R18) other end respectively with voltage stabilizing didoe (WD4) positive pole, 3 pin of metal-oxide-semiconductor (Q4) link to each other, voltage stabilizing didoe (WD4) negative pole links to each other with voltage stabilizing didoe (WD5) negative pole, 2 pin and 6 pin of voltage stabilizing didoe (WD5) positive pole and starting circuit (MK1), 1 pin of transformer (T2), 2 pin of metal-oxide-semiconductor (Q4) link to each other with 1 pin of metal-oxide-semiconductor (Q1), 1 pin ground connection of starting circuit (MK1), link to each other respectively, 3 pin of metal-oxide-semiconductor (Q1) respectively with inductance (L2) end, voltage stabilizing didoe (WD7) positive pole, thyristor (Q2) anode, resistance (R19) end links to each other, resistance (R19) other end links to each other with 3 pin of transformer (T1), voltage stabilizing didoe (WD7) negative pole links to each other with voltage stabilizing didoe (WD6) negative pole, 2 pin of metal-oxide-semiconductor (Q1), inductance (L2) other end, voltage stabilizing didoe (WD6) positive pole, the equal ground connection of 2 pin of thyristor (Q2) negative electrode and transformer (T1), 4 pin of transformer (T1) link to each other with electric capacity (C19) end, another termination level of electric capacity (C19), 1 pin of transformer (T1) links to each other with electric capacity (C24) end, electric capacity (C24) other end links to each other with electric capacity (C23) end, electric capacity (C23) other end respectively with 3 pin of transformer (T2), electric capacity (C25) end, resistance (R22) end, electric capacity (C26) end links to each other, resistance (R22) other end, electric capacity (C25) other end all links to each other with 1 pin that connects lamp coupler (J1), electric capacity (C26) other end links to each other with electric capacity (C27) end, electric capacity (C27) other end ground connection, 4 pin ground connection of transformer (T2), 2 pin of transformer (T2) link to each other with diode (D6) is anodal, diode (D6) negative pole respectively with resistance (R20) end, resistance (R21) end links to each other, resistance (R20) other end ground connection, resistance (R21) other end respectively with voltage stabilizing didoe (WD8) negative pole, electric capacity (C22) positive pole, electric capacity (C21) end links to each other, electric capacity (C22) negative pole, the equal ground connection of electric capacity (C21) other end, voltage stabilizing didoe (WD8) positive pole respectively with electric capacity (C20) end, the controlled end of thyristor (Q2) links to each other, electric capacity (C20) other end ground connection, electric capacity (C28) end, connect the equal ground connection of 2 pin of lamp coupler (J1), another termination level of electric capacity (C28).
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110170219A CN102300377A (en) | 2011-06-23 | 2011-06-23 | Timing power output reduction ballast of auto-excitation-type low-frequency ball bulb electrodeless lamp |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110170219A CN102300377A (en) | 2011-06-23 | 2011-06-23 | Timing power output reduction ballast of auto-excitation-type low-frequency ball bulb electrodeless lamp |
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| CN102300377A true CN102300377A (en) | 2011-12-28 |
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| CN201110170219A Pending CN102300377A (en) | 2011-06-23 | 2011-06-23 | Timing power output reduction ballast of auto-excitation-type low-frequency ball bulb electrodeless lamp |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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Application publication date: 20111228 |