CN102300235A - Device and method for synchronizing main clock and standby clock - Google Patents
Device and method for synchronizing main clock and standby clock Download PDFInfo
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- CN102300235A CN102300235A CN2010102124161A CN201010212416A CN102300235A CN 102300235 A CN102300235 A CN 102300235A CN 2010102124161 A CN2010102124161 A CN 2010102124161A CN 201010212416 A CN201010212416 A CN 201010212416A CN 102300235 A CN102300235 A CN 102300235A
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Abstract
The invention provides a device and method for synchronizing a main clock and a standby clock. The method comprises the steps of: counting a state of a clock t1 of a main clock and standby clock synchronizing system; when the state of the t1 falls behind a clock t3 of a mainboard sending system, reducing the delay of the t1; and when the state of the t1 pulls ahead the clock t3 of the mainboard sending system, adding the delay of the t1 until the t1 is aligned to the clock t3 of the mainboard sending system. By adopting the technical scheme provided by the invention, even if the delay between the clock of a standby board synchronizing system and the received synchronizing signal is not determined, a main clock and a standby clock can be subjected to phase coincidence.
Description
Technical field
The present invention relates to the communications field, the synchronous device and method of particularly a kind of master/backup clock.
Background technology
For this equipment that needs high reliability in base station, adopt active and standby framework usually, when mainboard went wrong, slave board can carry out seamless switching, thereby guaranteed the professional interruption of not having.
Occur under the unusual condition at mainboard in order to make, slave board can steadily and comprehensively replace mainboard, need the design related algorithm to realize the switching of every function, wherein the switching of clock seems and is even more important, because for the system as CDMA (Code Division Multiple Access), the necessary homophase of clock, this just mean switch slave board clock in the past must with the clock homophase of former mainboard, and active and standby plate all is the clock source that produces separately, realize homophase, then need to exist certain mutual.Around this theme, there is the method for multiple master/backup clock homophase.
For the same phase method of traditional master/backup clock, as shown in Figure 1, can be under the situation that hardware condition allows, by mainboard FPGA (Field Programmable Gate Array, field programmable gate array) send out synchronizing signal (Sync), this synchronizing signal arrives slave board through fixed delay.The active and standby synchro system clock of slave board is after receiving this synchronizing signal, again through producing again after one section constant time lag.Active and standby synchro system clock of slave board and the external transfer system clock of slave board have adjustable delay.Only need to regulate this time-delay, just can guarantee external transfer system clock of mainboard and the external transfer system clock of slave board homophase.If but hardware condition can't support, for example the time-delay between slave board synchro system clock and the synchronizing signal that receives is uncertain, then can't carry out homophase to master/backup clock.
Summary of the invention
The present invention proposes a kind of master/backup clock synchronizer and method,, also can carry out the master/backup clock homophase even when the time-delay between slave board synchro system clock and the synchronizing signal that receives is uncertain.
The method that a kind of master/backup clock is synchronous comprises:
Add up the state of active and standby synchro system clock t1, when the state of described t1 is the time-delay that reduces t1 when lagging behind mainboard transmitting system clock t3, when the state of described t1 is the time-delay that increases t1 when being ahead of mainboard transmitting system clock t3, align with mainboard transmitting system clock t3 until adjusting to t1.
Further, in each measurement period K, add up the state of described active and standby synchro system clock t1, when described measurement period K finishes, if the state of t1 is to lag behind t3 then the time-delay of described t1 to be reduced x, if the state of t1 is to be ahead of t3 then the time-delay of described t1 to be increased x, enter next measurement period then;
Described x is for adjusting step-length.
Further, in each measurement period K, utilize active and standby synchro system clock t1 that the signal of the system clock t3 of mainboard transmission is repeatedly sampled, during each the sampling, when active and standby synchro system clock t1 is ahead of plate transmitting system clock t3, the value of slave board counter is subtracted 1, when active and standby synchro system clock t1 lags behind plate transmitting system clock t3, the value of slave board counter is added 1;
When measurement period K finishes, if the value of described counter judges then that greater than default high threshold the state of t1 is for lagging behind t3, if being lower than default low threshold, the value of described counter judges that then the state of t1 is for being ahead of t3, if the value of described counter judges then that between high low threshold the edge of described t1 aligns with the edge of t3.
Further, when the edge of described t1 aligns with the edge of t3, if judge active and standby synchro system clock t1 and mainboard transmitting system clock t3 alignment when meeting in the following condition any:
(a1) if be in state 1 in the last measurement period K, promptly by transferring to state 3 behind the time-delay minimizing x of state 1 with active and standby synchro system clock t1;
(a2) if be in state 2 in the last measurement period K, promptly by transferring to state 3 behind the time-delay increase x of state 1 with active and standby synchro system clock t1;
(a3) if current be first measurement period K, then the time-delay of active and standby synchro system clock t1 is increased x, if statistics is a state 1 in the next measurement period K, and turn back to state 3 after reducing x by time-delay with active and standby synchro system clock t1;
(a4) if current be first measurement period K, then the time-delay of active and standby synchro system clock t1 is reduced x, if statistics is a state 2 in the next measurement period K, and turn back to state 3 after increasing x by time-delay with active and standby synchro system clock t1.
Further, the measurement period of establishing when forward position alignment is i cycle, if active and standby synchro system clock t1 and mainboard transmitting system clock t3 align when judging i measurement period end when meeting in the following condition any:
(b1) time-delay with active and standby synchro system clock t1 reduces x, return step S1 afterwards, if the state of the t1 that adds up in the next measurement period (i.e. i+1 measurement period) is a state 2, and with t1 set by step the mode of the S5 state of adjusting afterwards t1 in i+2 the measurement period be state 1 or state 3;
(b2) time-delay with active and standby synchro system clock t1 increases x, return step S1 afterwards, if the state of the t1 that adds up in the next measurement period (i.e. i+1 measurement period) is a state 1, and with t1 set by step the mode of the S4 state of adjusting afterwards t1 in i+2 the measurement period be state 2 or state 3.
The time-delay of described active and standby synchro system clock t1 is t when further, establishing active and standby synchro system clock t1 and align with mainboard transmitting system clock t3
1, the time-delay to plate transmitting system clock t3 input field programmable gate array that receives from external transmitting system clock to the slave board of the PLL of main board output is t
2, the clock cycle is T, and the time-delay Δ t of external transmitting system clock t2 is set in such a way:
Work as t
1-t
2＞0 o'clock, described Δ t=t
1-t
2Work as t
1-t
2＜0 o'clock, described Δ t=t
1-t
2+ T.
The present invention also provides a kind of master/backup clock synchronous device, comprises the field programmable gate array that is positioned at slave board;
Described field programmable gate array comprises control module, be used to add up the state of active and standby synchro system clock t1, when the state of described t1 is the time-delay that reduces described t1 when lagging behind mainboard transmitting system clock t3, when the state of described t1 is the time-delay that increases described t1 when being ahead of mainboard transmitting system clock t3, align with mainboard transmitting system clock t3 until adjusting to described t1.
Further, described control module is alignd t1 and is meant with t3, in each measurement period K, add up the state of described active and standby synchro system clock t1, when described measurement period K finishes, if the state of t1 is to lag behind t3 then the time-delay of described t1 to be reduced x,, enter next measurement period then if the state of t1 is to be ahead of t3 then the time-delay of described t1 to be increased x;
Described x is for adjusting step-length.
Further, described field programmable gate array also comprises d type flip flop and counter;
Described d type flip flop is used for when the active and standby synchro system clock t1 that receives lags behind t3, to the signal of counter output expression t1 hysteresis, and when the active and standby synchro system clock t1 that receives is ahead of t3, to the leading signal of counter output expression t1;
Described counter, be used in each measurement period K when reception be input as high signal the time value of counter added 1, the value with counter when being input as low signal subtracts 1;
Described control module reads the value of counter when each measurement period K finishes, if the value of described counter judges then that greater than default high threshold the state of t1 is for lagging behind t3, if being lower than default low threshold, the value of described counter judges that then the state of t1 is for being ahead of t3, if the value of described counter judges then that between high low threshold the edge of described t1 aligns with the edge of t3.
Further, described control module also is used for when the edge of described t1 aligns with the edge of t3, if judge active and standby synchro system clock t1 and mainboard transmitting system clock t3 alignment when meeting in the following condition any:
(a1) if be in state 1 in the last measurement period K, promptly by transferring to state 3 behind the time-delay minimizing x of state 1 with active and standby synchro system clock t1;
(a2) if be in state 2 in the last measurement period K, promptly by transferring to state 3 behind the time-delay increase x of state 1 with active and standby synchro system clock t1;
(a3) if current be first measurement period K, then the time-delay of active and standby synchro system clock t1 is increased x, if statistics is a state 1 in the next measurement period K, and turn back to state 3 after reducing x by time-delay with active and standby synchro system clock t1;
(a4) if current be first measurement period K, then the time-delay of active and standby synchro system clock t1 is reduced x, if statistics is a state 2 in the next measurement period K, and turn back to state 3 after increasing x by time-delay with active and standby synchro system clock t1.
Further, the measurement period of establishing when forward position alignment is i cycle, and active and standby synchro system clock t1 and mainboard transmitting system clock t3 alignd when described control module also was used for judging i measurement period end when meeting any of following condition:
(b1) time-delay with active and standby synchro system clock t1 reduces x, return step S1 afterwards, if the state of the t1 that adds up in the next measurement period (i.e. i+1 measurement period) is a state 2, and with t1 set by step the mode of the S5 state of adjusting afterwards t1 in i+2 the measurement period be state 1 or state 3;
(b2) time-delay with active and standby synchro system clock t1 increases x, return step S1 afterwards, if the state of the t1 that adds up in the next measurement period (i.e. i+1 measurement period) is a state 1, and with t1 set by step the mode of the S4 state of adjusting afterwards t1 in i+2 the measurement period be state 2 or state 3.
Further, described control module also be used for when described t1 with after t3 aligns, the time-delay Δ t of external transmitting system clock t2 is set in the following manner:
If the time-delay of described active and standby synchro system clock t1 was t when active and standby synchro system clock t1 alignd with mainboard transmitting system clock t3
1, the time-delay to plate transmitting system clock t3 input field programmable gate array that receives from external transmitting system clock to the slave board of the PLL of main board output is t
2, the clock cycle is T, works as t
1-t
2＞0 o'clock, Δ t=t
1-t
2, work as t
1-t
2＜0 o'clock, Δ t=t
1-t
2+ T.
In sum, the invention provides a kind of master/backup clock synchronizer and method, more flexible than prior art, do not need special hardware supports, in addition, the present invention adopts feedback principle, the reliability height.
Description of drawings
Fig. 1 is a main standby synchronous method schematic diagram in the prior art;
Fig. 2 is the master/backup clock synchronizer schematic diagram described in the present invention;
State transition graph when Fig. 3 is clock of the present invention alignment;
Fig. 4 is the flow chart of the inventive method embodiment.
Embodiment
Present embodiment provides a kind of master/backup clock synchronous device, is the master/backup clock synchronizer schematic diagram described in the present invention as shown in Figure 2, comprises the PLL and the FPGA that are positioned at slave board; FPGA comprises d type flip flop (DFF), counter and control module;
The external transmitting system clock of mainboard is introduced slave board through constant time lag, allow slave board synchro system clock that the external transmitting system clock of the mainboard that is sent to slave board is sampled, by in a period of time repeatedly sampled result add up, judge that the active and standby synchronised clock of slave board is leading to the mainboard clock that sends, lag behind or the edge alignment, and adjusting output is delayed time or judgement is rising edge or trailing edge alignment, thereby allow the mainboard clock that sends align with the active and standby synchronised clock rising edge of slave board.By regulating the time-delay of the active and standby synchronised clock of slave board and other each road clocks of slave board, make other each road clock homophases of mainboard clock and slave board.
D type flip flop (DFF), whether the system clock t3 that active and standby synchro system clock t1 that is used for relatively receiving and mainboard send is synchronous, when t1 lags behind t3, the signal that lags behind to counter output expression t1 (as can but to be not limited to be high signal), when t1 is ahead of t3, to the leading signal of counter output expression t1 (as can but to be not limited to be low signal), when t1 aligns with the t3 edge, d type flip flop is exported a high signal or a low signal at random, and what export through repeatedly sampling in a period of time so is the staggered signal of height.
Counter, be used in each measurement period K when reception be input as high signal the time value of counter added 1, the value with counter when being input as low signal subtracts 1.
Control module, be used for reading when each measurement period K finishes the value of counter, when the value of counter judges that current active and standby synchro system clock t1 lags behind plate transmitting system clock t3 during greater than default high threshold, be made as state 1, when the count value of counter judges that active and standby synchro system clock t1 is ahead of plate transmitting system clock t3 during less than default low threshold, be made as state 2, when the count value of counter between high threshold and low threshold, the edge of then judging active and standby synchro system clock t1 is aligned in the edge to plate transmitting system clock t3, is made as state 3;
Control module also is used for each measurement period K and finishes and judge when slave board is state 1 that the time-delay with active and standby synchro system clock t1 reduces x (x is for adjusting step-length), time-delay with active and standby synchro system clock t1 when judging that slave board is state 2 increases x, and the value of counter is changed to non-0 initial value; When judging that slave board is state 3, further judge it is that rising edge aligns with rising edge or rising edge aligns with trailing edge, if judge be rising edge align with rising edge (being that active and standby synchro system clock t1 and mainboard transmitting system clock t3 align) the time-delay Δ t of external transmitting system clock t2 then is set, if judge it is that the time-delay that rising edge aligns with trailing edge then active and standby synchro system clock t1 reduces x (or increase x), and the value of counter is changed to non-0 initial value enters next measurement period.
Further, the time-delay Δ t that control module is provided with external transmitting system clock t2 is meant that the time-delay of establishing active and standby synchro system clock t1 is t
1, the time-delay to plate transmitting system clock t3 input FPGA that receives from external transmitting system clock to the standby plate of the PLL (Phase Locked Loop) of main board output is t
2, the clock cycle is T, then the time-delay of external transmitting system clock t2 is provided with Δ t to be:
Δt＝t
1-t
2 (t
1-t
2＞0)
Or Δ t=t
1-t
2+ T (t
1-t
2＜0).
Further, if control module is judged active and standby synchro system clock t1 and mainboard transmitting system clock t3 alignment when meeting in the following condition any:
(a1) if be in state 1 in the last measurement period K, promptly by transferring to state 3 behind the time-delay minimizing x of state 1 with active and standby synchro system clock t1;
(a2) if be in state 2 in the last measurement period K, promptly by transferring to state 3 behind the time-delay increase x of state 2 with active and standby synchro system clock t1;
(a3) if current be first measurement period K, then the time-delay with active and standby synchro system clock t1 increases x, if statistics is a state 1 in the next measurement period K, and by transferring to state 2 or state 3 behind the time-delay minimizing x with active and standby synchro system clock t1;
(a4) if current be first measurement period K, then the time-delay with active and standby synchro system clock t1 reduces x, if statistics is a state 2 in the next measurement period K, and by transferring to state 2 or state 3 behind the time-delay increase x with active and standby synchro system clock t1.
(a3) or (a4) judge that active and standby synchro system clock t1 and mainboard transmitting system clock t3 finish to align in first measurement period if in a manner described, and when being not state 3 by the follow-up state of adjusting t1 when the 3rd measurement period finishes, need to continue to add up the state of t1 by above flow process, decidable t1 aligns with t3 once more when the state that counts on t1 once more is state 3, does not need further to judge and adjust.
Further, the measurement period of establishing when forward position alignment is i cycle, and active and standby synchro system clock t1 and mainboard transmitting system clock t3 alignd when control module was judged i measurement period end during in meeting following condition any:
(b1) time-delay with active and standby synchro system clock t1 reduces x, return step S1 afterwards, if the state of the t1 that adds up in the next measurement period (i.e. i+1 measurement period) is a state 2, and with t1 set by step the mode of the S5 state of adjusting afterwards t1 in i+2 the measurement period be state 1 or state 3;
(b2) time-delay with active and standby synchro system clock t1 increases x, return step S1 afterwards, if the state of the t1 that adds up in the next measurement period (i.e. i+1 measurement period) is a state 1, and with t1 set by step the mode of the S4 state of adjusting afterwards t1 in i+2 the measurement period be state 2 or state 3.
(b1) or (b2) judge that active and standby synchro system clock t1 and mainboard transmitting system clock t3 have alignd in i measurement period end if in a manner described, and when being not state 3 by the follow-up state of adjusting t1 when i+2 measurement period finishes, need to continue to add up the state of t1 by above flow process, decidable t1 aligns with t3 once more when the state that counts on t1 once more is state 3, does not need further to judge and adjust.
Present embodiment provides a kind of master/backup clock synchronous method, comprise: the state of adding up active and standby synchro system clock t1, when the state of t1 is the time-delay that reduces t1 when lagging behind mainboard transmitting system clock t3, when the state of t1 is the time-delay that increases t1 when being ahead of mainboard transmitting system clock t3, align with mainboard transmitting system clock t3 until adjusting to t1.
As shown in Figure 4, may further comprise the steps:
For the counter of slave board is provided with the initial value of a non-zero, and a high threshold and a low threshold are set;
Step S1: in slave board FPGA, utilize active and standby synchro system clock t1 that the signal of the system clock t3 of mainboard transmission is repeatedly sampled, and according to the sampled result output signal;
During each the sampling, when active and standby synchro system clock t1 is ahead of plate transmitting system clock t3, d type flip flop (DFF) is output as low, otherwise when active and standby synchro system clock t1 lags behind mainboard transmitting system clock t3, d type flip flop is output as height, when active and standby synchro system clock t1 alignd with mainboard transmitting system clock t3 edge, d type flip flop was exported a high signal or a low signal at random, and what export through repeatedly sampling in a period of time so is the staggered signal of height.
Step S2: if being input as of receiving is low, then the value with counter subtracts 1; If be input as height, then the value with counter adds 1.
Step S3: read the count value of measurement period K inside counting device accumulative total, if the count value of counter judges then that greater than default high threshold current active and standby synchro system clock t1 lags behind plate transmitting system clock t3, is made as state 1, then execution in step S4;
If the count value of counter judges then that less than default low threshold active and standby synchro system clock t1 is ahead of plate transmitting system clock t3, is made as state 2, then execution in step S5; If the count value of counter between high threshold and low threshold, is then judged the edge of active and standby synchro system clock t1 and is aligned in the edge to plate transmitting system clock t3, is made as state 3, then execution in step S6;
Step S4: establishing and adjusting step-length is x (is 1ns as x), because of being in state 1, with the time-delay minimizing x of active and standby synchro system clock t1; Return the statistics that step S1 carries out next measurement period K inside counting device then;
Step S5: establishing and adjusting step-length is x (is 1ns as x), because of being in state 2, with the time-delay increase x of active and standby synchro system clock t1; Return the statistics that step S1 carries out next measurement period K inside counting device then;
Step S6: because of being in state 3, needing further to judge is that rising edge aligns with rising edge or rising edge aligns with trailing edge, if rising edge aligns with rising edge (being that active and standby synchro system clock t1 and mainboard transmitting system clock t3 align), execution in step S7 then, otherwise execution in step S8;
Step S7: the time-delay Δ t that outer transmitting system clock t2 is set;
Particularly, suppose that the time-delay of active and standby synchro system clock t1 is t at this moment
1, the time-delay to plate transmitting system clock t3 input FPGA that receives from external transmitting system clock to the standby plate of the PLL (Phase Locked Loop) of main board output is t
2, the clock cycle is T, then the time-delay of external transmitting system clock t2 is provided with Δ t to be:
Δt＝t
1-t
2 (t
1-t
2＞0)
Or Δ t=t
1-t
2+ T (t
1-t
2＜0)
So just can guarantee that the system clock of standby plate is synchronized with the system clock of main board, a period of time after the Phase synchronization, clock just can active and standbyly switch.
Step S8: return step S1 behind the time-delay minimizing x (or increasing x) with active and standby synchro system clock t1.
Among the above-mentioned steps S6, think when meeting any in the following condition active and standby synchro system clock t1 and mainboard transmitting system clock t3 the alignment, this moment state transition graph as shown in Figure 3:
(a1) if be in state 1 in the last measurement period K, promptly by transferring to state 3 behind the time-delay minimizing x of state 1 with active and standby synchro system clock t1;
(a2) if be in state 2 in the last measurement period K, promptly by transferring to state 3 behind the time-delay increase x of state 2 with active and standby synchro system clock t1;
(a3) if current be first measurement period K, then the time-delay with active and standby synchro system clock t1 increases x, if statistics is a state 1 in the next measurement period K, and reduces by time-delay and to transfer to state 2 or state 3 when the 3rd measurement period (i.e. transfer to state 2 or state 3) behind the x active and standby synchro system clock t1;
(a4) if current be first measurement period K, then the time-delay with active and standby synchro system clock t1 reduces x, if statistics is a state 2 in the next measurement period K, and increases by time-delay and to move on to state 2 or state 3 when the 3rd measurement period (i.e. transfer to state 2 or state 3) behind the x active and standby synchro system clock t1.
(a3) or (a4) judge that active and standby synchro system clock t1 and mainboard transmitting system clock t3 finish to align in first measurement period if in a manner described, and when being not state 3 by the follow-up state of adjusting t1 when the 3rd measurement period finishes, need to continue to add up the state of t1 by above flow process, decidable t1 aligns with t3 once more when the state that counts on t1 once more is state 3, does not need further to judge and adjust.
Among the above-mentioned steps S6, the measurement period of establishing when the forward position alignment is i cycle, and the mode that whether active and standby synchro system clock t1 and mainboard transmitting system clock t3 align when judging i measurement period end can also be any in the following mode:
(b1) time-delay with active and standby synchro system clock t1 reduces x, return step S1 afterwards, if the state of the t1 that adds up in the next measurement period (i.e. i+1 measurement period) is a state 2, and with t1 set by step the mode of the S5 state of adjusting afterwards t1 in i+2 the measurement period be state 1 or state 3;
(b2) time-delay with active and standby synchro system clock t1 increases x, return step S1 afterwards, if the state of the t1 that adds up in the next measurement period (i.e. i+1 measurement period) is a state 1, and with t1 set by step the mode of the S4 state of adjusting afterwards t1 in i+2 the measurement period be state 2 or state 3.
(b1) or (b2) judge that active and standby synchro system clock t1 and mainboard transmitting system clock t3 have alignd in i measurement period end if in a manner described, and when being not state 3 by the follow-up state of adjusting t1 when i+2 measurement period finishes, need to continue to add up the state of t1 by above flow process, decidable t1 aligns with t3 once more when the state that counts on t1 once more is state 3, does not need further to judge and adjust.
One of ordinary skill in the art will appreciate that all or part of step in the said method can instruct related hardware to finish by program, described program can be stored in the computer-readable recording medium, as read-only memory, disk or CD etc.Alternatively, all or part of step of the foregoing description also can use one or more integrated circuits to realize.Correspondingly, each the module/unit in the foregoing description can adopt the form of hardware to realize, also can adopt the form of software function module to realize.The present invention is not restricted to the combination of the hardware and software of any particular form.
The present invention is not limited to above-mentioned execution mode, anyly is familiar with this operator, without departing from the spirit and scope of the present invention, all should drop within protection scope of the present invention.
Claims (12)
1. method that master/backup clock is synchronous comprises:
Add up the state of active and standby synchro system clock t1, when the state of described t1 is the time-delay that reduces t1 when lagging behind mainboard transmitting system clock t3, when the state of described t1 is the time-delay that increases t1 when being ahead of mainboard transmitting system clock t3, align with mainboard transmitting system clock t3 until adjusting to t1.
2. the method for claim 1 is characterized in that, described method is specially:
In each measurement period K, add up the state of described active and standby synchro system clock t1, when described measurement period K finishes, if the state of t1 is to lag behind t3 then the time-delay of described t1 to be reduced x, if the state of t1 is to be ahead of t3 then the time-delay of described t1 to be increased x, enter next measurement period then;
Described x is for adjusting step-length.
3. method as claimed in claim 2 is characterized in that:
In each measurement period K, utilize active and standby synchro system clock t1 that the signal of the system clock t3 of mainboard transmission is repeatedly sampled, during each the sampling, when active and standby synchro system clock t1 is ahead of plate transmitting system clock t3, the value of slave board counter is subtracted 1, when active and standby synchro system clock t1 lags behind plate transmitting system clock t3, the value of slave board counter is added 1;
When measurement period K finishes, if the value of described counter judges then that greater than default high threshold the state of t1 is for lagging behind t3, if being lower than default low threshold, the value of described counter judges that then the state of t1 is for being ahead of t3, if the value of described counter judges then that between high low threshold the edge of described t1 aligns with the edge of t3.
4. method as claimed in claim 3 is characterized in that:
When the edge of described t1 aligns with the edge of t3, if judge active and standby synchro system clock t1 and mainboard transmitting system clock t3 alignment when meeting in the following condition any:
(a1) if be in state 1 in the last measurement period K, promptly by transferring to state 3 behind the time-delay minimizing x of state 1 with active and standby synchro system clock t1;
(a2) if be in state 2 in the last measurement period K, promptly by transferring to state 3 behind the time-delay increase x of state 1 with active and standby synchro system clock t1;
(a3) if current be first measurement period K, then the time-delay of active and standby synchro system clock t1 is increased x, if statistics is a state 1 in the next measurement period K, and turn back to state 3 after reducing x by time-delay with active and standby synchro system clock t1;
(a4) if current be first measurement period K, then the time-delay of active and standby synchro system clock t1 is reduced x, if statistics is a state 2 in the next measurement period K, and turn back to state 3 after increasing x by time-delay with active and standby synchro system clock t1.
5. method as claimed in claim 3 is characterized in that:
If when the measurement period of forward position alignment is i cycle, if active and standby synchro system clock t1 and mainboard transmitting system clock t3 align when judging i measurement period end when meeting in the following condition any:
(b1) time-delay with active and standby synchro system clock t1 reduces x, return step S1 afterwards, if the state of the t1 that adds up in the next measurement period (i.e. i+1 measurement period) is a state 2, and with t1 set by step the mode of the S5 state of adjusting afterwards t1 in i+2 the measurement period be state 1 or state 3;
(b2) time-delay with active and standby synchro system clock t1 increases x, return step S1 afterwards, if the state of the t1 that adds up in the next measurement period (i.e. i+1 measurement period) is a state 1, and with t1 set by step the mode of the S4 state of adjusting afterwards t1 in i+2 the measurement period be state 2 or state 3.
6. the method for claim 1 is characterized in that, described method also comprises:
If the time-delay of described active and standby synchro system clock t1 was t when active and standby synchro system clock t1 alignd with mainboard transmitting system clock t3
1, the time-delay to plate transmitting system clock t3 input field programmable gate array that receives from external transmitting system clock to the slave board of the PLL of main board output is t
2, the clock cycle is T, and the time-delay Δ t of external transmitting system clock t2 is set in such a way:
Work as t
1-t
2＞0 o'clock, described Δ t=t
1-t
2Work as t
1-t
2＜0 o'clock, described Δ t=t
1-t
2+ T.
7. the device that master/backup clock is synchronous comprises the field programmable gate array that is positioned at slave board; It is characterized in that:
Described field programmable gate array comprises control module, be used to add up the state of active and standby synchro system clock t1, when the state of described t1 is the time-delay that reduces described t1 when lagging behind mainboard transmitting system clock t3, when the state of described t1 is the time-delay that increases described t1 when being ahead of mainboard transmitting system clock t3, align with mainboard transmitting system clock t3 until adjusting to described t1.
8. device as claimed in claim 7 is characterized in that:
Described control module is alignd t1 and is meant with t3, in each measurement period K, add up the state of described active and standby synchro system clock t1, when described measurement period K finishes, if the state of t1 is to lag behind t3 then the time-delay of described t1 to be reduced x, if the state of t1 is to be ahead of t3 then the time-delay of described t1 to be increased x, enter next measurement period then;
Described x is for adjusting step-length.
9. device as claimed in claim 8 is characterized in that:
Described field programmable gate array also comprises d type flip flop and counter;
Described d type flip flop is used for when the active and standby synchro system clock t1 that receives lags behind t3, to the signal of counter output expression t1 hysteresis, and when the active and standby synchro system clock t1 that receives is ahead of t3, to the leading signal of counter output expression t1;
Described counter, be used in each measurement period K when reception be input as high signal the time value of counter added 1, the value with counter when being input as low signal subtracts 1;
Described control module reads the value of counter when each measurement period K finishes, if the value of described counter judges then that greater than default high threshold the state of t1 is for lagging behind t3, if being lower than default low threshold, the value of described counter judges that then the state of t1 is for being ahead of t3, if the value of described counter judges then that between high low threshold the edge of described t1 aligns with the edge of t3.
10. device as claimed in claim 9 is characterized in that:
Described control module also is used for when the edge of described t1 aligns with the edge of t3, if judge active and standby synchro system clock t1 and mainboard transmitting system clock t3 alignment when meeting in the following condition any:
(1) if is in state 1 in the last measurement period K, promptly by transferring to state 3 behind the time-delay minimizing x of state 1 with active and standby synchro system clock t1;
(2) if be in state 2 in the last measurement period K, promptly by transferring to state 3 behind the time-delay increase x of state 1 with active and standby synchro system clock t1;
(3) if current be first measurement period K, then the time-delay of active and standby synchro system clock t1 is increased x, if statistics is a state 1 in the next measurement period K, and turn back to state 3 after reducing x by time-delay with active and standby synchro system clock t1;
(4) if current be first measurement period K, then the time-delay of active and standby synchro system clock t1 is reduced x, if statistics is a state 2 in the next measurement period K, and turn back to state 3 after increasing x by time-delay with active and standby synchro system clock t1.
11. device as claimed in claim 9 is characterized in that:
If when the measurement period of forward position alignment is i cycle, active and standby synchro system clock t1 and mainboard transmitting system clock t3 alignd when described control module also was used for judging i measurement period end when meeting any of following condition:
(b1) time-delay with active and standby synchro system clock t1 reduces x, return step S1 afterwards, if the state of the t1 that adds up in the next measurement period (i.e. i+1 measurement period) is a state 2, and with t1 set by step the mode of the S5 state of adjusting afterwards t1 in i+2 the measurement period be state 1 or state 3;
(b2) time-delay with active and standby synchro system clock t1 increases x, return step S1 afterwards, if the state of the t1 that adds up in the next measurement period (i.e. i+1 measurement period) is a state 1, and with t1 set by step the mode of the S4 state of adjusting afterwards t1 in i+2 the measurement period be state 2 or state 3.
12. device as claimed in claim 6 is characterized in that:
Described control module also be used for when described t1 with after t3 aligns, the time-delay Δ t of external transmitting system clock t2 is set in the following manner:
If the time-delay of described active and standby synchro system clock t1 was t when active and standby synchro system clock t1 alignd with mainboard transmitting system clock t3
1, the time-delay to plate transmitting system clock t3 input field programmable gate array that receives from external transmitting system clock to the slave board of the PLL of main board output is t
2, the clock cycle is T, works as t
1-t
2＞0 o'clock, Δ t=t
1-t
2, work as t
1-t
2＜0 o'clock, Δ t=t
1-t
2+ T.
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| CN2010102124161A CN102300235A (en) | 2010-06-28 | 2010-06-28 | Device and method for synchronizing main clock and standby clock |
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| CN107483170A (en) * | 2017-07-14 | 2017-12-15 | 天津大学 | A kind of binary baseband signal bit synchronization Clock Extraction and digital display method |
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