CN102299171A - Silicon nanowire apparatus compatible with complementary metal oxide semiconductor (CMOS) process and manufacturing method thereof - Google Patents
Silicon nanowire apparatus compatible with complementary metal oxide semiconductor (CMOS) process and manufacturing method thereof Download PDFInfo
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- CN102299171A CN102299171A CN2011102662436A CN201110266243A CN102299171A CN 102299171 A CN102299171 A CN 102299171A CN 2011102662436 A CN2011102662436 A CN 2011102662436A CN 201110266243 A CN201110266243 A CN 201110266243A CN 102299171 A CN102299171 A CN 102299171A
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Abstract
The invention relates to a silicon nanowire apparatus compatible with a complementary metal oxide semiconductor (CMOS) process and a manufacturing method thereof. The height of silicon nanowire of the silicon nanowire apparatus is reduced, the aspect ratio of the silicon nanowire is reduced and the cross contact area of the silicon nanowire is increased. The manufacturing method of the silicon nanowire apparatus comprises the following steps of: forming the silicon nanowire and a source/drain region on a substrate; forming a metal welding pad and a contact hole sequentially according to the source/drain region; and releasing the silicon nanowire apparatus by using a dry method to expose the silicon nanowire. Compared with the conventional silicon nanowire apparatus, the silicon nanowire apparatus has the advantages that: the influence of a side wall on the silicon nanowire apparatus is greatly reduced; the effective contact surface of the silicon nanowire apparatus is increased, so that the influenced rate of the silicon nanowire apparatus is increased; and the width of the silicon nanowire is increased, so that requirements of the manufacturing method of the silicon nanowire apparatus on photoetching and etching processes are greatly reduced and the production cost is effectively reduced.
Description
Technical field
The present invention relates to a kind of biochip, silicon nanowires device of particularly a kind of and CMOS process compatible and preparation method thereof.
Background technology
In recent years, be accompanied by continuous exploration and the research of people, have the material of one-dimensional nano structure,, attracted more and more people's eyeball as silicon nanowires (SiNW, Silicon Nanowire) to field of nanometer technology.Silicon nanowires has characteristics such as significant quantum effect, super large surface to volume ratio, in fields such as MOS device, transducers good prospects for application is arranged.
The silicon nanowires device as a kind of biochip elementary cell, just is applied to the biological detection field more and more widely.People such as Kuan-1Chen have delivered one piece and have been entitled as the article of " Silicon nanowire field-effect transistor-based biosensors for biomedical diagnosis and cellular recoding investigation ", the manufacture craft of wherein having introduced the application of silicon nanowires and having proposed to make the silicon nanowires device at 2011 the 6th phase 131-154 pages or leaves of nanometer magazine today (Nano Today).As Fig. 1 a, shown in Fig. 1 b, silicon nanowires device of the prior art, be to have the source/drain region 3 that forms silicon nanowires 4 on the polysilicon substrate 1 of silicon dioxide layer 2 and be connected respectively with silicon nanowires 4 two ends on the surface and constitute, wherein, silicon nanowires normally covers layer of oxide layer and forms on polysilicon or monocrystalline silicon surface, its main operation principle is similar to MOSFET, utilize oxide layer on polysilicon or the monocrystalline silicon as grid oxygen, because the biomolecule group of adsorbing on it all has electric charge usually, this electric charge can be similar to the potential regulating of MOSFET to silicon nanowires, and then influence the conductive characteristic of silicon nanowires, by discerning specific biomolecule group to the monitoring of this conductive characteristic.
In the silicon nanowires device making technics of prior art; after forming silicon nanowires and source/drain region on the substrate, adopt insulating medium layer to cover on the silicon nanowires, so that follow-up; for example, on source/drain region, form metal pad and to offer in the technology of contact hole the protection silicon nanowires injury-free.After making such as above-mentioned metal pad, contact hole finish, need to remove the insulating medium layer on the silicon nanowires, to discharge the silicon nanowires zone, make its directly contact measured liquid.Fig. 2 is the profile before the silicon nanowires device release process, because this step release process is normally after whole silicon nanowires device technology is finished, after promptly all metal pads are finished, this just makes release process can't enter the relevant base station of preceding road technology, because the metal on the metal pad can bring pollution to preceding working procedure, so can't use the selection of preceding working procedure to carry out operation than very high hot phosphoric acid base station, and additionally purchase new hot phosphoric acid base station, this can increase production cost greatly.Do not increasing under the condition of cost, select for use dry method to discharge (being dry etching), Fig. 3 is the profile behind the dry etching in the prior art, its weak point is: because dry etching can't be accomplished high selectivity isotropic etching completely, so can on silicon nanowires 4, form side wall 41 (spacer), after silicon nanowires 4 is coated with side wall 41, then can't form effective the contact with testing liquid, it is remaining that what can effectively contact with testing liquid mainly is the end face of silicon nanowires 4, yet, because the depth-width ratio of the silicon nanowires 4 of prior art approached 1: 1, it is very little to make the total surface area of top surface area and silicon nanowires compare shared ratio, thereby significantly reduced effective contact area of silicon nanowires and testing liquid, and then reduced the area that influenced by biomolecule group, reduced the influenced rate of silicon nanowires device thus, wherein, influenced rate is meant the ratio of the surface area that is subjected to the silicon that biomolecule group influences and the volume of silicon.
Summary of the invention
The purpose of this invention is to provide a kind of silicon nanowires device, to improve the influenced rate of silicon nanowires device.
Technical solution of the present invention is that the structure of silicon nanowires has been done the adjustment that reduces height, increases width, depth-width ratio is descended, making the total surface area of top surface area and silicon nanowires compare shared ratio increases greatly, and then the influence that is subjected to side wall of silicon nanowires device reduces greatly, contact-making surface is influenced by side wall hardly, it is big that thereby the influenced rate of silicon nanowires device becomes, and realization of the present invention comprises following scheme:
The silicon nanowires device comprises the silicon nanowires and the source/drain region that are formed on the substrate, and described silicon nanowires links to each other with described source/drain region, and its special character is that the depth-width ratio of described silicon nanowires is 1: 3-1: 6.
As preferably: the height of described silicon nanowires is 20-30nm.
As preferably: described silicon nanowires device comprises two source/drain regions, lays respectively at the both sides of described silicon nanowires.
The present invention also provides the manufacture method of described silicon nanowires device, comprises the steps:
Form silicon nanowires and source/drain region on substrate, described silicon nanowires links to each other with described source/drain region, and the depth-width ratio of described silicon nanowires is 1: 3-1: 6;
Protective mulch on silicon nanowires;
Adopt standard CMOS process, on source/drain region, form metal pad successively and be communicated to the contact hole of metal pad;
Adopt dry etch process, remove the protective layer on the silicon nanowires, expose silicon nanowires.
As preferably: the height of described silicon nanowires is 20-30nm.
As preferably: the described step that forms silicon nanowires and source/drain region on substrate comprises
Adopt thermal oxidation process, on substrate, form silicon dioxide layer;
Deposit spathic silicon layer and carry out light dope on silicon dioxide layer;
Described polysilicon layer is adopted photoetching, etching, form silicon nanowires and source/drain region;
Adopt thermal oxidation process, form oxide-film on the surface at silicon nanowires and source/drain region.
As preferably: after adopting photoetching, etching, forming the step in silicon nanowires and source/drain region, also comprise and adopt photoetching, ion implantation technology that heavy doping is carried out in source/drain region.
As preferably: described on silicon nanowires the step of protective mulch comprise the employing deposition process, deposition one deck oxide covers silicon nanowires and source/drain region as described protective layer.
As preferably: described employing standard CMOS process, the step that forms metal pad and contact hole on source/drain region successively comprises deposition first oxide layer, adopt photoetching, etching to form through hole, in through hole, fill metal and form metal level, adopt photoetching, etching to form metal pad, deposition second oxide layer and silicon nitride passivation on metal pad adopt photoetching, etching to form contact hole.
As preferably: described employing standard CMOS process also comprises silicon nitride passivation, second oxide layer and first oxide layer of removing above the silicon nanowires in the step that forms metal pad and contact hole on source/drain region successively.
Compared with prior art, the present invention has done the structure of silicon nanowires and has reduced height, increase the adjustment of width, depth-width ratio is descended, making the total surface area of top surface area and silicon nanowires compare shared ratio increases greatly, and the cumulative volume of silicon nanowires is almost constant, make the silicon nanowires device reduced greatly by the influence of side wall, effectively contact area is influenced by side wall hardly, it is big that thereby the influenced rate of silicon nanowires device becomes, simultaneously because the increase of the width of silicon nanowires, greatly reduce and make of the requirement of silicon nanowires device, effectively reduce production cost for photoetching and etching technics.
Description of drawings
Fig. 1 a is a kind of silicon nanowires device schematic top plan view.
Fig. 1 b is the A-A cross-sectional schematic of Fig. 1 a.
Fig. 2 is the profile before the prior art silicon nanowires release process.
Fig. 3 is the profile behind the prior art silicon nanowires release process.
Fig. 4 is the process chart of silicon nanowires device of the present invention.
Fig. 5-Fig. 7 is the profile in each processing step of silicon nanowires device of the present invention.
Embodiment
The present invention is further detailed in conjunction with the accompanying drawings below:
A lot of details have been set forth in the following description so that fully understand the present invention.But the present invention can implement much to be different from alternate manner described here, and those skilled in the art can do similar popularization under the situation of intension of the present invention, so the present invention is not subjected to the restriction of following public concrete enforcement.
Secondly, the present invention utilizes schematic diagram to be described in detail, when the embodiment of the invention is described in detail in detail; for ease of explanation; the profile of expression device architecture can be disobeyed general ratio and be done local the amplification, and described schematic diagram is example, and it should not limit the scope of protection of the invention at this.The three dimensions size that in actual fabrication, should comprise in addition, length, width and the degree of depth.Silicon nanowires device profile map only drawn in a simplified manner part silicon nanowires and a source/drain region among the present invention, those skilled in the art can do similar popularization under the situation of intension of the present invention.
See also the manufacture craft flow chart of silicon nanowires device shown in Figure 4, and cooperate with reference to Fig. 5～7, silicon nanowires device manufacture method of the present invention comprises the steps:
See also Fig. 3, shown in Figure 7, the structure of the silicon nanowires of prior art as shown in Figure 3, depth-width ratio is about 1: 1, the height of silicon nanowires is 30-80nm, in the present embodiment, as shown in Figure 7, structure to silicon nanowires is improved, reduced the height of silicon nanowires, the height of silicon nanowires is 20-30nm, and increased the width of silicon nanowires, and the depth-width ratio of improved silicon nanowires is 1: 3-1: 6, and make the horizontal contact-making surface shown in Fig. 7 (being top surface area) increase greatly than the contact area of prior art silicon nanowires device among Fig. 3, and the volume of silicon nanowires is almost constant, when contacting with testing liquid, the surface area that is subjected to the silicon that biomolecule group influences obviously increases with the ratio of the volume of silicon, and therefore silicon nanowires device of the present invention is compared influenced rate and become big with the nano-wire devices of prior art structure.
The manufacture craft of described silicon nanowires device is as follows:
In step 101, on substrate, form silicon nanowires and source/drain region.
As shown in Figure 5, adopt thermal oxidation technology to generate silicon dioxide layer 2 on substrate 1, deposit spathic silicon layer and carry out light dope on silicon dioxide layer 2 adopts the reactive ion etching polysilicon layer with formation source/drain region 3 and silicon nanowires 4.As preferably, also can may further comprise the steps after in step 101, adopting reactive ion etching to form source/drain region 3 and silicon nanowires 4 steps: adopt photoetching, ion implantation technology, heavy doping is carried out in source/drain region 3, thus the contact resistance in reduction source/drain region 3.Follow thermal oxide growth layer oxide film 40 on source/drain region 3 and silicon nanowires 4, described oxide-film 40 is a silicon dioxide.
In step 102, adopt depositing operation, deposition one deck oxide 5 covers on silicon nanowires 4 and the source/drain region 3 as protective layer, and 5 pairs of silicon nanowires of described oxide have protective effect, and described oxide 5 is a silicon dioxide.
In step 103, on source/drain region 3, form metal pad 7 successively and be connected to the contact hole of metal pad 7.
As shown in Figure 6: deposition first oxide layer 61 on oxide 5, adopt photoetching, etching to form through hole in the source/drain region 3 of described device, in through hole, fill metal and form metal level, adopt photoetching, etching sheet metal to form metal pad 7, described metal pad 7 is an aluminium welding pad, deposition second oxide layer 62 and silicon nitride passivation 63 on metal pad 7 adopt photoetching, etching to form contact hole, and described oxide layer 61,62 is a silica.Described silicon nanowires device is after metal pad 7 and contact hole are finished; be coated with protective layer (oxide 5), oxide layer 61,62 and silicon nitride passivation 63 on the silicon nanowires 4; need discharge it; thereby in step 104; adopt dry etching; remove silicon nitride passivation 63, oxide layer 61,62 and the protective layer (oxide 5) of silicon nanowires 4 tops, thereby expose described silicon nanowires 4.
Profile after silicon nanowires device of the present invention discharges, as shown in Figure 7.When the silicon nanowires device is carried out dry etching, because dry etching can't be accomplished high selectivity isotropic etching completely, so can on silicon nanowires 4, form side wall 41.The present invention has done the height that reduces silicon nanowires 4 to silicon nanowires 4 structures of prior art, increase the improvement of the width of silicon nanowires 4, the proportion that makes the lateral area of silicon nanowires 4 account for total area reduces, even therefore there is side wall 41, also can not cause effective contact area of silicon nanowires to descend greatly, it is minimum to make that the influence of 41 pairs of silicon nanowires of side wall drops to, so, compared with prior art, the influenced rate of silicon nanowires device of the present invention can not produce decay significantly because of side wall.
The above only is preferred embodiment of the present invention, and all equalizations of being done according to claim scope of the present invention change and modify, and all should belong to the covering scope of claim of the present invention.
Claims (10)
1. the silicon nanowires device with the CMOS process compatible comprises the silicon nanowires and the source/drain region that are formed on the substrate, and described silicon nanowires links to each other with described source/drain region, it is characterized in that: the depth-width ratio of described silicon nanowires is 1: 3-1: 6.
2. the silicon nanowires device of according to claim 1 and CMOS process compatible, it is characterized in that: the height of described silicon nanowires is 20-30nm.
3. the silicon nanowires device of according to claim 1 and CMOS process compatible, it is characterized in that: described silicon nanowires device comprises two source/drain regions, lays respectively at the both sides of described silicon nanowires.
4. manufacture method with the silicon nanowires device of CMOS process compatible may further comprise the steps:
Form silicon nanowires and source/drain region on substrate, described silicon nanowires links to each other with described source/drain region, and the depth-width ratio of described silicon nanowires is 1: 3-1: 6;
Protective mulch on silicon nanowires;
Adopt standard CMOS process, on source/drain region, form metal pad successively and be communicated to the contact hole of metal pad;
Adopt dry etch process, remove the protective layer on the silicon nanowires, expose silicon nanowires.
5. the manufacture method of the silicon nanowires device of according to claim 4 and CMOS process compatible, it is characterized in that: the height of described silicon nanowires is 20-30nm.
6. the manufacture method of the silicon nanowires device of according to claim 4 and CMOS process compatible is characterized in that: the described step that forms silicon nanowires and source/drain region on substrate comprises:
Adopt thermal oxidation process, on substrate, form silicon dioxide layer;
Deposit spathic silicon layer and carry out light dope on silicon dioxide layer;
Described polysilicon layer is adopted photoetching, etching, form silicon nanowires and source/drain region;
Adopt thermal oxidation process, form oxide-film on the surface at silicon nanowires and source/drain region.
7. the manufacture method of the silicon nanowires device of according to claim 6 and CMOS process compatible, it is characterized in that: adopting photoetching, etching, after forming the step in silicon nanowires and source/drain region, also comprise and adopt photoetching, ion implantation technology that heavy doping is carried out in source/drain region.
8. the manufacture method of the silicon nanowires device of according to claim 4 and CMOS process compatible; it is characterized in that: described on silicon nanowires the step of protective mulch comprise the employing deposition process, deposition one deck oxide covers silicon nanowires and source/drain region as described protective layer.
9. the manufacture method of the silicon nanowires device of according to claim 4 and CMOS process compatible, it is characterized in that: described employing standard CMOS process, the step that forms metal pad and contact hole on source/drain region successively comprises deposition first oxide layer, adopt photoetching, etching to form through hole, in through hole, fill metal and form metal level, adopt photoetching, etching to form metal pad, deposition second oxide layer and silicon nitride passivation on metal pad adopt photoetching, etching to form contact hole.
10. the manufacture method of the silicon nanowires device of according to claim 9 and CMOS process compatible, it is characterized in that: described employing standard CMOS process, silicon nitride passivation, second oxide layer and first oxide layer above the step that forms metal pad and contact hole on source/drain region successively also comprises the removal silicon nanowires.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2004003535A1 (en) * | 2002-06-27 | 2004-01-08 | Nanosys Inc. | Planar nanowire based sensor elements, devices, systems and methods for using and making same |
| CN101592627A (en) * | 2009-03-19 | 2009-12-02 | 苏州纳米技术与纳米仿生研究所 | The making integrated approach of multichannel high-sensitive biosensor |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2004003535A1 (en) * | 2002-06-27 | 2004-01-08 | Nanosys Inc. | Planar nanowire based sensor elements, devices, systems and methods for using and making same |
| CN101592627A (en) * | 2009-03-19 | 2009-12-02 | 苏州纳米技术与纳米仿生研究所 | The making integrated approach of multichannel high-sensitive biosensor |
Non-Patent Citations (3)
| Title |
|---|
| AJAY AGARWAL等: "Silicon nanowire sensor array using top-down CMOS technology", 《SENSORS AND ACTUATORS A》, vol. 145146, 28 December 2007 (2007-12-28), pages 207 - 213 * |
| KUAN-L CHEN等: "Silicon nanowire field-effect transistor-based biosensors for biomedical diagnosis and celluar recording investigation", 《NANO TODAY》, 8 March 2011 (2011-03-08), pages 131 - 154 * |
| YI CUI等: "Nanowire Nanosensors for Highly Sensitive and Selective Detection of Biological and Chemical Species", 《SCIENCE》, vol. 293, 17 August 2001 (2001-08-17), pages 1289 - 1292 * |
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