CN102299061B - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
- Publication number
- CN102299061B CN102299061B CN201010215854.3A CN201010215854A CN102299061B CN 102299061 B CN102299061 B CN 102299061B CN 201010215854 A CN201010215854 A CN 201010215854A CN 102299061 B CN102299061 B CN 102299061B
- Authority
- CN
- China
- Prior art keywords
- layer
- metal
- thickness
- work function
- oxygen uptake
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Abstract
The invention relates to the field of semiconductor manufacturing and provides a method for manufacturing a semiconductor device. The method comprises the following steps: providing a semiconductor substrate; forming an interface layer, a gate dielectric layer and a metal work function layer on the substrate; forming a diffusion barrier layer on the metal work function layer; forming a metal oxygen absorbing layer on the diffusion barrier layer; and carrying out thermal annealing treatment on the device so as to ensure the metal oxygen absorbing layer to absorb the oxygen in the interface layer to reduce the thickness of the interface layer and ensure the diffusion barrier layer to prevent the oxygen absorbing metals in the metal oxygen absorbing layer from being diffused into the metal work function layer. By adopting the method, the oxygen absorbing metals can be prevented from being diffused into the work function layer and/or gate dielectric layer while the thickness of the interface layer is reduced, thus reducing the equivalent oxide thickness under the premise of not affecting the threshold voltage of the device.
Description
Technical field
The present invention relates generally to the manufacture method of semiconductor device, specifically, relate to the threshold voltage control method of the gate regions of cmos device.
Background technology
Develop in decades in microelectric technique, logic chip manufacturer, in the time manufacturing MOS device, adopts SiO always
2as gate medium, adopt heavily doped polysilicon as gate material.But, along with constantly dwindling of characteristic size, the SiO in MOS transistor
2gate medium has closed on the limit.For example, in 65 nanometer technologies, SiO
2the thickness of gate medium has been down to 1.2 nanometers, is about 5 silicon atom layer thickness, if continue to dwindle, leakage current and power consumption will sharply increase again.The problems such as the doped with boron atom diffusion that meanwhile, caused by polygate electrodes, poly-Si depletion effect and too high gate resistance are also more and more serious by what become.For 32 nanometers and following technology generation, the problem such as leakage current and power consumption sharply increasing treats that by anxious the exploitation of new material, new technology and new device structure solves.
For reducing leakage current and power consumption, having a kind of improvement technology is to adopt " high k/ metal gate " structure.At present, the each main semiconductor company in international coverage has all taken up towards the exploitation of " the high k/ metal gate " technology in 32 nanometers and following technology generation.Intel discloses out and is adopting after high-k gate dielectric material, and the leakage current of device reduces to original 1/10th.But, in high k/ metal gate process, due to the annealing process that must adopt, cause boundary layer thickening in annealing process.But because the cmos device below 45nm exists very serious short-channel effect, need EOT (Equivalent OxideThickness, equivalent oxide thickness) gate medium that is no more than 1nm improves the control ability to raceway groove, so thick boundary layer SiO
2unacceptable.Especially in 32 nanometers and 22 nano-technology techniques, gate dielectric EOT even needs to reach 0.7 nanometer even below 0.5 nanometer, and common high k/ metal gate process median surface layer SiO
2thickness has just reached 0.5-0.7 nanometer.Therefore, how can effectively reduce EOT, particularly reduce interfacial layer thickness and become the problem with challenge.
Summary of the invention
The invention provides a kind of manufacture method of semiconductor device, described method comprises: Semiconductor substrate is provided; On described substrate, form boundary layer, gate dielectric layer and metal work function layer; On described metal work function layer, form diffusion impervious layer; On described diffusion impervious layer, form metal oxygen uptake layer; Described device is carried out to thermal anneal process, so that described metal oxygen uptake layer is absorbed the oxygen in boundary layer, make the thickness of boundary layer reduce and make described diffusion impervious layer stop the oxygen uptake metal in metal oxygen uptake layer to be diffused in described metal work function layer.
By adopting method of the present invention, on metal work function layer, form and there is the diffusion impervious layer of barrier effect and there is the metal oxygen uptake layer of absorbing the effect of oxygen in boundary layer, thereby can stop the oxygen in extraneous atmosphere in annealing process to enter boundary layer, prevent SiO
2the thickness of boundary layer increases, and utilizes oxygen removal techniques, makes script thickness reach the SiO of 0.5-1nm
2boundary layer thickness in annealing process is reduced to below 0.5 nanometer, remove even completely, effectively reduce the EOT of device, can utilize diffusion impervious layer to prevent that the oxygen uptake metal in metal oxygen uptake layer is diffused in work function layer and/or gate dielectric layer, thereby adversely affect the threshold voltage of device simultaneously.
Accompanying drawing explanation
Fig. 1 shows according to the flow chart of the manufacture method of the semiconductor device of the first embodiment of the present invention;
Fig. 2-5 show according to the schematic diagram of each fabrication stage of semiconductor device of the first embodiment of the present invention;
Embodiment
The present invention relates generally to the method for manufacturing semiconductor device.Disclosing below provides many different embodiment or example to be used for realizing different structure of the present invention.Of the present invention open in order to simplify, hereinafter the parts to specific examples and setting are described.Certainly, they are only example, and object does not lie in restriction the present invention.In addition, the present invention can be in different examples repeat reference numerals and/or letter.This repetition is in order to simplify and object clearly, itself do not indicate the relation between discussed various embodiment and/or setting.In addition, the various specific technique the invention provides and the example of material, but those of ordinary skills can recognize the property of can be applicable to of other techniques and/or the use of other materials.In addition, First Characteristic described below Second Characteristic it " on " structure can comprise that the first and second Characteristics creations are the direct embodiment of contact, also can comprise the embodiment of other Characteristics creation between the first and second features, such the first and second features may not be direct contacts.
According to embodiments of the invention, with reference to figure 1, Fig. 1 shows the flow chart of the manufacture method of semiconductor device according to the invention.At step S11, provide Semiconductor substrate, with reference to figure 2.In the present embodiment, substrate 101 comprises the silicon substrate (for example wafer) that is arranged in crystal structure, and substrate 101 can also comprise other basic semiconductor or compound semiconductors, such as Si, Ge, GeSi, GaAs, InP, SiC or diamond etc.For example, according to the known designing requirement of prior art (p-type substrate or N-shaped substrate), substrate 101 can comprise various doping configurations.In addition, alternatively, substrate 101 can comprise epitaxial loayer, can be by stress changes to strengthen the property, and can comprise silicon-on-insulator (SOI) structure.
At step S12, on described substrate 101, form boundary layer 102, gate dielectric layer 103 and metal work function layer 104.As shown in Figure 3.Can hot mode of growing form boundary layer 102 on described substrate 101, in embodiments of the present invention, boundary layer 102 is SiO
2, can be also oxynitride layer, its thickness is about 0.7nm.Then, on described boundary layer 102, form gate dielectric layer 103 and metal work function layer 104.Preferably, described gate dielectric layer 103 is high-k gate dielectric layer 103.Specifically, first, on described boundary layer 102, utilize ALD technology growth high-k gate dielectric layer 103, for example high K medium material HfO
2, HfSiO
x, HfZrO
x, HfLaO
x, HfLaON
x, LaAlO
x, La
2o
3or its combination, its thickness is about 0.5nm-3nm.Then, plated metal work function layer 104 on described high-k gate dielectric layer 103.Described metal work function layer can comprise metal, metallic compound and metal silicide and their combination thereof.In embodiments of the present invention, described metal work function layer 104 thickness are about 5nm to 50nm, can comprise HfN, TiN, TaN, MoN, TiAlN, MoAlN, HfCN
x, HfC, TiC, TaC, Ru, Re, Pt, RuO
2, TaRu
x, HfRu or its combination.
Then, at step S13, on described metal work function layer 104, form diffusion impervious layer 105 and metal oxygen uptake layer 106.As shown in Figure 4, can form described diffusion impervious layer 105 by the mode of deposition, its thickness is 1-20nm.Described diffusion impervious layer can comprise metal nitride, metal carbides or its combination, for example TiN, TaN, HfN, WN, WCN, HfC, TaC, TiC or its combination, but the invention is not restricted to above-mentioned material.When in subsequent step, described device being carried out in thermal anneal process process, described diffusion impervious layer 105 can stop the oxygen uptake metal in metal oxygen uptake layer 106 to be diffused into described metal work function layer 104, thereby adversely affects the threshold voltage of device.Forming in the step of metal oxygen uptake layer 106, can be by for example depositing or the method such as cosputtering, its thickness is about 1-10nm, is preferably 2nm.Described metal oxygen uptake layer 106 can comprise Ti, Hf, Al, Be, La, Y or its combination.When in subsequent step, described device being carried out in thermal anneal process process, the oxygen that described metal oxygen uptake layer 106 can be absorbed in boundary layer 102, reduces the thickness of boundary layer, thereby advantageously reduces the thickness of the equivalent oxide layer of device.
At step S14, described device architecture is carried out to thermal anneal process, so that the oxygen that described metal oxygen uptake layer 106 is absorbed in boundary layer 102 makes metal oxygen uptake layer 106 be oxidized to metal oxide, the thickness of boundary layer 102 is reduced, as shown in Figure 5.And described diffusion impervious layer 105 can stop the oxygen uptake metal in metal oxygen uptake layer 106 to be diffused into described metal work function layer 104, thereby avoids oxygen uptake metal to affect the threshold voltage of device.In the present embodiment, annealing temperature can be 300-800 ℃, is preferably 400 ℃, and the time is 1-300s, is preferably 60s.
Then, can carry out follow-up manufacturing process to described device, for example, can remove as required described metal oxygen uptake layer and diffusion impervious layer, and deposit new layer, then described device is carried out graphically, stacking to form grid, and form side wall at the stacking sidewall of grid, and formation source area and drain region, before forming source area and drain region, can first form source/leakage shallow junction region, thereby form final semiconductor device structure.
Above the method for utilizing metal oxygen uptake layer 106 to reduce boundary layer 102 thickness and to utilize diffusion impervious layer 105 to stop that oxygen uptake metal enters metal work function layer 104 is described.According to embodiments of the invention, on metal work function layer 104, form diffusion impervious layer 105 and metal oxygen uptake layer 106, diffusion impervious layer 105 is combined to form by metal nitride, metal carbides or its, for example TiN, TaN, HfN, WN, WCN, HfC, TaC, TiC or its combination, metal oxygen uptake layer 106 is formed by Ti, Hf, Al, Be, La or Y or its combination metal, then carry out thermal annealing, choose reasonable annealing time and temperature in annealing process, and, can select as required once to anneal or repeatedly annealing.Finally make to absorb the oxygen in boundary layer 102 in metal oxygen uptake layer 106, make metal oxygen uptake layer 106 be oxidized to metal oxide, the thickness of boundary layer 102 is reduced, and make described diffusion impervious layer 105 stop the oxygen uptake metal in metal oxygen uptake layer 106 to be diffused into described metal work function layer 104, thereby avoid oxygen uptake metal to affect the threshold voltage of device.Because selected metal generates gibbs free energy change much larger than Si, this means that the oxide of these metals is more stablized and easily forms than the oxide of silicon in boundary layer 102 simultaneously, therefore, in pyroprocess, boundary layer SiO
2in oxygen driven with these metal oxygen uptake layers 105 and formed metal oxide, thereby cause boundary layer 102 less thick, even disappear, effectively reduced EOT.In addition, metal oxygen uptake layer 105 is oxidized to after metal oxide, metal oxide can be unsatuated metal oxide, can stop the oxygen in extraneous atmosphere in the annealing process of subsequent technique to enter boundary layer 102, prevent or reduce the possibility of the thickness increase of boundary layer 102, thereby avoid the increase of EOT, also reduced EOT, controlled the threshold voltage of device simultaneously.
Although describe in detail about example embodiment and advantage thereof, be to be understood that the protection range in the case of not departing from spirit of the present invention and claims restriction, can carry out various variations, substitutions and modifications to these embodiment.For other examples, those of ordinary skill in the art should easily understand in keeping in protection range of the present invention, and the order of processing step can change.
In addition, range of application of the present invention is not limited to technique, mechanism, manufacture, material composition, means, method and the step of the specific embodiment of describing in specification.From disclosure of the present invention, to easily understand as those of ordinary skill in the art, for had or be about at present technique, mechanism, manufacture, material composition, means, method or the step developed later, wherein they carry out identical function or the identical result of acquisition cardinal principle of corresponding embodiment cardinal principle of describing with the present invention, can apply them according to the present invention.Therefore, claims of the present invention are intended to these technique, mechanism, manufacture, material composition, means, method or step to be included in its protection range.
Claims (1)
1. a manufacture method for semiconductor device, described method comprises:
Semiconductor substrate is provided;
On described substrate, form boundary layer, gate dielectric layer and metal work function layer;
On described metal work function layer, form diffusion impervious layer;
On described diffusion impervious layer, form metal oxygen uptake layer;
Described device is carried out to thermal anneal process, so that described metal oxygen uptake layer is absorbed the oxygen in boundary layer, make the thickness of boundary layer reduce and make described diffusion impervious layer stop the oxygen uptake metal in metal oxygen uptake layer to be diffused in described metal work function layer; The temperature of described thermal anneal process is 400 ℃; The time of described thermal anneal process is 60s;
Wherein, the thickness of described diffusion impervious layer is 20nm, in the group of described diffusion impervious layer column element from comprising, selects unit usually to form: TiN, TaN, HfN, WN, WCN, HfC, TaC, TiC or its combination; The thickness of described metal oxygen uptake layer is 1-10nm, selects unit usually to form: La, Y or its combination in the group of described metal oxygen uptake layer column element from comprising; The thickness of described gate dielectric layer is 0.5nm-3nm, selects unit usually to form: HfO in the group of described gate dielectric layer column element from comprising
2, HfSiO
x, HfZrO
x, HfLaO
x, HfLaON
x, LaAlO
x, La
2o
3or its combination; Described metal work function layer thickness is 50nm, selects unit usually to form: HfN, TiN, TaN, MoN, TiAlN, MoAlN, HfCN in the group of described metal work function layer column element from comprising
x, HfC, TiC, TaC, Ru, Re, Pt, RuO
2, TaRu
x, HfRu or its combination; Described boundary layer is SiO
2or oxynitride layer, its thickness is 0.7nm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010215854.3A CN102299061B (en) | 2010-06-22 | 2010-06-22 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010215854.3A CN102299061B (en) | 2010-06-22 | 2010-06-22 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102299061A CN102299061A (en) | 2011-12-28 |
| CN102299061B true CN102299061B (en) | 2014-05-14 |
Family
ID=45359386
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201010215854.3A Active CN102299061B (en) | 2010-06-22 | 2010-06-22 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102299061B (en) |
Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103456614A (en) * | 2012-06-04 | 2013-12-18 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method for semiconductor device with high-K metal gate |
| CN103531540B (en) * | 2012-07-02 | 2016-06-08 | 中国科学院微电子研究所 | Method, semi-conductor device manufacturing method |
| CN103632941A (en) * | 2012-08-23 | 2014-03-12 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device comprising metal gate, and preparation method thereof |
| CN105304476A (en) * | 2014-07-29 | 2016-02-03 | 中芯国际集成电路制造(上海)有限公司 | High-K gate dielectric layer formation method and semiconductor device |
| CN107437562B (en) * | 2016-05-27 | 2020-11-27 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor device |
| CN106711051A (en) * | 2016-11-16 | 2017-05-24 | 西安电子科技大学 | La-based medium material high-K metal gate structure based on Si substrate and preparation method thereof |
| CN106783974A (en) * | 2016-11-16 | 2017-05-31 | 西安电子科技大学 | Hafnium base aluminate high-K metal gate structure and preparation method based on Ge substrates |
| CN106531785A (en) * | 2016-11-16 | 2017-03-22 | 西安电子科技大学 | La-base medium material high-K metal gate structure based on Ge substrate, and preparation method |
| CN108155235B (en) * | 2016-12-02 | 2020-12-25 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN108321121B (en) * | 2017-01-18 | 2021-03-09 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing back gate type semiconductor device |
| CN108573868B (en) * | 2017-03-07 | 2020-12-22 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN110634952B (en) * | 2018-06-25 | 2023-06-13 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101661957A (en) * | 2008-08-26 | 2010-03-03 | 台湾积体电路制造股份有限公司 | Structure and method for a cmos device with doped conducting metal oxide as the gate electrode |
| CN101661883A (en) * | 2008-08-25 | 2010-03-03 | 台湾积体电路制造股份有限公司 | Manufacturing method for semiconductor element |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6921711B2 (en) * | 2003-09-09 | 2005-07-26 | International Business Machines Corporation | Method for forming metal replacement gate of high performance |
| US7154779B2 (en) * | 2004-01-21 | 2006-12-26 | Sandisk Corporation | Non-volatile memory cell using high-k material inter-gate programming |
| US20090152651A1 (en) * | 2007-12-18 | 2009-06-18 | International Business Machines Corporation | Gate stack structure with oxygen gettering layer |
-
2010
- 2010-06-22 CN CN201010215854.3A patent/CN102299061B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101661883A (en) * | 2008-08-25 | 2010-03-03 | 台湾积体电路制造股份有限公司 | Manufacturing method for semiconductor element |
| CN101661957A (en) * | 2008-08-26 | 2010-03-03 | 台湾积体电路制造股份有限公司 | Structure and method for a cmos device with doped conducting metal oxide as the gate electrode |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102299061A (en) | 2011-12-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102299061B (en) | Method for manufacturing semiconductor device | |
| CN102237398B (en) | Semiconductor structure and forming method thereof | |
| CN102222616B (en) | Manufacturing method of semiconductor device | |
| CN103378008B (en) | Bimetallic grid CMOS device and manufacture method thereof | |
| KR101789865B1 (en) | Semiconductor device with profiled work-function metal gate electrode and method of making | |
| CN102103994B (en) | Method of fabricating high-k/metal gate device | |
| CN101840862B (en) | Forming method of high-performance semiconductor device | |
| CN102129978B (en) | Method of forming a semiconductor device | |
| CN102064133B (en) | Method for making semiconductor device | |
| US8980718B2 (en) | PMOS transistors and fabrication method | |
| CN103854983B (en) | The manufacturing method of p-type MOSFET | |
| CN102110650A (en) | Semiconductor device and manufacturing method thereof | |
| CN102064176B (en) | Semiconductor device and manufacturing method thereof | |
| CN101661957A (en) | Structure and method for a cmos device with doped conducting metal oxide as the gate electrode | |
| US8178939B2 (en) | Interfacial barrier for work function modification of high performance CMOS devices | |
| CN102956454A (en) | Semiconductor structure and manufacturing method thereof | |
| CN102299077B (en) | Semiconductor device and manufacturing method thereof | |
| CN102110609B (en) | High-performance semiconductor device and forming method thereof | |
| CN102655094B (en) | A kind of semiconductor structure and manufacture method thereof | |
| CN102157553B (en) | Structure of asymmetrical semi-conductor and forming method thereof | |
| CN102254824A (en) | Semiconductor device and forming method thereof | |
| CN102194692A (en) | Production method for semiconductor device | |
| CN101740570B (en) | Complementary metal oxide semiconductor transistor device and manufacturing method thereof | |
| CN102931085A (en) | Semiconductor device and manufacturing method thereof | |
| CN103943492A (en) | Semiconductor device and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20201214 Address after: 510000 601, building a, 136 Kaiyuan Avenue, Huangpu District, Guangzhou City, Guangdong Province Patentee after: AoXin integrated circuit technology (Guangdong) Co.,Ltd. Address before: 100029 Beijing city Chaoyang District Beitucheng West Road No. 3 Patentee before: Institute of Microelectronics, Chinese Academy of Sciences |
|
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20220428 Address after: 510000 room 710, Jianshe building, No. 348, Kaifa Avenue, Huangpu District, Guangzhou, Guangdong Patentee after: Ruili flat core Microelectronics (Guangzhou) Co.,Ltd. Address before: 510000 601, building a, 136 Kaiyuan Avenue, Huangpu District, Guangzhou City, Guangdong Province Patentee before: AoXin integrated circuit technology (Guangdong) Co.,Ltd. |