CN102292774B

CN102292774B - Memory device and memory controller for controlling the same

Info

Publication number: CN102292774B
Application number: CN200880130151.1A
Authority: CN
Inventors: 佐藤贵彦
Original assignee: Fujitsu Semiconductor Ltd
Current assignee: Socionext Inc
Priority date: 2008-06-30
Filing date: 2008-06-30
Publication date: 2014-07-02
Anticipated expiration: 2028-06-30
Also published as: US20110128810A1; US8493400B2; EP2299449A1; KR20110015030A; JP5126360B2; JPWO2010001433A1; KR101226394B1; CN102292774A; WO2010001433A1

Abstract

A memory device includes: a memory cell array which stores two-dimensionally arranged data in a plurality of memory unit regions selected by an address; an internal address control unit which generates an internal address which selects a memory unit region according to an external address; and a decoder which decodes the internal address and selects a memory unit region. The plurality of memory unit regions store data arranged in a first direction from among two-dimensionally arranged data according to a least-significant bit group of the internal address and store data arranged in a second direction from among the two-dimensionally arranged data according to a most-significant bit group of the address. The internal address control unit successively generates an internal address corresponding to the scan direction according to a scan direction control signal which controls a plurality of scan directions including at least an oblique direction of the two-dimensionally arranged data.

Description

Storage arrangement and control the Memory Controller of this storage arrangement

Technical field

The present invention relates to storage arrangement and control the Memory Controller of this storage arrangement, relate in particular to storage arrangement and the Memory Controller thereof of preserving view data.

Background technology

Storage arrangement, especially jumbo SDRAM is widely used in the frame memory in image processing apparatus in semiconductor memory system.Preserve the frame memory of view data in order to support full HD picture by strong request high capacity.On the other hand, corresponding to the mpeg standard of compression and decompression processing with moving image, except the common memory access based on grating scanner, be also required to access at high speed the view data of arbitrary region.For example, in mpeg standard, comprise the processing of searching for the image consistent with the image of predetermined rectangular area in order to detect motion vector.The search processing of this motion vector need to be carried out the frequent and jumbo action of reading to frame memory.

The applicant has proposed patented claim for the storage arrangement with the access function that can support various image processing.For example, Japanese patent application laid is willing to No. 2006-345415 (application on Dec 22nd, 2006 (not yet open)).According to this application, storage arrangement has multiple storage cells region of selecting by Input Address, and according to predetermined memory mapped to multiple storage cell area stores view data, and read from the storage cell region of adjacency and export data and write input data to the storage cell region of adjacency according to the address of once input.

General SDRAM has burst and reads and function is write in burst, can conduct interviews efficiently to the storage area of continuation address.Thereby, in the case of preserve the memory mapped of view data of the raster scanning direction of two-dimensional image data in continuation address region, the access of two-dimensional image data being carried out to raster scanning has very high efficiency, very large as the bandwidth of the storer of accessible data amount check of unit interval.But the access of the storer carrying out to the direction different from raster scanning or region has reduced the access efficiency of storer, thereby has caused bandwidth of memory decline.

In order to eliminate the defect of above-mentioned general SDRAM, various schemes are proposed.For example following patent documentation 1～5 etc.

In patent documentation 1, record following content: to the view data of preserving in the identical row address in multiple memory banks region in storer and the region of column address in the vertical direction of two dimensional image, and by make multiple memory banks region activate the view data of accessing multirow simultaneously simultaneously.That is, preserve the view data of two dimensional image by the memory mapped based on special, and improved the access efficiency of multirow view data.

In patent documentation 2, record following content: video-ram (VRAM) has the DRAM of the view data of preserving two dimensional image and the data of DRAM carried out to the sequential access memory SAM of buffer control, sequential access memory SAM has can ascending order or the sequence address counter of descending counting, by making sequence address counter descending counting write image reversed left to right to DRAM.

In patent documentation 3, record following content: video-ram (VRAM) has the DRAM of the view data of preserving two dimensional image and the data of DRAM carried out to the sequential access memory SAM of buffer control, and the address counter of sequential access memory can be changed to addition pattern and subtraction mode, and can be from external setting-up Arbitrary Digit the additive value as address counter.

In patent documentation 4, record following content: the view data reading by image read-out, so that the mode that the address of adjacent view data becomes continuation address on sub scanning direction writes in video memory, and is read to processing for being carried out page mode by the view data of reverse read in length and breadth.

In patent documentation 5, record the video-ram identical with patent documentation 2.

Patent documentation 1: Japanese documentation JP 2005-116128 communique;

Patent documentation 2: Japanese documentation Unexamined Patent 8-190372 communique;

Patent documentation 3: Japanese documentation Unexamined Patent 6-243675 communique;

Patent documentation 4: Japanese documentation Unexamined Patent 5-334426 communique;

Patent documentation 2: Japanese documentation Unexamined Patent 5-54657 communique.

Summary of the invention

The problem that invention will solve

Above-mentioned patent documentation 1～5 all discloses the structure of the system with DRAM, does not relate to the inner structure of the DRAM that preserves view data.Thereby, these formerly technology cannot increase the bandwidth of DRAM of preserving view data.And on the other hand, just expecting to have a kind of storage arrangement that can support efficiently the special access of various image processing.

Therefore, the object of the present invention is to provide the storage arrangement that can carry out efficiently special access.

Another object of the present invention is to provide the storage arrangement that can carry out efficiently to the connected reference of any direction of two dimensional image.

In addition, a further object of the present invention is to provide the storage arrangement that can carry out efficiently the access in the random two-dimensional region of two dimensional image.

For the means of dealing with problems

Storage arrangement comprises: memory cell array, and it has multiple storage cells region of selecting by address, and two-dimensional array data are stored in described multiple storage cells region; Home address control part, it generates the home address for selecting described storage cell region based on external address; And code translator, home address is come and selects described storage cell region described in its decoding.The low-order bit group of described multiple storage cells region based on described home address stored the data on the first direction in the matrix that is arranged on described two-dimensional array data, and high order bit group based on described home address is stored the data in the second direction in the matrix that is arranged on described two-dimensional array data.And the direction of scanning control signal of the multiple direction of scanning that at least comprise vergence direction of described home address control part based on for controlling described two-dimensional array data, generates the home address corresponding with described direction of scanning successively.

Because the direction of scanning control signal of home address control part based on vergence direction comes to generate concurrently successively low level and high address, therefore can carry out burst access by adipping.In addition,, because home address control part generates low level and high address successively based on direction of scanning control signal, therefore can carry out burst access to the direction of scanning of specifying by direction of scanning control signal.

The Memory Controller of controlling above-mentioned storage arrangement comprises: burst direction determining portion, and position coordinates, portraitlandscape length and the degree of tilt of the rectangular area of its input regulation access object, and generate described direction of scanning control signal; Portion is sent in instruction, and it generates steering order and exports described steering order to described storage arrangement; And address sends portion, it generates external address and also exports described external address to described storage arrangement.And described direction of scanning control signal is exported to described storage arrangement.

Invention effect

Storage arrangement can carry out burst access to various directions for two-dimensional array data such as view data.

Brief description of the drawings

Fig. 1 is the structural drawing of image encoding system;

Fig. 2 A and Fig. 2 B are for the figure of image encoding system for the appointment of the access region of view data is described;

Fig. 3 illustrates the structure of the Memory Controller in present embodiment and the figure with the syndeton of storage arrangement;

Fig. 4 is the structural drawing of the storage arrangement in present embodiment;

Fig. 5 is the structural drawing of the storage arrangement in present embodiment;

Fig. 6 is the detail view of the memory mapped of Fig. 5;

Fig. 7 is the figure that the memory mapped in page region is shown;

Fig. 8 is the figure of the structure of the generation column address in the column address control part 41 illustrating in present embodiment;

Fig. 9 is the figure that the concrete example of direction of scanning control signal vaext is shown;

Figure 10 A and Figure 10 B are the figure that the example of the direction of motion of moving image is shown;

Figure 11 A and Figure 11 B illustrate the direction of motion of moving image and the figure of momental distribution;

Figure 12 is the figure that an example of the hunting zone of motion vector is shown;

Figure 13 A and Figure 13 B are the figure that an example of the access method of diamond-shaped area is shown;

Figure 14 is the figure that the scanning of vergence direction is described;

Figure 15 is the figure that the column address control part that carries out vergence direction scanning is shown;

Figure 16 is the detail view of carrying out the column address control part of vergence direction scanning;

Figure 17 is the detail view of carrying out the column address control part of vergence direction scanning;

The sequential chart of storage arrangement when Figure 18 is adipping scanning;

The sequential chart of storage arrangement when Figure 19 is adipping scanning;

Figure 20 is the figure that the horizontal scanning access in page region is shown;

Figure 21 is the figure that the vertical scanning access in page region is shown;

Figure 22 is the figure that the burst direction determining processing of being undertaken by Memory Controller is shown;

Figure 23 is the process flow diagram that the burst direction determining processing of being undertaken by Memory Controller is shown;

Figure 24 illustrates the figure that scans the example of access (burst access) to vertical direction;

Figure 25 is the structural drawing that scans the column address control part of access (burst access) to vertical direction;

Figure 26 is the sequential chart while scanning access to vertical direction;

Figure 27 is the sequential chart while scanning access to vertical direction;

Figure 28 illustrates the figure that scans another example of access (burst access) to vertical direction;

Figure 29 is the figure for the access while carrying out motion prediction is described;

Figure 30 is the figure for another access while carrying out motion prediction is described;

Figure 31 is for the figure of an access again while carrying out motion prediction is described;

Figure 32 is the structural drawing of the column address control part in searching for for the first time of two stage Search rules;

Figure 33 is the structural drawing of the column address control part in searching for for the first time of two stage Search rules;

Figure 34 is the sequential chart of the storage arrangement in searching for for the first time of two stage Search rules;

Figure 35 is the figure of the burst access of the rectangular area for present embodiment is described;

Figure 36 is the structural drawing of the column address control part while carrying out the burst access of the rectangular area in present embodiment;

Figure 37 is the structural drawing of a part for the high address generation unit while carrying out the burst access of rectangular area;

Figure 38 is the structural drawing of a part for the high address generation unit while carrying out the burst access of rectangular area;

Figure 39 is the sequential chart of the storage arrangement while carrying out the burst access of rectangular area;

Figure 40 is the structural drawing of a part for the low order address generation unit while carrying out inverted access;

Figure 41 is the figure that the example of the memory mapped with time shaft is shown.

Label declaration

10: storage arrangement 41: column address control part;

44: row address control part 47: memory core;

48: memory cell array 49: column decoder;

50: line decoder.

Embodiment

Below, with reference to the accompanying drawings embodiments of the present invention are described.But technical scope of the present invention is not limited to these embodiments, also comprise item and the equivalent thereof in claims, recorded.

[summary of image encoding system, Memory Controller, storage arrangement]

Fig. 1 is the structural drawing of image encoding system.The storage arrangement of present embodiment is corresponding to the frame memory 10 of the two-dimensional array data such as storing image data.Image encoding system has processing selecting portion 18 and encoding processor 20, processing selecting portion 18 is chosen in the processing in processing of the intra-prediction process of compressing in same frame and the inter prediction compressing on time-axis direction to input image data IMin, and encoding processor 20 is carried out the output image data CDout after coding the output encoder of input image data IMin based on the processing of choosing.And, the inter prediction handling part 16 that image encoding system has intra-prediction process portion 14 and comprises motion prediction process 17.In addition, intra-prediction process portion 14 and inter prediction handling part 16 are accessed frame memory 10 via Memory Controller 12 respectively, read or write for the view data of desired region in the view data being stored in frame memory.The result of processing selecting portion 18 based on intra-prediction process and the result of inter prediction processing are selected more suitably to process.Intra-prediction process portion 14 and inter prediction handling part 16 are via the frequent access frame memory 10 of Memory Controller 12.Therefore, frame memory 10 need to carry out the access of the view data to desired region by intra-prediction process portion 14 and inter prediction handling part 16 efficiently.

The processing that above-mentioned intra-prediction process and inter prediction processing example are carried out in this way in the compress technique of mpeg standard.In these are processed, carry out to high-frequency to writing of the view data of frame memory 10 and reading from the view data of frame memory 10.For example, in inter prediction is processed, carry out the motion prediction process that detects the direction of motion of identical image between two field pictures different on time-axis direction and obtain motion vector.In this motion prediction process, the image that need to search for the little rectangular area of 16 × 16 pixels moves to the processing of which position in the image of different frame, and repeats the action of reading to frame memory 10.

Fig. 2 A and Fig. 2 B are for the figure of image encoding system for the appointment of the access region of view data is described.In the case of the rectangular area access of Fig. 2 A, handling

part

14,16 provides the information of 0 ° of the height Lv of length L h, vertical direction of starting point coordinate (Xa, Ya), the horizontal direction of access region 22 and degree of tilt to Memory Controller 12.In addition, in the case of the diamond-shaped area access of Fig. 2 B, handling

part

14,16 provides the information of 45 ° of the length L v of length L h, second direction of starting point coordinate (Xa, Ya), the first direction of access region 22 and degree of tilt to Memory Controller 12.

Storage arrangement in present embodiment is constituted as and can accesses storage area as described above with higher efficiency (larger bandwidth).Storage arrangement for example can be according to the shape of access region and is happened suddenly and read and burst is write to the line direction of view data or column direction.And storage arrangement can be according to the degree of tilt of access region and read and burst is write to the burst that the vergence direction of expecting degree of tilt carries out view data.In addition, storage arrangement burst direction can also be switched to forward and oppositely in any direction.In addition, storage arrangement can also row system directive and column address based on once happen suddenly and read or happen suddenly to write the view data in two-dimentional access region continuously.

Fig. 3 illustrates the structure of the Memory Controller in present embodiment and the figure with the syndeton of storage arrangement.Memory Controller 12 is accepted providing of memory map information MAP from superior system such as the handling

parts

14,16 of Fig. 1, and this memory map information MAP is kept in register 34.Memory map information MAP is the information about how to preserve two-dimensional array data in storage arrangement 10.In addition, Memory Controller 12 is accepted the interview providing of data Acn is provided, and generates by memory register control part 35 the mode register setting data MRSdata that the mode register 40 in reply storage arrangement 10 is set.In this mode register setting data MRSdata, for example comprise paces information STEP or the width information WIDTH etc. while generating column address by column address control part 14.About these stride information STEP or width information WIDTH etc., will in the explanation of storage arrangement, be elaborated.

Memory Controller 12 is used to specify the information of starting point coordinate (Xa, Ya), degree of tilt SLOP, length L h and the Lv of access region from superior system input, by burst, best burst direction is judged by direction determining portion 32, and generates burst directional information (corresponding to vector address VA described later).And the address that should export to storage arrangement 10 is calculated based on starting point coordinate (Xa, Ya) and burst directional information by address computation portion 30.

Memory Controller 12 is for example, for example, for example, via instruction bus (4 bits) 38, address bus (12 bits) 37, data bus (32 bits) 36 and be connected with storage arrangement 10.Instruction send portion 33 generate various instructions, be used to specify activate ACT, precharge PRE, read RD, write WR, mode register arranges MRS etc. 4 command signal/CS ,/RAS ,/CAS ,/WE, and with appropriate timing output to instruction bus 38.Simultaneously, address is sent portion 31 and bank-address BA, row address RA, column address CA, vector address VA, mode register are arranged to data MRSdata etc. is exported address bus 37 to for instruction that the and instruction portion that sends is sent out.In addition, Memory Controller 12 is write data to data bus 36 outputs, inputs read data from data bus 36.

Memory Controller 12 to the control example of storage arrangement 10 as carried out as follows.Memory Controller 12, in the time switching on power or in other predetermined timing, arranges data MRSdata by mode register and exports together with mode register set command MRS.In response to this, storage arrangement 10 arranges data MRSdata to preservation mode register in mode register 40.In the time reading or writing action, Memory Controller 12 is exported bank-address BA and row address RA together in company with activation instruction ACT, makes the page region corresponding with bank-address BA and row address RA in storage arrangement 10 become state of activation.Afterwards, instruction RD is read in Memory Controller 12 companions or write command WD exports bank-address BA, column address CA and vector address VA together, thus the storage cell region of expecting in the page region of access in state of activation.Here, storage cell region is region selecteed by address, that have memory cell group, and described memory cell group is made up of multiple bits or multiple byte.

In addition, under burst mode, column address control part 41 in storage arrangement 10 is according to the column address CA and the vector address VA that come are provided, generate successively the internal column address corresponding with direction of scanning in access region, the memory core (not illustrating) that makes to have born of the same parents' array carries out the input and output of the data in the multiple storage cells region corresponding with direction of scanning continuously., storage arrangement 10, under burst mode, can read or write in response to row system directive (reading or writing) once the two-dimensional array data on direction of scanning arbitrarily continuously with column address.

In addition, in the time that direction of scanning is vergence direction, storage arrangement is by set paces information STEP and input vector address VA in mode register, can also carry out burst access to angle direction arbitrarily.In addition, in the time that access region is 2 dimensional region, by set width information WIDTH in mode register, in response to row system directive (reading or writing) and column address once, column address control part 14 can generate the column address corresponding with two-dimensional access region continuously, and storage arrangement 10 can read or write continuously to the data in two-dimensional access region.

Both there is the situation that is offered storage arrangement by Memory Controller multichannel in above-mentioned bank-address BA, row address AV, column address CA etc. (time-division), also exist by the non-multichannel of Memory Controller (non-time-division and in the lump) offer the situation of storage arrangement.

Fig. 4 is the structural drawing of the storage arrangement in present embodiment.As the explanation in Fig. 3, storage arrangement 10 is used to specify command signal/CS ,/RAS ,/the CAS ,/WE of instruction via longitudinal 38 inputs of instruction from Memory Controller, corresponding these instructions of instruction control part 40 come control model register 40, row timing control part 43, row timing control part 42.For example, in response to mode register set command MRS, instruction control part 40 arranges data MRSdata to setting the mode register being provided on address bus 37 in mode register 40.In addition,, in response to activation instruction ACT, instruction control part 40 is controlled row timing control part 43 and is activated action.In addition,, in response to reading or writing instruction RD, WD, instruction control part 40 is controlled row timing control part 42 and is read or write action.

Storage arrangement 10 from Memory Controller via address bus 37 Input Address signal A[11:0], outer row address raext is provided for row address control part 44 via line buffer 46, and outer array address caext is provided for column address control part 41 via column buffer 45.In addition, storage arrangement 10 from Memory Controller via private bus 39 or via a part of bit of address bus 37 input vector address VA[2:0], outside vector address vaext is provided for column address control part 41.And the control signal selcntext corresponding with being set in paces information in mode register 40 or width information is also provided for column address control part 41.

In addition, row address control part 44 generates internal rows address raint according to outer row address raext, and this internal rows address raint is offered to line decoder 50.Row address is for example made up of 12 bits.In addition, column address control part 41 generates internal column address caint, and this internal column address caint is offered to column decoder 49 based on outer array address caext, vector address vaest, control signal selcntext etc.For the address and the control signal that are provided to storage arrangement 10 from outside, in reference symbol, add " ext ".In addition, the address and the control signal that generate for the inside at storage arrangement 10 are added " int " in reference symbol.

Fig. 5 is the figure that an example of the memory mapped of the storage arrangement in present embodiment is shown.In Fig. 5, comprise that the view data in the image processing system of display device 1 is stored in storage arrangement 10.View data is made up of data such as the brightness signal Y of each pixel and the RGB GTG signals of colour difference signal Ca, Cb or each pixel, and each signal is for example made up of 8 bits (1 byte) data.

On the other hand, storage arrangement 10 has formed integrated circuit by SDRAM etc. conventionally on semiconductor substrate large capacity and semiconductor memory system at a high speed form.Such storage arrangement is that 4 memory bank Bank0～3 form by multiple memory banks, in Fig. 1, and each memory bank Bank0 has multiple BLK-0, and each has the memory cell MC of multiple word line WL, bit line BL and their crossover location.Although do not illustrate, memory cell comprises that its grid is connected to the MOS transistor on word line and is connected to the capacitor in this MOS transistor.In addition, in the example of Fig. 5,4 memory banks are corresponding with bank-address BA0～BA4, and word line WL is corresponding with row address RA0～RA7, and bit line BL is corresponding with column address CA0～CA127.

Select the word line WL in memory bank by the combination of bank-address BA and row address RA, select bit line BL by column address CA., visit the data of 4 byte BY0-3 by the combination of bank-address BA, row address RA and column address CA.Because 1 byte is made up of 8 bits, therefore, in access once, 4 bytes, the input and output terminal DQ that data of 4 × 8=32 bit are associated with storer go up and are read out or write.Conventionally, above-mentioned 1 byte data is corresponding to 8 one-bit data signal of pixel.

According to the memory mapped 2 shown in Fig. 5, the page region Page specifying by bank-address BA and row address RA is aligned to the matrix as the two-dimensional array data of view data.And as shown in magnification region PageE, 1 page region Page has 128 storage cell regions of specifying with column address CA0～127, the data of each storage cell area stores 4 byte BY0～3.The data of these 4 byte BY0～3 are transfused to output via input and output terminal DQ0～31 of 32 bits of storage arrangement.

Above-mentioned memory mapped 2 is suitable for making storage arrangement 10 high speed motion such as the SDRAM of multiple bank structure.As mentioned above, SDRAM is in response to the activation instruction being provided together with bank-address BA and row address RA, carry out and activate action, that is: drive selected word line in selected memory bank, export the data of memory cell to bit line, activate the sensor amplifier corresponding with bit line and amplify bit line current potential.Afterwards, SDRAM, in response to the instruction of reading being provided together with column address CA, carries out the action of reading from selected bit line sense data.Or SDRAM, after activating action, in response to the write command being provided together with column address CA and data writing, carries out the action of writing that writes data writing to selected bit line.Reading action or writing after action, carrying out the precharge action based on precharge instruction, again becoming to activate and move, read or write action.So, in SDRAM, each memory bank can independently activate action, reads action, write action.

According to the memory mapped 2 of Fig. 5, different bank-address BA0～3 are corresponded to the page region Page of adjacency up and down.That is, in the odd-numbered line of memory mapped 2, alternately configure bank-address BA0,1, in even number line, alternately configured bank-address BA2,3.And upper at the grating orientation (line direction) of memory mapped 2, row address RA0～7 are repeated the mode of twice with identical address and increased progressively, each row of memory mapped 2 with 4 row address RA0～3, RA4～7 repeatedly.

Fig. 6 is the details drawing of the memory mapped of Fig. 5.Relation between memory mapped 2, bank-address BA0 and BA1, row address RA and column address CA has been shown in Fig. 6.Bank-address BA0 and BA1 are with the binary number representation of " 0,1 ", and row address RA represents with the decimal number of " 0～K-1,0～L-1 ".As shown in Figure 6, in memory mapped 2, the multiple page region Pages corresponding with the matrix directions of the two-dimensional array data as view data based on bank-address BA and row address RA by corresponding.That is, lower memory body address BA0 and low level row address RA are corresponding to the page region Page of line direction, and higher memory body address BA1 and high-order row address RA are corresponding to the page region Page of column direction.

A part of the memory mapped 2E having amplified has been shown in Fig. 6.Identical with Fig. 5, the page region being listed as with the 2 adjacent row 2 that bold box is surrounded is corresponding to " BA0, RA0 ", " BA1, RA0 ", " BA2, RA0 ", " BA3, the RA0 " of bank-address and row address.And line direction is turned back at row address RAK-1 place.In addition, in each page of region, also have by column address CA and come corresponding multiple storage cells region.In Fig. 6, omit the occurrence of column address CA.

For example, when distribute the view data of 1920 × 1080 full HD sizes in storer time, if the information of 1 pixel is assumed to 8bit × 4 (GRB α), the data volume of 1 picture is 64Mbit.In the encoder of MPEG, frequently the view data of rectangular area is processed as mentioned above.Thereby, as shown in Figure 6, multiple pages of regions are mapped as to rectangle and contribute to improve access efficiency.And, by giving different bank-address by adjacent page region allocation, to 4 row addresses that page region allocation is identical in bold box, thus activate for a long time by needs action 4 memory bank regions are become after state of activation simultaneously, by change bank-address and column address in changing row system directive, the data of the memory cell of available short time access state of activation.

Fig. 7 is the figure that the memory mapped in page region is shown.In the example of Fig. 7,1 page region Page has the storage cell region MU (256 region) being listed as by 16 row 16 of column address A00～S007 selection.In figure, on each storage cell region MU, show column address CA00～CAff that 16 systems represent.The DQ interface of storage cell region MU and 32 bits is stored the data of 4 bytes (32 bit) accordingly.And, according to the memory mapped of Fig. 7, multiple storage cells region MU stores the data on the line direction that is arranged on two-dimensional array data based on low-order bit group CA-L (A00～A03) in column address, and stores the data on the column direction that is arranged on two-dimensional array data based on high order bit group CA-U (A04～A07) in column address.

Thus, in the time that the data (RGB α, 8 bits × 4=32 bit) of 1 pixel are concentrated preservation, in 1 storage cell region MU, preserve the data (RGB α) of 1 pixel.Thus, in the case, in 1 page region Page, preserve the view data of 16 × 16 pixels.

In addition,, in the time of the separated preservation of each data (8 bit) in the data (RGB α) of 1 pixel, in 1 storage cell region MU, preserve the view data of 4 pixels.In the case, if preserve the view data of the pixel that 1 row 4 is listed as in 1 storage cell region MU, in 1 page region Page, preserve the view data of 64 × 16 pixels.In addition,, if preserve the view data of the pixel that 2 row 2 are listed as in 1 storage cell region MU, in 1 page region, preserve the view data of 32 × 32 pixels.And, if preserve the view data of the pixel that 4 row 1 are listed as in 1 storage cell region MU, in 1 page region, preserve the view data of 16 × 64 pixels.Their difference is, Memory Controller is controlled based on memory mapped.

In the MU of the storage cell region of Fig. 7,16 systems for row address (CA00～CAff) represent.On the other hand, in low-order bit group CA-L (A00～A03), high order bit group CA-U (A04～A07), the column address A00～A03 of each 4 bits, A04～scale-of-two for A07 (0,1) represent.

[column address control part]

Fig. 8 is the figure of the structure of the generation column address in the column address control part 41 illustrating in present embodiment.Column address control part 41 is inputted outer array address caext<07:04>, the caext<03:00> of 8 bits, generate internal column address caint<07:04>, the caint<03:00> of 8 bits, and by this internal column address caint<07:04>, caint<03:00> offers in the column decoder in memory core.When set burst mode in mode register 40 time, column address control part 41 generates and exports the internal column address of the number of burst-length successively.

Column address control part 41 has: low order address generation unit 80, and it generates the low-order bit group caint<03:00> of internal column address; High address generation unit 84, it generates the high order bit group caint<07:04> of home address; And scalar/vector control circuit 88, its direction of scanning control signal vaext<02:00> based on two-dimensional array data controls the action of low order address generation unit 80 and high address generation unit 84, and this column address control part 41 generates the internal column address corresponding with the direction of scanning of direction of scanning control signal vaext<02:00> successively.In this example, low-order bit group and high order bit group are divided into each 4 bits, but are not limited to this, also can be divided into 2 bits and 6 bits, 3 bits and 5 bits.In the case, the ratio of the matrix in the storage cell region of the page shown in Fig. 7 in region will be according to high order bit number and low-order bit number and difference.

Low order address generation unit 80 has: 4 bit counter 81; Paces initialization circuit 82, it sets the paces number (fluctuation number of every 1 clock) of counter; And the width initialization circuit 83 of turning back, it sets the maximum count value (corresponding with the width of turning back) of counter.Paces initialization circuit 82 is selection circuit of selecting counting controling signal countlz to be input to which bit of counter, and it is selected according to the paces control signal selcntls (2 bit) setting in mode register 40.In addition, the width initialization circuit 83 of turning back is to select the counter that should export which bit to export the selection circuit as count end signal (a kind of carry signal) caintle, and it carrys out the bit of gated counter according to the width control signal selcntlw that turns back (2 bit) setting in mode register 40.

The same with low order address generation unit 80, high address generation unit 84 has: 4 bit counter 81; Paces initialization circuit 82, it sets the paces number (fluctuation number of every 1 clock) of counter; And the width initialization circuit 83 of turning back, it sets the maximum count value (corresponding with the width of turning back) of counter.Paces initialization circuit 86 is also identical with the

circuit

82,83 in low order address generation unit 80 with the width initialization circuit 87 of turning back.

The address computation control signal selcntlext providing together with mode register set command from Memory Controller and come is provided in mode register 40.This address computation control signal selcntlext has paces control signal selcntls (the high-order each dibit of low level) and the width control signal selcntlw that turns back (the high-order each dibit of low level).

Scalar/vector control circuit 88 is provided according to the direction of scanning control signal vaext providing from Memory Controller by the action of low level and high address generation unit 80,84.Direction of scanning control signal vaext is the signal of 3 bits, is to be used to specify the signal of totally 8 direction of scanning of direction and 4 vergence directions up and down.

Fig. 9 is the figure that the concrete example of direction of scanning control signal vaext is shown.Reference numeral 90 in figure represents the concrete example of direction of scanning control signal vaext, has distributed accordingly the direction of scanning control signal vaext of 3 bits with column direction up and down from current pixel CPX, left and right line direction and 4 vergence directions.

The method that it is set to together with mode register set command to the method for mode register and is provided together with row system directive by Memory Controller can be provided about providing of this direction of scanning control signal.The distribution of address terminal A00～A11 in the time providing together with row system directive is provided Reference numeral 92 in Fig. 9.In the activation instruction ACT sending as row system directive, input the row address RA00～RA11 of 12 bits to the address terminal A00～A11 of 12 bits.In addition, in the write or read instruction WR/RD sending as row system directive, input the column address CA00～CA07 of 8 bits to address terminal A00～A07, input auto-precharge signal AP to address terminal A10, and input the direction of scanning control signal VA0～VA2 of 3 bits to remaining address terminal A08, A09, A11.Direction of scanning control signal vaext is owing to being imported on address terminal, therefore also referred to as vector address.

Turn back to Fig. 8, scalar/vector control circuit 88 is controlled following according to direction of scanning control signal vaext: be to carry out the clock CLK of address control as the counting controling signal countlz output of low order address generation unit 80, or as the counting controling signal countuz output of high address generation unit 84, or export as both counting controling signal countlz, countuz.And, scalar/vector control circuit 88 is controlled following according to direction of scanning control signal vaext: be using the count end signal of low order address generation unit 80 (carry signal) caintle as the counting controling signal countuz output to high-order, or using the count end signal of high address generation unit 84 (carry signal) caintue as the counting controling signal countlz output to low level.And scalar/vector control circuit 88 comes to low level and high

address generation unit

80,84 output reverse control signal reverslz, reversuz according to direction of scanning control signal vaext.

; in the time that direction of scanning is line direction; output clock CLK is as the counting controling signal countlz of low order address generation unit 80, and provides count end signal (carry signal) caintle of low order address generation unit 80 as the counting controling signal of high address generation unit 84.In the time that direction of scanning is column direction, output clock CLK is as the counting controling signal countuz of high address generation unit 84, and provides the count end signal caintue of high address generation unit 84 as the counting controling signal of low order address generation unit 80.In addition,, in the time that direction of scanning is vergence direction, output clock, as low level and high-order counting controling signal.

Below, how scalar/vector control circuit 88 is controlled to low level according to direction of scanning control signal vaext and high

address generation unit

80,84 describes.

(1) direction of scanning control signal vaext=000: just march forward to line direction

Clock CLK is connected with the counting controling signal countlz of low level;

Count end signal (carry signal) caintle of low level is connected with high-order counting controling signal countuz;

Reverse control signal reverslz, reversuz are all set to forward;

Its result, is connected in series to high-order clock control circuit 84 from the clock control circuit 80 of low level, and the internal column address caint<07:00> of 8 bits and clock CLK are synchronously upwards counted successively., high address generation unit 84 is synchronously counted action with the count end signal caintle of low order address generation unit 80.

(2) direction of scanning control signal vaext=111: oppositely advance to line direction

Reverse control signal reverslz, reversuz are all set to oppositely;

Its result, the clock control circuit 80 of low level and high-order clock control circuit 84 are connected in series, and the internal column address caint<07:00> of 8 bits and clock CLK are synchronously counted downwards successively., high address generation unit 84 is synchronously counted action with the count end signal caintle of low order address generation unit 80.About reverse downward counting action, will describe in detail in the back.In addition, reverse control signal reversuz can be set to forward.

(3) direction of scanning control signal vaext=001: just march forward to column direction

Clock CLK is connected with high-order counting controling signal countuz;

High-order count end signal (carry signal) caintue is connected with the counting controling signal countlz of low level;

Reverse control signal reverslz, reversuz are all set to forward;

Its result, clock control circuit 80 from high-order clock control circuit 84 to low level is connected in series, high-order internal column address caint<07:04> and the clock CLK of 4 bits are synchronously upwards counted successively, and the low level internal column address caint<03:00> of 4 bits and high-order count end signal caintue are synchronously upwards counted successively.

(4) direction of scanning control signal vaext=110: oppositely advance to column direction

Clock CLK is connected with high-order counting controling signal countuz;

Reverse control signal reverslz, reversuz are all set to oppositely;

Its result, clock control circuit 80 from high-order clock control circuit 84 to low level is connected in series, high-order internal column address caint<07:04> and the clock CLK of 4 bits are synchronously counted downwards successively, and the low level internal column address caint<03:00> of 4 bits and high-order count end signal caintue are synchronously counted downwards successively.In addition, reverse control signal reverslz can be set to forward.(5) direction of scanning control signal vaext=011: to lower right

Clock CLK is connected with counting controling signal countuz, the countlz of a high position and low level;

Reverse control signal reverslz, reversuz are all set to forward;

Its result, high-order clock control circuit 84 and the clock control circuit of low level 80 are synchronously upwards counted concurrently with clock CLK., high-order internal column address caint<07:04> and low level internal column address caint<03:00> are upwards counted concurrently successively.

(6) direction of scanning control signal vaext=101: to upper right

Reverse control signal reverslz, reversuz are set to respectively forward, reverse;

Its result, the clock control circuit 84 of a high position and the clock control circuit of low level 80 synchronously walk abreast and count action with clock CLK, count downwards respectively, upwards count.That is, high-order internal column address caint<07:04> is counted downwards successively, and low level internal column address caint<03:00> is upwards counted successively.

(7) direction of scanning control signal vaext=010: direction to left down

Clock CLK is connected with counting controling signal countuz, the countlz of low level and a high position;

Reverse control signal reverslz, reversuz are set to respectively oppositely, forward;

Its result, the clock control circuit 84 of a high position and the clock control circuit of status 80 synchronously walk abreast and count action with clock CLK, upwards count respectively, count downwards.That is, high-order internal column address caint<07:04> is upwards counted successively, and low level internal column address caint<03:00> is counted downwards successively.

(8) direction of scanning control signal vaext=100: to upper left

Reverse control signal reverslz, reversuz are all set to oppositely;

Its result, high-order clock control circuit 84 and the clock control circuit of low level 84 synchronously walk abreast and count action with clock CLK, all count downwards.That is, high-order internal column address caint<07:04> is counted downwards successively, and low level internal column address caint<03:00> is also counted downwards successively.

Low level and high

address generation unit

80,84 are upwards counted or are counted downwards with the paces of setting according to paces control signal selcntls.By suitably setting this paces value, can to by the direction of scanning tilting with respect to the tilt directions (low level, high-order the equal situation of paces number) of 45 degree of level, vertical direction, or with respect to tilt directions (low level, high-order the different situation of the paces number) scanning of the angle beyond 45 degree of level, vertical direction.For example, if the paces number of low level is set as to 1, high-order paces number is set as to 2, can the moving direction of " osmanthus horse " in chess be scanned to Japan.

In addition, low level and high

address generation unit

80,84 repeat upwards to count or count downwards with the width of turning back of setting according to the width control signal selcntlw that turns back.By suitably setting this width of turning back, can conduct interviews to any rectangle by the burst access based on row system directive once.

And the number of the burst-length clock CLK of the continuous counter value of being undertaken by low level and high

address generation unit

80,84 based on above-mentioned is controlled.

As mentioned above, direction of scanning control signal vaext and address computation control signal selcntlext are the signals of controlling address computation method.Thereby two control signals both can be set in mode register 40 by mode register set command, also can input from address terminal together with row system directive simultaneously.In the embodiment of Fig. 8, direction of scanning control signal vaext inputs together with row system directive, and address computation control signal selcntlext is set in mode register 40 by mode register set command.

Below, dip sweeping access, level and vertical scanning access, special scanning access are described successively.

[dip sweeping access]

Motion image data is made up of continuous frame image data.Process the direction of motion of obtaining identical figure between two field picture as motion vector according to the compression of mpeg standard, and data using the difference of motion vector and figure as next two field picture only.Thus, can compress the data volume of next two field picture.In the search of this motion vector, search and microlith image in the consistent or similar follow-up two field picture of the view data of the microlith by 16 × 16 pixels formations.

Figure 10 A and Figure 10 B are the figure that the example of the direction of motion of moving image is shown.The in the situation that of moving image, as shown in Figure 10 A, the motion of horizontal direction is more, and then, as shown in Figure 10 B, the motion of vertical direction is more., the motion of horizontal direction and the motion of vertical direction have occupied a greater part of in figure motion.On the other hand, the probability that figure adipping moves is lower.

Figure 11 A and Figure 11 B illustrate the direction of motion of moving image and the figure of momental distribution.Figure 11 A shows the distribution of the direction of motion of moving image.Suppose the view data of 4 pixels of 1 storage cell region (4 byte) storage, the view data of 4 storage cell region CA67～CA97 storage 4 × 4 pixels.In the case, in the search of motion vector, the view data in search 4 storage cell regions consistent or similar with the view data of 4 × 4 pixels of unit area CA67～CA97.Thereby the motion vector based on moving image and momental statistics are come setting search region, this contributes to improve the efficiency of motion-vector search processing.

Show the angle θ of the direction of motion that the motion image data of sample is investigated and the relation of travel frequency in the left side of Figure 11 A.To θ=0 corresponding with horizontal direction, the travel frequency of the direction of π, 2 π is high, time high to the travel frequency of the direction of the θ=pi/2 corresponding with vertical direction, 3 pi/2s, the travel frequency of all the other angles is low.It is maximum that the direction of motion of the moving image describing in Figure 10 A and Figure 10 B is proved horizontal direction, and then vertical direction is many, and vergence direction is few.The left side of Figure 11 B shows amount of exercise d that the moving image of sample is investigated and the relation of travel frequency.Hence one can see that, and the shorter travel frequency of displacement is just higher.

Be understood that in the search of motion vector according to these statisticses, in the time of search vergence direction and the large region of amount of movement d, detect that the probability of consistent or similar figure is lower.

Figure 12 is the figure that an example of the hunting zone of motion vector is shown.Page region Page is made up of 16 × 16 storage cell region, as the matrix of the graph data of two-dimensional array data and this 16

× 16 storage cell region is corresponding.And, first suppose the block graphics of 4 × 4 pixels in the storage cell region CA67～CA97 of 4, center carried out to the search of motion vector.As described in the past, if will all search for the storage cell region of 16 × 16 in the Page of page region, need to access these 256 storage cell regions.

But, as illustrated, if according to the direction of motion of moving image and mobile quantitative statistics, can improve search efficiency by the region of the rhombus RHB except 4 angular zones in the Page of search page region in Figure 10 A～Figure 11 B.Rhombus RHB region is 1/2 area of 1 page region Page, if therefore region of search is made as to diamond-shaped area, region of search will reduce by half.Therefore the access, to carry out the search of motion vector in this diamond-shaped area RHB time describes.

Figure 13 A and Figure 13 B are the figure that an example of the access method of diamond-shaped area is shown.In the time of diamond-shaped area RHB in the Page of access page region, if column address is in the past increased progressively to (increment) thus in the situation that line direction scans, conducting interviews, cannot happen suddenly and read or happen suddenly to write with identical burst-length, access efficiency declines.Therefore, as shown in FIG. 13A, if happen suddenly and read or happen suddenly to write in the situation that adipping scans as shown by arrows in storage arrangement side,, owing to conducting interviews with identical burst-length, therefore the efficiency of reference-to storage device uprises.In common image encoding system, the view data in frame memory is kept in intrasystem working storage (Figure 13 B).

As shown in Figure 13 A and Figure 13 B, if the diamond-shaped area RHB in frame memory (Figure 13 A) can be scanned along the vergence direction of arrow, in system working memory (Figure 13 B), will preserve the view data in 8 × 16 storage cell region.

Figure 14 is the figure that the scanning of vergence direction is described.For diamond-shaped area is along inclined direction scanned, need the column address control part in storage arrangement to generate successively column address CA07～CA7e along the direction of arrow of Figure 14.,, in order along inclined direction to scan, must increase progressively concurrently the column address CA-L of low level and high-order column address CA-U.Therefore, as described in the column address control part 41 of Fig. 8, by suitably controlling low order address generation unit 80 and high address generation unit 84 so that their concurrent activities can carry out with burst mode the scanning of above-mentioned vergence direction.

Figure 15 is the figure that the column address control part that carries out vergence direction scanning is shown.Figure 16, Figure 17 are the detail view of carrying out the column address control part of vergence direction scanning.In Figure 15, scalar/vector control circuit 88 provides clock CLK according to direction of scanning control signal vaext=011 to counting controling signal countlz, the countuz of low level and high

address generation unit

80,84 simultaneously.And paces control signal selcntls is set to paces number 1 (step1), be set to so that the selector switch of

paces initialization circuit

82,86 offers counting controling signal countlz, countuz respectively A00 and the A04 of counter 81,85.In addition, the width control signal selcntlw that turns back is set to the width 16 (width16) of turning back, and is set to so that the A03 of the selector switch gated

counter

81,85 of the

width initialization circuit

83,87 of turning back and the output of A07.In addition, where count end signal caintle, caintue also do not connect.

By as above setting, in column address control part 41, low level and high

address generation unit

80,84 and clock CLK upwards count with running simultaneously.Thus, (set 0111 to low level if set initial value CA07=00000111 to the

counter

81,85 of low level and high

address generation unit

80,84, set 0000 to a high position), and synchronously generate column address with 8 clock CLK, can conduct interviews to the storage cell region CA07～CA7e shown in Figure 14 with page mode.

In Figure 16, Figure 17, only show the details drawing of low order address generation unit.As shown in the figure, 4 selector switchs 161 (SL00～SL03) in paces initialization circuit 82 select the low order digit of counting controling signal countlz and counter 81 to export any one in caint0～3.The selection of this selector switch 161 is carried out based on control signal control (step1,2,4,8), and this control signal control is obtained the paces control signal selcntls decoding of 2 bits by code translator 160.In the example of Figure 16, be set to step1, thereby only have selector switch SL00 to select defeated in2, other selector switchs SL01-03 has selected input in1.

In addition, caext0～3, outer array address are provided for the initial value terminal init of 4 bit counter 81 as initial value, bit counter 81 with synchronize and repeatedly upwards count action from clock signal clkca0～3 of selector switch 161.At the negative edge of clock clk, each trigger of counter 81 is the rotary movement from L level to H level or from H level to L level by output out repeatedly.

By as above setting, 4 bit counter 81 are synchronously upwards counted initial value successively with counting controling signal countlz.And, as shown in figure 16, export respectively internal column address caint0～3 from the lead-out terminal out of counter 81.Because low level, high address generation unit are set to step1 by paces control signal, therefore direction of scanning is with respect to 45 degree directions vertical, horizontal direction.But, by suitable setting paces number, also direction of scanning can be set as to the direction different from 45 degree.Thus, according to direction of scanning control signal vaext and paces control signal, can carry out to the burst access of vergence direction scanning at any angle.

On the other hand, as shown in figure 17, in internal column address caint0～3 of the lead-out terminal out from counter 81, the signal that only has the selector switch 171 of being turned back in width initialization circuit 83 to select is used as count end signal (carry signal) caintle and exports.Action is selected based on control signal control (width02,04,06,08) in 4 selector switch SL10～13, and this control signal control (width02,04,06,08) is obtained the turning back width control signal selcntlw decoding of each 2 bits by code translator 170.

The sequential chart of storage arrangement when Figure 18, Figure 19 are adipping scanning.Figure 18 shows the example of the storage arrangement of the burst mode without vergence direction, and Figure 19 shows the example of the storage arrangement of the burst mode with vergence direction.There is shown clock CLK, CS, RAS, CAS, WE and bank-address BA as command signal.And show the subsidiary column address CA that reads instruction RD and input.Dash area shows the action of memory bank BA1, and remainder shows the action of memory bank BA0.,, in this example, two memory banks move across.

The in the situation that of Figure 18, storage arrangement does not have the burst mode of vergence direction.When in the time that time t0 has been inputted precharge instruction PRE to memory bank BA0, from time t1, memory bank BA0 carries out precharge action.During this period, in memory bank BA1, repeatedly read action in response to reading instruction RD.After 1 clock of time t1, play the time t3 after RAS tRP precharge time, to memory bank BA0 input activation instruction ACT.Thereby, during 1 clock period from time t3, do not send the instruction of reading to memory bank BA0.In response to this activation instruction, the row address not illustrating in based on figure in memory bank BA0 activates action.During this period, in memory bank BA1, again repeatedly read action in response to reading instruction RD.

Then, the time t6 after RASCAS tRCD time delay, inputs and reads instruction RD and column address CA continuously memory bank BA0.Storage arrangement respectively in response to be not with burst mode but continuously 8 times of input read instruction RD and 8 kinds of column address CA07～CA7e, 8 storage cell regions of arranging at vergence direction are repeated to read to move.And, in the example of Figure 18, send the precharge instruction PRE for memory bank BA1 at time t5, send the activation instruction ACT for memory bank BA1 at time t7.Thus, during 1 clock rising at time t7, do not send and read instruction RD for memory bank BA0.

So, in the example of Figure 18, Memory Controller is for adipping scans, and need to send the row system directive of 8 times, read instruction RD and column address CA.In addition, storage arrangement can not move with burst mode, and the continuous input of reading instruction is because memory bank crossed work is interrupted.

The in the situation that of Figure 19, storage arrangement has the burst mode function of vergence direction.When inputted by the action of the column address control part shown in Figure 15,16,17 1 time read instruction RD and initial column address CA07 time, arrange control circuit generates internal column address CA18, CA29, CA3a, CA4b, CA5c, CA6d, CA7e continuously, and carry out continuously 8 times 32 Bit datas read action.,, once input activation instruction ACT at time t1 for memory bank BA0, will the time t3 input after RASCAS tRCD time delay read instruction RDA, initial column address CA07 and direction of scanning control signal VA=011.Owing to having preset burst-length BL=8, therefore column address control part generates internal column address CA18, CA29, CA3a, CA4b, CA5c, CA6d, CA7e continuously, and carries out continuously the action of reading of 32 bit × 8 time.During this period, although sent the activation instruction ACT for memory bank BA1 at time t5, it is interference-free that action is read in the burst in memory bank BA0.Reading instruction RDA is the instruction of reading with auto-precharge, can specify this to read instruction RDA by the auto-precharge bit of the address terminal A10 shown in Fig. 9 is set as to H level.

So, because storage arrangement has the burst mode function of vergence direction, the scanning access of the vergence direction therefore can conduct interviews expeditiously diamond-shaped area time.And the angle of vergence direction can be set as arbitrarily angled by direction of scanning control signal vaext and paces control signal selcntls.Here arbitrarily angled refer to arbitrarily angled in the scope being limited by the position in the storage cell region in memory mapped.

[level and vertical scanning access]

Figure 20 is the figure that the horizontal scanning access in page region is shown.Conduct interviews in the Page of page region, along continuous straight runs (line direction) scans as shown by arrows in the situation that, column address control part in storage arrangement need to preferentially increase progressively low level column address CA-L (arrow 200), and increases progressively high-order column address CA-U according to the carry signal of low level column address.Thus, can happen suddenly and read continuously to horizontal direction.

Figure 21 is the figure that the vertical scanning access in page region is shown.Conduct interviews in the Page of page region, as shown by arrows vertically (column direction) scans in the situation that, column address control part in storage arrangement need to preferentially increase progressively high-order column address CA-U (arrow 210), and increases progressively low level column address CA-L according to the carry signal of high-order column address.Thus, can happen suddenly and read continuously to vertical direction.

Figure 22 is the figure that the burst direction determining processing of being undertaken by Memory Controller is shown.Carry out this determination processing by the burst direction determining portion 32 in the Memory Controller 12 of Fig. 3.As shown in the Reference numeral 220 in Figure 22, suppose that the input and output terminal DQ of storage arrangement is made up of 32 bits, the view data of 1 pixel is made up of 8 bits.And, suppose according to memory mapped, in the storage cell region of selecting by column address, store the pixel data of the pixel count Dv=1 of pixel count Dh=4, the vertical direction of horizontal direction.And as shown in the Reference numeral 221 in Figure 22, suppose from superior system and sent the request of access for the access region of degree of tilt=0, horizontal direction pixel count Lh=8, vertical direction pixel count Nv=8.Number and direction determining processing are in the case described.

Figure 23 is the process flow diagram that the burst direction determining processing of being undertaken by Memory Controller is shown.Memory Controller is the request of access (S20) of Lh=8, Nv=8 from superior system reception horizontal direction pixel count and vertical direction pixel count.Burst direction determining circuit in Memory Controller converts pixel count to columns (S21) in storage arrangement.Its result, as shown in the Reference numeral 221 of Figure 22, burst direction determining circuit calculated level direction columns Nh=Lh/Dh=2, vertical direction columns Nv=Lv/Dv=8 (S22).Then, burst direction determining circuit is by relatively this horizontal direction columns Nh and vertical direction columns Nv judge best burst direction (S23).If Nh≤Nv, the direction that happens suddenly is set to horizontal direction (S24).On the contrary, if Nh > is Nv, the direction that happens suddenly is set to vertical direction.This be because by by burst direction setting be that the direction of growing can be applied the access based on burst mode effectively.

Figure 24 illustrates the figure that scans the example of access (burst access) to vertical direction.In this example, in storage cell region, preserve the view data of 4 pixels, the rectangular area of 4 × 8 pixels is accessed.Thereby, need to conduct interviews to a storage cell region, 8 of the vertical direction of column address CA20 to CA90.In the case, the column address control part 41 in storage arrangement increases progressively high-order column address CA-U and generates successively CA20～CA90 from initial column address CA20.

Figure 25 is the structural drawing that scans the column address control part of access (burst access) to vertical direction.In order to carry out burst access to vertical direction, low order address generation unit 80 and high address generation unit 84 in column address control part 41 are upside down connection.; scalar/vector control circuit 88 provides clock CLK as counting controling signal countuz to high address generation unit 84, provides count end signal (carry signal) caintue of high address generation unit 84 as counting controling signal countlz to low order address generation unit 80.And for low level and high address generation unit, both are set to paces step1 to paces control signal selcntls, low counter 81 and high-positioned counter 85 response count control signal and count value is added to 1 concurrently.In addition, for low level and high address generation unit, both are set to width width16 to the width control signal selcntlw that turns back, and are selected the most significant bit of low counter 81 and high-positioned counter 85 by

selector switch

83,87.

By as above setting, high-positioned counter 85 first synchronously increases by 1 by each count value with clock CLK, and low counter 81 synchronously increases by 1 by each count value with the count end signal caintue of high-positioned counter 85.Consequently, column address caext0～7 that column address control part 41 comes providing from outside generate until the address of end value CA90 successively as internal column address caint0～7 as initial value CA20.

Figure 26, Figure 27 are the sequential charts while scanning access to vertical direction.Figure 26 is the sequential chart of storage arrangement while not having the burst mode of vertical direction.Identical with Figure 18, when in the time that time t0 has been inputted precharge instruction PRE to memory bank BA0, from time t1, memory bank BA0 carries out precharge action.During this period, in memory bank BA1, repeatedly read action in response to reading instruction RD.After 1 clock of time t1, play the time t3 after RAS tRP precharge time, to memory bank BA0 input activation instruction ACT.Thereby, during 1 clock period from time t3, do not send the instruction of reading to memory bank BA1.In response to this activation instruction, the row address not illustrating in based on figure in memory bank BA0 activates action.During this period, in memory bank BA1, again repeatedly read action in response to reading instruction RD.

Then, the time t6 after RASCAS tRCD time delay, inputs and reads instruction RD and column address CA continuously memory bank BA0.Storage arrangement respectively in response to be not with burst mode but continuously 8 times of input read instruction RD and 8 kinds of column address CA20～CA90,8 storage cell regions of arranging are in the vertical direction repeated to read to move.Then, in the example of Figure 26, send the precharge instruction PRE for memory bank BA1 at time t5, send the activation instruction ACT for memory bank BA1 at time t7.Thus, during 1 clock rising at time t7, do not send and read instruction RD for memory bank BA0.

So, in the example of Figure 26, Memory Controller is in order to conduct interviews to vertical scan direction, need to send the row system directive of 8 times, read instruction RD and column address CA.In addition, storage arrangement can not move with burst mode, and the continuous input of reading instruction is because memory bank crossed work is interrupted.

Figure 27 is the sequential chart of storage arrangement while having the burst mode function of vertical direction.When the action of the column address control part 41 by shown in Figure 25 inputted 1 time read instruction RD and initial column address CA20 time, column address control part generates internal column address CA20, CA30, CA40, CA50, CA60, CA70, CA80 continuously, and carry out continuously 8 times 32 Bit datas read action.,, once input activation instruction ACT at time t1 for memory bank BA0, will the time t3 input after RASCAS tRCD time delay read instruction RDA, initial column address CA20 and direction of scanning control signal VA=001.Owing to having preset burst-length BL=8, therefore column address control part generates internal column address CA20, CA30, CA40, CA50, CA60, CA70, CA80 continuously, and carries out continuously the action of reading of 32 bit × 8 time.During this period, although sent the activation instruction ACT for memory bank BA1 at time t5, it is interference-free that action is read in the burst in memory bank BA0.

So, because storage arrangement has the burst mode function of vertical direction, the scanning access of the vertical direction while thering is in vertical direction the rectangular area in more storage cell region that therefore can conduct interviews expeditiously.

Figure 28 illustrates the figure that scans another example of access (burst access) to vertical direction.In this example, in storage cell region, preserve the view data of 4 pixels, the rectangular area of 8 × 8 pixels is accessed.Thereby, need to conduct interviews to 8 storage cell regions of the vertical direction of a storage cell region, 8 of the vertical direction of column address CA20 to CA90 and column address CA21 to CA91.

In SDRAM in the past, owing to carrying out burst access to horizontal direction, therefore set burst-length BL=2, and together with column address CA20, CA30, CA40, CA50, CA60, CA70, CA80, row system directive RD, the WR of 8 times are offered to storage arrangement, access thus the view data of the rectangular area of 8 × 8 pixels.

With respect to this, in present embodiment can be to the storage arrangement of vertical direction burst access, if set burst-length BL=8, and together with column address CA20, CA21, row system directive RD, the WR of 2 times are offered to storage arrangement, just can access the view data of the rectangular area of 8 × 8 pixels.Thus, can shorten the busy condition of the bus between Memory Controller and storage arrangement.

[special direction of scanning]

Below, sparse (Inter is drawn to I) burst access of burst access, rectangular area and forward and reverse access describe as special direction of scanning.

Figure 29 is the figure for the access while carrying out motion prediction is described.In this example, the data of 8 bits of every 1 pixel are mapped to the storage arrangement of the DQ interface that word structure is × 16 bits.Suppose in motion prediction, to the foursquare rectangle 290 of 4 × 4 pixels of surrounding by bold box, to vertical direction search ± 4 pixels, to horizontal direction search ± 8 pixels.; in motion-vector search; rectangle 290 rectangular region 292 interior respectively to column direction move 9 times, move 9 times to line direction in the situation that, carry out altogether the processing of the view data of the view data of comparison rectangle 290 of 81 times and the rectangle of mobile destination.Once detect consistent view data, the direction from rectangle 290 to this rectangular area detecting becomes motion vector.

Figure 30, Figure 31 are the figure for another access while carrying out motion prediction is described.In this example, the data of 8 bits of every 1 pixel are also mapped to the storage arrangement of the DQ interface that word structure is × 16 bits.And, the rectangular area of 4 × 4 pixels is carried out to the search of motion vector.

In the access example of Figure 30, originally, be in rectangular area 302 (rectangular area being surrounded by CA24-CA2d-CAdd-Cad4) that sparse to ranks direction is that in 1/2 region, searching in the rectangular area 300 (rectangular area being surrounded by CA46-CA4c-CAcc-CAc6) of 8 × 8 pixels of 2 times big or small of handling object rectangle sparse to ranks direction is 1/2 region.This search for for the first time by carry out to line direction 4 times, to column direction carry out carrying out altogether for 3 times the access of 12 times and relatively process.

Then, as shown in figure 31, suppose that in search for the first time, best position is the rectangular area 314 (region being surrounded by CA66-CA69-Cad9-Cad6) using the storage cell region of column address CA66 as the upper left corner.In the case, in search for the second time, the rectangular area 310 (region being surrounded by CA66-CA67-CA97-CA96) of search 4 × 4 pixels in the rectangular area 312 (region being surrounded by CA55-CA5a-CAea-Cae5) of a large circle than rectangular area 314.In this search, do not carry out 1/2 sparse.This search need to line direction carry out 5 times, to column direction carry out carrying out altogether for 7 times the access of 35 times and relatively process.Because the search for the first time of Figure 30 is carried out 12 times, therefore the summation of search for the first time and search is for the second time 12+35=47 time.Compared with this number of times 81 during with Figure 29, be approximately reduced to approximately 58%.

Above-mentioned two stage Search rules are known.And when having adopted above-mentioned 2 stage Searchs whens rule, for access Figure 30 by sparse be 1/2 data, Memory Controller cannot utilize burst to read, and need to send the row system directive of 8 times and corresponding column address to storage arrangement.Or, also can conduct interviews as follows: by burst read to visit not by sparse be 1/2 data, and abandon unwanted data.But no matter which kind of situation all will decline to a great extent to the access efficiency of storage arrangement.

Figure 32, Figure 33 are the structural drawing of the column address control part in searching for for the first time of two stage Search rules.Figure 32 shows a part for low order address generation unit 80, and Figure 32 shows a part for high address generation unit 84.

Structural similarity shown in structure and the Figure 25 of column address control part in search for the first time.That is, scalar/vector control circuit 88 provides clock CLK as counting controling signal to high address generation unit 84, provides the count end signal caintue of high-order side as counting controling signal to low order address generation unit 80.The burst access of the rectangular area that can grow in vertical direction expeditiously thus.And stride is set as step2 by the

paces initialization circuit

82,86 of low level and high address generation unit.Thus, can synchronously increase progressively count value with stride 2 with counting controling signal, can be to carrying out burst access through 1/2 sparse storage cell region.

Then, Figure 32, Figure 33 are described.As mentioned above, in search for the first time, need access through 1/2 sparse storage cell region.Therefore, in low level and high

address generation unit

80,84, selector switch SL01, SL05 select counting controling signal countlz, countuz according to paces control signal selcntls=Step2, and export counting controling signal countlz, countuz as clock clka1, clka5 to counter 81,85.Thus, can synchronously in the numerical digit (digit) higher than A01, the A05 of

counter

81,85, increase progressively action with clock CLK by burst mode.Its result, low level and high

address generation unit

80,84 increase progressively internal column address with 2 recruitment (paces number).Thus, shown in Figure 32 in the access of 1/2 sparse rectangular area, also can use burst mode.The defeated in1 of the selector switch SL00 of the low order address generation unit 80 of Figure 32 does not input any clock.Similarly, on the defeated in1 of the selector switch SL04 of the high address generation unit 84 of Figure 33, do not input any clock yet.Thus, the A00 of counter, A04 bit maintain column address A00, the A04 of initial set value.

Figure 34 is the sequential chart of the storage arrangement in searching for for the first time of two stage Search rules.As shown in this sequential chart, at time t3, read instruction RDA and be input to storage arrangement together with bank-address BA0, column address CA24 and vector address VA=001.In response to this, the column address control part in storage arrangement generates internal column address CA24, CA44, CA64, CA84 successively, column address CA24, the CA44 of connected reference Figure 30, the storage cell region of CA64, CA84.

As mentioned above, in low level and high

address generation unit

80,84, by according to paces control signal selcntls, selcntus, the selector switch in

paces initialization circuit

82,86 being set as to paces step2, can be to carrying out burst access through 1/2 sparse storage cell region.Similarly, if be set as paces step4, step8, can be to carrying out burst access through 1/4,1/8 sparse storage cell region.It is more than the explanation of sparse burst access.

[burst access of rectangular area]

Then, the burst access of rectangular area is described.Set by the low level of present embodiment and the width control signal selcntlw that turns back of high address generation unit the

width initialization circuit

83,87 of turning back, can at random set the counting end value of low level and high address generation unit.Thus, scalar/vector can synchronously generate repeatedly with clock CLK the count value of any range.As long as by it utilization, just can come with initial column address the rectangular area that burst access is made up of the storage cell region that on the column direction of being expert at, column address is different by the row system directive of 1 time.But due to the restriction of counter action, the address of turning back of the column address of rectangular area is the position of CA=1,3,7, F on low level, high address.

Figure 35 is the figure of the burst access of the rectangular area for present embodiment is described.Suppose burst access is carried out in the rectangular area being surrounded by column address CA00-CA01-CA71-CA70 in Figure 35.In burst access in the past, burst-length is made as to BL=2, the row system directive of 8 times and column address CA00, CA10, CA20, CA30, CA40, CA50, CA60, CA70 are offered to storage arrangement.In addition, if can carry out the scanning access of the vertical direction describing in Figure 25, Figure 27 etc., set burst-length BL=8, the row system directive of 2 times and column address CA00, CA01 are offered to storage arrangement.

With respect to this, in the burst access of the rectangular area of Figure 35, if provide the row system directive of 1 time and the initial column address CA00 of rectangular area to storage arrangement, storage arrangement generates 16 internal column address successively in inside, 16 storage cell regions of burst access.For this reason, in column address control part, need to set the width control signal selcntlw that turns back.

Figure 36 is the structural drawing of the column address control part while carrying out the burst access of the rectangular area in present embodiment.In column address control part 41, in order to carry out the scanning access of vertical direction, scalar/vector 88 offers synchronous clock CLK the counting controling signal countuz of high address generation unit 84, the count end signal of high address generation unit 84 (carry signal) caintue is offered to the counting controling signal countlz of low order address generation unit 80.And about high-order, low level side, paces control signal selcntls is set as to step1, the control signal selcontlw that turns back of low level side is set as to width16, the control signal selcontlw that turns back of high-order side is set as to width8.And if set burst-length BL=8, column address control part from initial column address CA00 by the action that increases progressively of high address generation unit 84, generate successively internal column address CA00, CA10, CA20, CA30, CA40, CA50, CA60, CA70, then the carry signal of output counter A06 is as count end signal (carry signal) caintue, and exports the counting controling signal countlz of this count end signal (carry signal) caintue as status address generation unit to counter A00.In response to this, low order address generation unit 80 increases progressively low order address+and 1.And the action that increases progressively by high address generation unit 84 from the column address CA01 having increased progressively in low level side of column address control part generates internal column address CA01, CA11, CA21, CA31, CA41, CA51, CA61, CA71 successively.The burst mode that can be 16 by burst-length thus, carries out the access of rectangular area.

Figure 37, Figure 38 are the structural drawing of a part for the high address generation unit while carrying out the burst access of rectangular area.As shown in figure 37, high address generation unit 84 is at paces initialization circuit 86 with turn back and have 4 bit counter 85 between width initialization circuit 87.The width initialization circuit 87 of turning back has selector switch group SL14～SL17 and selector switch group SL24～SL27.And, as shown in figure 38, high address generation unit 84 has the first code translator 170A and the second code translator 170B, the first code translator 170A generates control signal width02～16 for controlling selector switch group SL14～SL17, and the second code translator 170B generates the control signal cnt02en～con16en for controlling selector switch group SL24～SL27.

In the high address of Figure 37 generation unit 84, code translator 170A controls as H level based on the width control signal selcntlw that the turns back width width08 that only will turn back, and only has the output caint6 of selector switch SL16 gated counter A06 and sets it as count end signal caintue and export.Similarly, in response to the width width08=H that turns back, the code translator 170B of Figure 38 controls control signal cnt08en, cnt04en, cnt02en for H level, only control signal cnt16en is controlled for L level, selector switch SL27 selects input in2, and other selector switchs SL26, SL25, SL24 select input in1.Thus, form 3 bit counter that are made up of counter A04, A05, A06, internal column address cain4～6 are followed successively by 000-111.The address caint7 of most significant digit is fixed on initial value caext7., the decoder circuit 170B of Figure 38, because control signal 380 is set to L level, therefore generates control signal cnt02en～cnt16en according to width signal width02～16 of turning back.Particularly, turning back in width signal width02～16, if width02=H, cnt02en=H, is set to 1 bit counter.If width04=H, cnt02en and cnt04en=H, is set to 2 bit counter.If width16=H, cnt02en, cnt04en, cnt08en, cnt16en=H, is set to 4 bit counter.

By as above forming, column address control part increases progressively high-order column address successively from initial column address CA00, if internal column address arrives to CA70 and high-order internal column address is turned back to 0000, and again increases progressively successively high-order column address from column address CA01, and arrives to CA71.Generate thus 16 internal column address CA00～CA70, the CA01～CA71s corresponding with burst-length 16.So, by the suitable setting control signal of turning back, can make low level column address or high-order column address turn back with 2,4,8,16, can generate the required internal column address of burst access is carried out in rectangular area.

In Figure 36, by common mode, counting controling signal is connected to low level and high address generation unit, can carry out burst access to long in the horizontal direction rectangular area by row system directive and the initial column address of 1 time.

Figure 39 is the sequential chart of the storage arrangement while carrying out the burst access of rectangular area.Figure 39 is the sequential chart of the burst access the same with Figure 27, if input column address CA00 and vector address VA=001 together with reading instruction RDA at time t3, the column address control part in storage arrangement generates successively internal column address CA00, CA10～CA70 and CA01, CA11～CA71 after time t3.Thus, by inputting row system directive and the column address of 1 time, memory layer carries out the burst access of rectangular area with the burst access of burst-length 16.

[forward, inverted access]

Figure 40 is the structural drawing of a part for the low order address generation unit while carrying out inverted access.In Figure 40, only show the counter 81 of low order address generation unit 80, paces initialization circuit and the width initialization circuit of turning back have been omitted.Be provided with EOR (XOR) door group 400 in the prime of the initial value input terminal init of counter 81, be provided with EOR door group 402 in the rear class of output electronics out.Reverse control signal reverslz is input on the input terminal of one in these EOR door groups 400,402, if reverse control signal reverslz=H, caext0～3, outer array address are input to counter 81 after overturning in EOR door group 400, and counter output is exported as internal column address caint0～3 after upset in EOR door group 402.If reverse control signal reverslz=L, EOR door group 400,402 is directly exported the input signal of another one and is not overturn.

; if reverse control signal reverslz=H; for example using outer array address caext0～3=1111 upset and 0000 be set to counter as initial value; counter 81 synchronously increases progressively from 0000 successively with counting controling signal countlz, and 4 bit addresses that its output valve upset is obtained are exported as internal column address caint0～3.Thus, with respect to outer array address caext0～3=1111, by reverse control, count downwards to 0000 to inverse direction from 1111 internal column address caint0～3.

Scalar/vector control circuit 88 is owing to having EOR door group 400,402, therefore the counting direction of low level and high address generation unit can be set as to forward, any direction in oppositely.Thus, even the inverse direction that the direction of vector address VA is column address, column address control part also can generate with burst mode the internal column address of inverse direction accordingly successively.

Figure 41 is the figure that the example of the memory mapped with time shaft is shown.Above-mentioned embodiment is illustrated as prerequisite the view data of the data as two-dimensional arrangements is kept to 1 memory mapped in page region in Fig. 7 etc.Now, in order to scan access to any direction in the two-dimensional space being formed by horizontal direction and vertical direction, column address is divided into low level and a high position has formed column address control part.

In the present embodiment, the Segmentation Number of column address is not limited to 2, can be 3 or more than it.Figure 41 is the example that the Segmentation Number of column address is 3.Low level column address CA-L (A00～A03) and meta column address CA-M (A04～A07) are corresponding with horizontal direction and the vertical direction of two-dimensional array data, and high-order column address CA-U (A08～A09) is corresponding with time-axis direction time.So, by column address being divided into 3, page Page0～3, region of the two-dimensional array of specifying by low level and meta column address are designated as 4 by high-order column address.

For example, in the compression of motion image data, not only carry out compression in frame, also carry out the compression on time-axis direction.In addition, for the raw image data of 60 frame/seconds, make image more good-looking by adding compensated frame in interframe recently.Such as in the case, need the access of the horizontal and vertical direction that not only carry out at a high speed picture but also the storage arrangement that carries out the access of time-axis direction at a high speed.In the case, the mapping as view data to the page region of storer, effectively mode is to storer by the rectangular parallelepiped spatial mappings that also comprises time-axis direction.; as shown in figure 41; add CA08, CA09 as the address that is used to specify time-axis direction, thereby column address control part is consisted of low level column address CA03～CA00, the meta column address CA07～CA04 that distributes to the vertical direction of image, three scalar/vectors distributing to the high-order column address CA09～CA08 of time-axis direction as the horizontal direction of distributing to image.According to this column address control part, can carry out burst access to the time-axis direction of image.

Availability in industry

According to the present invention, can carry out burst access to various directions to two-dimensional array data such as view data.

Claims

1. a storage arrangement, is characterized in that, comprising:

Memory cell array, it has multiple storage cells region of selecting by address, and two-dimensional array data are stored in described multiple storage cells region;

Home address control part, it inputs external address, and generates the home address for selecting described storage cell region based on described external address; And

Code translator, home address is selected described storage cell region described in its decoding;

Wherein, the low-order bit group of described multiple storage cells region based on described home address stored the data on the first direction in the matrix that is arranged on described two-dimensional array data, and high order bit group based on described home address is stored the data in the second direction in the matrix that is arranged on described two-dimensional array data

Described home address control part comprises: low order address generation unit, and it generates the low-order bit group of described home address; High address generation unit, it generates the high order bit group of described home address; And scalar/vector control circuit, the direction of scanning control signal of its direction of scanning based on for controlling described two-dimensional array data is controlled the action of described low order address generation unit and high address generation unit, and described home address control part generates the home address corresponding with the direction of scanning of described direction of scanning control signal successively

Described scalar/vector control circuit is in the time that described direction of scanning control signal is described first direction, preferentially make described low order address generation unit move to change successively described low order address, in the time that described direction of scanning control signal is described second direction, preferentially make described high address generation unit move to change successively described high address, in the time that described direction of scanning control signal is the vergence direction different from described first and second direction, make described low level and high address generation unit concurrent activity to change successively concurrently described low level and high address.

2. storage arrangement as claimed in claim 1, is characterized in that,

Described address has row address and column address,

Described memory cell array has the multiple pages of regions of selecting by described row address, and described page region has the multiple described storage cell region of selecting by described column address,

Described home address control part generates the internal column address in described home address.

3. storage arrangement as claimed in claim 2, is characterized in that,

The page region response of selecting by described row address activates action in activation instruction, and read action or action response reading instruction or write command and the described storage cell region corresponding with described column address carried out in providing described activation instruction after is provided

Under burst mode, in response to described instruction or the write command read, home address control part generates the internal column address of burst-length number successively, and reads action or write action the described storage cell region of selecting by the described internal column address generating is successively repeated.

4. storage arrangement as claimed in claim 3, is characterized in that,

In the time that described direction of scanning control signal is vergence direction, described scalar/vector control circuit makes described low order address generation unit and high address generation unit concurrent activity, thus parallel generation low level internal column address and high-order internal column address successively.

5. storage arrangement as claimed in claim 4, is characterized in that,

Described low order address generation unit and high address generation unit have respectively counter circuit, and described counter circuit changes count value in response to counter control signal.

6. storage arrangement as claimed in claim 5, is characterized in that,

Described low order address generation unit and high address generation unit also have respectively low level paces initialization circuit and high-order paces initialization circuit, and described low level paces initialization circuit and high-order paces initialization circuit are inputted described counter control signal according to paces control signal to a certain numerical digit of described counter circuit.

7. storage arrangement as claimed in claim 6, is characterized in that,

Described low order address generation unit and high address generation unit generate successively corresponding to low level internal column address and the high-order internal column address of described direction of scanning control signal and the corresponding angle direction of described paces control signal.

8. storage arrangement as claimed in claim 5, is characterized in that,

Described low order address generation unit and high address generation unit also have respectively low level width initialization circuit and the high position width initialization circuit of turning back of turning back, and described low level is turned back width initialization circuit and the high-order width initialization circuit of turning back the export described counter circuit output signal of a certain numerical digit according to the width control signal of turning back as carry signal.

9. storage arrangement as claimed in claim 5, is characterized in that,

Described counter circuit will provide from outside and the column address come is set as initial value, and changes count value in response to counting controling signal and generate successively low level and the high-order internal column address of described burst-length number.

10. storage arrangement as claimed in claim 3, is characterized in that,

When described direction of scanning data are described first or when second direction, described scalar/vector control circuit makes described low order address generation unit and high address generation unit series connection action,

In the time that described direction of scanning data are described first direction, described scalar/vector control circuit makes described low order address generation unit generate successively low level internal column address in response to clock, and make the carry signal that described high address generation unit generates in response to described low order address generation unit and generate successively high-order internal column address

In the time that described direction of scanning data are described second direction, described scalar/vector control circuit makes described high address generation unit generate successively high-order internal column address in response to clock, and makes the carry signal that described low order address generation unit generates in response to described high address generation unit and generate successively low level internal column address.

11. storage arrangements as claimed in claim 3, is characterized in that,

Described low order address generation unit and high address generation unit have respectively counter circuit, and described counter circuit changes count value in response to counter control signal,

Described low order address generation unit and high address generation unit also have respectively low level width initialization circuit and the high position width initialization circuit of turning back of turning back, described low level is turned back width initialization circuit and the high-order width initialization circuit of turning back the export described counter circuit output signal of a certain numerical digit according to the width control signal of turning back as carry signal

In the time that access has respectively the rectangular area in multiple storage cells region on both direction, in response to outer array address with described in read instruction or write command, the generation of width carries out repeatedly internal column address that what described low level or high address generation unit were set with the width control signal of turning back described in basis turn back.

12. storage arrangements as claimed in claim 3, is characterized in that,

And described low order address generation unit and high address generation unit have a group, described door group, in response to reverse control signal, will offer described counter circuit after the upset of counter initial value, and by output after the count value upset of described counter circuit.

13. storage arrangements as claimed in claim 1, is characterized in that,

The direction of scanning control signal of the multiple direction of scanning that at least comprise vergence direction of described home address control part based on for controlling described two-dimensional array data, generates the home address corresponding with described direction of scanning.

14. 1 kinds of Memory Controllers, is characterized in that, control the storage arrangement described in claim 1, and comprise:

Burst direction determining portion, position coordinates, portraitlandscape length and the degree of tilt of the rectangular area of its input regulation access object, and generate described direction of scanning control signal;

Portion is sent in instruction, and it generates steering order and exports described steering order to described storage arrangement; And

Portion is sent in address, and it generates external command and exports described external command to described storage arrangement;

Wherein, described direction of scanning control signal is exported to described storage arrangement.

15. Memory Controllers as claimed in claim 14, is characterized in that,

Described burst direction determining portion generates the described direction of scanning control signal using longitudinal direction longer in described portraitlandscape length or horizontal direction as direction of scanning.