CN102289417B

CN102289417B - Memory system and method

Info

Publication number: CN102289417B
Application number: CN201110167651.6A
Authority: CN
Inventors: 李俊; 李敏宇
Original assignee: Cypress Semiconductor Corp
Current assignee: Cypress Semiconductor Corp
Priority date: 2010-06-21
Filing date: 2011-06-21
Publication date: 2016-05-11
Anticipated expiration: 2031-06-21
Also published as: CN102289417A; TW201216067A; TWI564724B

Abstract

In one embodiment, one equipment comprises a Memory Controller Hub, multiple daisy chain internal memory members that this Memory Controller Hub is connected through a daisy chain bus with control through configuration, this daisy chain bus is to comprise always the connecing in succession an of receiving interface of transmitting the initial internal memory member of interface to from one of this Memory Controller Hub, and transmitting the daisy chain connection of interface to a receiving interface of next internal memory member from one of this initial internal memory member, a bus is a receiving interface that directly expands to this Memory Controller Hub from a transmission interface of last internal memory member.

Description

Memory system and method

Technical field

This disclosure is general relevant with the field of memory system.

The mutual reference of related application

The application's case is the U.S. patent application case the 12/239th, 532 in the Shen of carrying on the 26th September in 2008Number continuous application case, its entirety is to enter herein in way of reference.

Background technology

One memory system comprises a Memory Controller Hub, and this Memory Controller Hub is via an address/command bus and oneData/address bus and be connected to one or more internal memory members. This Memory Controller Hub is total through this address/commandLine sends order and will write and/or read from a memory headroom, this memory headroom to control which internal memory memberPresented by stored data on those internal memory members. An internal memory member in those internal memory members to be writtenData be transferred to via this data/address bus from this Memory Controller Hub those internal memory members in a correspondenceDeposit member, simultaneously memory to be read from those internal memory members one corresponding internal memory member via this data/address busAnd be transferred to this Memory Controller Hub.

Some existing memory architecture are used the multiple spot from this Memory Controller Hub to those internal memory members(multi-drop) connect. A pair of point connects to comprise from this internal memory member and is branched off into one of those internal memory membersTrace. The branch of this trace sets up signal reflection, and obstructs high-frequency operation and be limited in accordingly this Memory controlTreating capacity between device and those internal memory members.

A subject under discussion of existing memory architecture is relevant with capacity. The storage volume of one memory system is limited to and comprisesMany factors of the word length of this system. One word typical case is equal to from the data of this Memory Controller Hub expansionThe bit width of bus.

For example, although the word length of expansion can cause a larger capacity (: one 64 systems compare 1Position system can have larger memory size conventionally), but still have many balance items. Along with wordThe increase of width, route is around sending the data/address bus of widening to gradually become difficulty. Complicated data/address bus route aroundSend and can cause data misalignment, wherein a structure is arrived at different time in the position on each link of this data/address busPart place. This data misalignment further obstructs high-frequency operation, and it affects again in this Memory Controller Hub and thoseDeposit the treating capacity between member. The stitch counting increasing for increasing another balance item of word width, itsIncrease cost to manufacturing Memory Controller Hub and internal memory member significantly.

Two direct insertion memory modules (FB-DIMM) parts of full buffer solve some above-mentioned restrictions. From thisThe point to point connect of the advanced core buffer of Memory Controller Hub to (AMB) replaces aforementioned multiple spot and connects.Reduce the stitch this Memory Controller Hub from this Memory Controller Hub to the serial line interface of this advanced person's core bufferCounting, and simplify some total lines by around sending. Each internal memory member is contributed its part to whole word length.

But the two direct insertion memory modules systems of this full buffer cause the problem of self. For example: this internal memory controlDevice processed those internal memory members that cannot write direct, and first must first write this advanced person and remember buffer. AgainPerson, because this advanced person that serves as reasons remembers processing (subsequent analysis subsequently and foundation one queue that buffer cushionsResend) introduce the stand-by period (latency), so remembering buffer, this advanced person hinders high speed operation.

Be that for another subject under discussion again of some existing memory systems this Memory Controller Hub must have and eachOne data length of the data length coupling of internal memory member. For example: 144 Memory Controller Hub are compatible with144 internal memories, this data pins count matches that means this Memory Controller Hub is in each internal memory memberData pins counting. So, module manufacturer must obtain the internal memory structure that this Memory Controller Hub is mated to some extentPart, and a high stitch counting on this Memory Controller Hub means each internal memory member and has a high stitch counting.

Summary of the invention

In one embodiment, an equipment comprises a Memory Controller Hub, this Memory Controller Hub through configuration to controlOne internal memory member and the second internal memory member. Through configuration to pass between this Memory Controller Hub and those internal memory membersOne Point-to-Point Data bus of delivery data can comprise direct from each internal memory member to this Memory Controller HubConnect. This Point-to-Point Data bus can be a universal serial bus. In one embodiment, through configuration with at this internal memoryBetween controller and those internal memory members, a daisy chain address bus of transferring command can comprise from this first internal memoryMember connects to this Memory Controller Hub always in succession, and from this first internal memory member to this second internal memory structureOne daisy chain of part connects.

In another embodiment, an equipment comprises a Memory Controller Hub, this Memory Controller Hub through configuration with controlThe multiple daisy chain internal memory members that connect through a daisy chain bus. This daisy chain bus packet contains from this Memory Controller HubAlways the connecing in succession an of receiving interface of transmitting the initial internal memory member of interface to, and from this initially inDeposit one of member and transmit the daisy chain connection of interface to a receiving interface of next internal memory member. One bus fromOne transmission interface of last internal memory member directly expands to a receiving interface of this Memory Controller Hub.

Brief description of the drawings

Fig. 1 illustrates to be had internal memory member according to an embodiment to be connected to a low latency address through daisy chain totalOne point-to-point memory architecture of line.

Fig. 2 illustrates the internal memory degree of depth expander graphs of the point-to-point memory architecture that uses Fig. 1.

Fig. 3 illustrates a process of the initial internal memory member for using Fig. 1.

Fig. 4 illustrates the internal memory width expander graphs of the point-to-point memory architecture that uses Fig. 1.

Fig. 5 illustrates to be had internal memory member and carries out one of daisy chain connection from the transmission interface of a Memory Controller Hub and beSystem figure.

Fig. 6 illustrates for the internal memory member 51A of system shown in Fig. 5 and a sequential chart of 51B.

Fig. 7 illustrates and utilizes for the described principle of Fig. 4 internal memory width expander graphs in conjunction with for Fig. 5 internal memory degree of depthOne system of the described principle of expander graphs.

Detailed description of the invention

Several examples of the application's case are narrated with reference to rear accompanying drawing formula. Various other example of the present invention alsoFeasible and practical. This application case can many multi-form examples of enumerating, and should not be regarded as hereinIn the restriction of mentioned example.

This system 100 comprises a Memory Controller Hub 20, and it has (can to multiple internal memory member 21A and 21BAs the discrete integrated circuit of any type storing) point to point connect. For address/command bus14A-B, those internal memory member 21A and 21B are connected to this Memory Controller Hub 20 by daisy chain, only mean and haveThe first internal memory member 21A can be connected directly to a command interface of this Memory Controller Hub 20. But forData/address bus 13A-B and 15A-B, those internal memory members 21A, means through being directly connected with the each person of 21BThose internal memory member 21A and 21B all can be connected directly to a data-interface of this Memory Controller Hub 20.

This first internal memory member 21A system comprises a Circuits System 11, through configuration with immediately will be via this addressAll order line ripples transmission (ripplethrough) that bus 14A receives. This Circuits System 11 can be groundBetween location/order receiver 17A and address command conveyer 19A one is inner to be connected. Because those ordersCan be for example, by row ripple transmission immediately (: the demand that there is no queue and buffering), so this internal memory member 21B energyReceive with the minimum latency increasing the order retransferring via bus 14B. Should be obvious:This Circuits System 11 is not born has complex analyses to determine which order will be by the transmission of row ripple.

In this system 100, this internal memory of width of the data-interface on those internal memory member 21A and 21BThe sub-fraction of one width of the data-interface of controller. For example: those Point-to-Point Data buses 13A and15A can be connected to the initial part on a data-interface on this Memory Controller Hub, and remaining internal memory structurePart 21B via those data/address bus 13B and 15B to be connected to the remainder on this data-interface.Accordingly, those internal memory member 21A and 21B can have a little portion of the stitch counting of this Memory Controller Hub 20Point. Equally, extend to and can be calculating from the width of the data/address bus of each internal memory member 21A and 21BThe sub-fraction of the width of device system.

Should be appreciated that: be different from the system of commonly using, this system 100 provides flexibility, makes those internal memoriesThe width of member 21A and 21B can be different from the width of this Memory Controller Hub 20. This character allows to controlDevice 20 process routine plans are to operate mutually with multiple internal memory width/depth combinations. One example will be shown in figureIn 2, how to be used to expand the degree of depth of a memory system to illustrate this Circuits System 10. One example will showBe shown in the width that how to be used to expand a memory system in Fig. 4 to illustrate this Circuits System 10.

Still with reference to figure 1, those buses 13A, 13B, 15A and 15B are serial in native system 100Bus. But should be obvious: application of principle mentioned above is same in the system that contains parallel data bus lineSample is feasible and practical.

Should be appreciated that equally: those internal memory member 21A and 21B can be equal on framework. Should be obvious: the aforementioned easy property that convenience in configuration is provided and manufactures.

This system 100 is specially adapted to wherein to use sizable word length (for example: 144)Networked environment. In this environment, special around the number of links of delivering to each internal memory member through route to reducingUseful. Should be obvious: make comparisons by commonly using system with some, native system 100 use through route aroundThe 1/N that delivers to the number of links of each internal memory member, wherein N equals the number of used internal memory memberAmount. Although described principle is applicable to this networked environment or use other environment of quite high-order width hereinIn, but described application of principle herein equally can at any memory system of for example 32 memory systemsCapable and practical.

In this networked environment, treat the internal memory member typical static random access memory (SRAM) of access.But, will be herein described application of principle including but not limited to DRAM (DRAM),Any type internal memory of flash memory etc. is same feasible and practical.

Example system 200 is by operate two 40 internal memory member 30A with one 8 Memory Controller Hub 40Carry out the exented memory degree of depth with 30B. Via background technology, the internal memory degree of depth is censured desirable for each bit widthWith bit quantity. This system 200 by use two (but not one) internal memory members come access one word withThe internal memory degree of depth effectively doubles. Following paragraph provides an example of a write operation in this system 200.

For making a word be written into an internal memory, this Memory Controller Hub 400 is sent out this word through this interface 23See off. In this word, first 40 positions send through this bus 13A, and bus 13A is tool in this exampleThere is a universal serial bus of 5 serial links. In this word, one of next 40 positions process same-interface 23 is notSend with part and through other bus 13B. The two near points of this word be not received in interface 33A and33B place.

This controller 40 also sends the single order that writes through this address bus 14A. This is single writes orderProvide memory headroom address so that this word is write. Because this address space is done to expand through two internal memory membersExhibition, so this writes the position in corresponding two internal memories in address contained in order.

This internal memory member 30A receives this through this receiver 17A and writes order. This internal memory member 30A existsThis writes, and order is corresponding works when a position on it, by this front subluxation of this word is write to this this statusPut.

This Circuits System 11 also writes this order line ripple and is sent to this receiver 19A, should for processBus 14 retransfers. Decide this which part that writes order to should structure with its cost stand-by periodPart 30B, this Circuits System 30A is on the contrary via this receiver 19A whole order that writes that retransfers. ThisClass of operation is seemingly used to conveyer to a wireless transceiver and receiver carries out a loopback skill of selftestArt.

This member 30B writes this word (through input interface according to the order that writes from this bus 14B33B receives) rear subluxation. For the convenience of manufacture and mutual operation, this internal memory member 30B also containsThere is this Circuits System 11 also feasible, although do not have bus to be connected in this example with two membersThis receiver 19B.

One reading order operates with a similar fashion. Read receiving this through those buses 14A and 14BAfter command fetch, those internal memory member 30A and 30B process those interfaces 33A and 33B output requireWord.

The transmission latency energy being associated with those data/address bus 13A-B and those address bus 15A-BDifferent, particularly because transmit by row ripple the stand-by period that those orders add. With regard to aforementioned or itsIts reason, a compensation technique can be used to avoid the misalignment of this order and these data. For example: this internal memoryMember 30A can force a delay (delay) on the data being received through this bus 13A through configuration,So that these data are alignd with the order receiving through this receiver 17A. This internal memory member 30B can be through groupState is to force one compared with long delay in the data being received through this bus 13B, so that these data and processOrder that this receiver 14B receives alignment, wherein the reception of this order in time will be than by this internal memoryThe order that member 30A receives is evening also. This delay can be used buffer, first in first out (FIFO) bufferingDevice or implement for any other mechanisms known of forcing a delay. This delay can be depended on those internal memoriesMember along the position of this daisy chain and programmable on each internal memory member.

Forcing of the other type that can be used postpones by a delay of this Memory Controller Hub 40, to guaranteeThe data that receive through those buses 15A-B can be associated with the life sending through this address bus 14AOrder. When the delay of those internal memory members transmits this order and regains between these data at this Memory Controller Hub 40Different time on while affecting to some extent, corresponding those internal memory structures of delay that applied by this Memory Controller Hub 40The delay that part applies.

Should be obvious: even if this degree of depth expansion has identical at those internal memory members with this Memory Controller HubWhen width, still can be implemented. For example: if those internal memory member 30A and 30B are made as 80 of toolsMember, has half to be de-energized in those interfaces 33A and 33B.

Should be obvious: this Circuits System 10 allow these Memory Controller Hub 40 for above-mentioned degree of depth expansion andThrough routine plan. Accordingly, this controller 40 can be situated between and is connected to the internal memory member that for example there is 80 bit wides, has2 internal memory members of 40 bit wides, there are 4 internal memory members of 20 bit wides etc. Should be appreciated that: this circuitSystem 10 also can be used to those internal memory members of routine plan to use the input and output that reduce quantity, because ofAnd increase in proportion this internal memory degree of depth by two, for example: the degree of depth of 40 is the degree of depth that is 2X8 position,And the degree of depth of 20 is by the degree of depth that is 4X8 position. Depend on this configuration, this system 200 is different by havingThe internal memory degree of depth.

Should be obvious: this system 200 can be upgraded by the software that carries out configuration for above-mentioned functionsExisting Memory Controller Hub and implementing. This software can cause a stand-by period difference. Otherwise existing controller is notCan formulate in order to receive any hardware change from the word of two or more members.

In square 301, this internal memory member receives an order through address receiving interface. At square 302In, this command echo to one address is transmitted interface by this internal memory member.

In square 303, this internal memory member can postpone to force a programmable to this data-interface of processThe data that receive. This programmable postpones the data of reception and this address receiving interface of process to receiveOrder alignment, the duration of this delay is depended on the position of this internal memory member along this daisy chain. At squareIn 303, if the corresponding local address position of this order, this internal memory member is according in this order access oneDeposit position.

Depend on the tolerance that this system is built-in and depend on such as those data/address bus to different internal memory membersDifferent length, operating frequency and along this address bus its of the internal memory member total quantity through being connected in seriesIts factor, square 303 can not need. For example: some systems are stood up to 10 times of these circulation timeisMisalignment, for example: there is 10 in a system of an operating frequency 10GHz how second.

Routine plan number can measure etc. and to bide one's time according to propagate in the time receiving order institute for each internal memory memberBetween empirical analysis set. Accordingly, by from the outside inferior counting number of this initial internal memory member, each internal memoryMember postpones progressively to force a larger programmable through routine plan, and final internal memory in this serialMember by routine plan to force maximum delay.

This programmable postpones also can calculate according to input by each internal memory member. For example: based on useTo point out input and this internal memory member of the internal memory the number of components being connected in series along this address bus processOne instruction of the position in this serial, this internal memory member can determine a time delay to be forced.

Example system 300 is used to illustrate wide that the Circuits System 10 that uses on Memory Controller Hub 50 carries outDegree expansion or width adjustment. In this example, this Memory Controller Hub 50 is 160 Memory Controller Hub,And can operate with multiple bit width patterns, wherein comprise one first of 80 of tools as pointed in solid linePattern, and one second pattern of 160 of tools as pointed in dotted line.

In this first mode, this system 300 is operating as a system with 80 bit wides. Because controller50 with 40 internal memory 41A-B operations, so some bus (45C-D) and the interface portion of this interface 43Divide and can be separated energy for economize on electricity, as indicated in " x " mark. Should be obvious: some data/address busConnection and partial memory controller 50 already showed for convenience of description in this first mode.

In this second pattern, this system 300 can be operating as use similar hardware there are one of 160 bit widesSystem. Specifically, by using two extra memorys (41C-D) and by this Memory Controller HubWhole data-interface 43 and all data/address bus 45A-D power supply, this width can be adjusted to 160. ShouldThis is obvious: some data/address bus connect and partial memory controller 50 was already in this second patternConveniently illustrate and show.

Accordingly, should be obvious: the ability of these Circuits System 10 width adjustment. Depend on that user is inclined to one sideGet well and application demand, arbitrary pattern can be used this Circuits System 10 elect and allow same hardware to useIn the system of different bit wides. Should be appreciated that: the pattern quantity that can provide for 10 of this Circuits System does not haveRestricted, for example: this Circuits System 10 can A internal memory for the three-mode of 40 and to utilizeMember 41 carrys out this system 300 of configuration.

This system 500 comprises a Memory Controller Hub 505, and it has from the transport unit of serial memory interface 512Assign to one of an internal memory member 51A and connect 515A/517A, this internal memory member 51A can be for storingThe discrete integrated circuit of any type. For the translator unit of this serial memory interface 512, those internal memory structuresPart 51A-51N is connected to this Memory Controller Hub 505 by daisy chain, means and only has first internal memory member 51ACan be connected directly to a translator unit of the interface 512 of this Memory Controller Hub 505. But, for this stringThe receiving unit of row memory interface 512, this part has directly to last internal memory member in this daisy chainOne of 51N transmits a point to point connect of interface.

This internal memory member 51A makes the translator unit of its data-interface be connected to the number of this internal memory member 51BAccording to the receiving unit of interface. This internal memory member 51B makes the translator unit of its data-interface be connected to that this is interiorDeposit the receiving unit of the data-interface of member 51B. This internal memory member 51A makes the transport unit of its data-interfaceDivide the receiving unit of the data-interface that is connected to next internal memory member. Last internal memory member 51NMake the receiving unit of its data-interface be connected to previous internal memory member. Last internal memory member 51NTranslator unit be connected to the receiving unit of the interface 512 of this Memory Controller Hub 505. Those internal memory membersThe width of the data-interface on 51A-N meets data division one wide of the interface 512 of this Memory Controller HubDegree.

Those internal memory members 51A-N comprises Circuits System 511, through configuration with immediately will be through this address busThe order line ripple transmission that 517A receives. The address/command that this Circuits System 511 can be this internal memory member connectsReceive inner connection the between device and the address command conveyer of this internal memory member. Because those orders can be stoodRipple transmission at once (for example: the demand that there is no queue and buffering), so this internal memory member 51B can be to increaseMinimum latency receive the order retransferring via bus 517B.

Each internal memory member 51A-N have by a for example joint select, position set or for configuration thoseThe configuration that other mechanism of internal memory member 51A-N is formulated. This configuration mechanism is used to a memory headroomParticular be assigned to each internal memory member 51A-N. For example: this internal memory member 51A is with an internal memory skyBetween an initial part carry out configuration, this internal memory member 51B carries out with the next part of this memory headroomConfiguration, and this internal memory member 51N carries out configuration with last part of this memory headroom. This internal memory skyBetween thus expand via exceeding an internal memory member.

The first internal memory member 51A is by the address of ordering and the appointment ground that receive through connecting 517ALocation scope is made comparisons. If there is coupling, this first internal memory member 51A carries out one according to the order receivingInner access, and send a NOP instruction through connecting 517B. This NOP instruction responds this order and hindersEvery other internal memory member 51B-N operation below more in this daisy chain. If do not mate, this Circuits System511 orders by reception are passed to next internal memory member 51B through this connection 517B. This process continuesBy this daisy chain (NOP finally sends through connecting 525).

When the order receiving be to a memory scope of this internal memory member 51A in while reading of an address,This internal memory member 51A searches these data and is sent through connecting 515B, and these data are via connection515B-N and 527 is passed through other internal memory member 515B-N. When the order receiving is to this internal memory structureIn a memory scope of part 51A, one of an address writes fashionablely, and this internal memory member 51A 515 connects through connectingReceive data to be written. This confirmation writing is final to be sent through connecting 515B-N and 527.

Should be appreciated that: this system 500 provides flexibility to the internal memory degree of depth. That is, this Memory Controller Hub505 have a same-interface 512, no matter and be connected to the interface 512 of this Memory Controller Hub 505 through daisy chainThe quantity of internal memory member 51A-N of translator unit. When a degree of depth is by the quantity of variation internal memory memberWhen being expanded/reducing, this internal memory degree of depth (for example: the width of this interface 512) can be maintained.

Should be appreciated that equally: on those internal memory members 51A-N framework, can be equal to each other. Should be obviousBe: the aforementioned easy property that convenience in configuration is provided and manufactures. Should be obvious: previously discussedConfiguration can after a manufacture process, just be implemented.

The above-mentioned configuration of this system 500 has total line by the advantage around sending in the time comparing with other system.Along with the increase of the internal memory the number of components in this system 500, little corresponding trace can be added into. For exampleShould be obvious: each extra memory member only needs an extra data bus, but not in other designTwo extra data bus (due to the reception money bus 527 of single internal memory controller).

Should be appreciated that: can be with combined for the principle described in Fig. 4 for the principle described in Fig. 5. At thisIn one combined system, the each person of those internal memories 41A-41D (Fig. 4) comprises at least one and gives attached otherInternal memory member. The each person of those internal memories 41A-41D through a data/address bus so that order line ripple is sent to attachedInternal memory member. The reception that the transmission interface of attached internal memory member is attached to this Memory Controller Hub 50 connectsMouthful. Institute's generation system has the expansion of width and the degree of depth. Continuing to discuss native system 500 for Fig. 6Afterwards, aforementionedly will be described in a more detailed discussion for Fig. 7 after a while.

In a time t1 place, the address bus that this internal memory member 51A passes through this Memory Controller Hub receivesWrite W1 to one of its specified address area. This internal memory member 51A is also through interior to this in a data/address busThe respective channel of memory controller receives data Din1 and crcW1. This crcW1 and address W1 and dataDin1 is associated.

(cause and the memory stand-by period of processing this and writing associated) this internal memory member in a time t5 place51A passes through this address bus transmission NOP because this writes W1 in its address realm. This internal memory structurePart 51A is also owing to writing and countlessly passing through this data/address bus according to output and export a NOP one. One confirmsAlso can be output to check as CRC.

In a time t7 place, those NOP and this confirmation be received in this internal memory member 51B place (cause withThe passage stand-by period of transmitting associated through this bus). In time t11 place, this internal memory member 51BThose NOP and this confirmation are passed to next internal memory member.

The sequential chart of Fig. 6 also shows to one of this internal memory member 51A reading, to this internal memory member 51B'sOne writes and a process reading to this internal memory member 51B. With reference to writing this internal memory member 51BEnter (W2), in time t3 place, this internal memory member 51A receives this W2 order and the data that write to be written.In time t7 place, after comparative result points out the address realm of this internal memory member 51A not meet,This internal memory member 51A spreads out of this W2 order and data to be write back through this bus, to treat as shownReceive and process by next internal memory member.

Some temporal aspects of system 500 are from the sequential chart of Fig. 1 and obvious. For example: this system 500 shouldStand-by period on data/address bus maintains identical (transfer of data and address transfer are alignd) with this address bus.

Equally, suppose reading and writing of equal amount, the data channel of this data/address bus has 50% profitBy rate. For example: in this exemplary sequential chart, the data letter on the receiving interface of this memory device 51AIn 4 time slots that road has, having two is emptying (50% utilization rate), wherein have twi-read andWrite for twice.

Equally, this system 500 utilizes the CRC channel in this data/address bus to use one by circulation CRCScheme. For example: the transmission interface of this memory device 51A through a CRC channel of this data/address bus with oftenOne time time t5 sends transmission to the mode of t8. So with have one by data CRC inspection some otherMemory system contrary (CRC aligns CRC is transmitted with data transfer or other reasons through accumulation/delay).

In this system 700, Memory Controller Hub 705 has width expansion, that is the transmission of 20 of toolsInterface is coupled to internal memory A1 and the A2 of 10 of tools. In other systems, narration that can similar Fig. 4 andThere is extra memory A3-AN. The each person of those internal memories A1 and A2 as shown in figure encloses respectively through coupling withFor at least one internal memory N1 and N2 of degree of depth expansion.

Similar Fig. 4, internal memory A1 is sent to internal memory A2 by the order line ripple of reception as shown. Stand-by period existsIn this system 700 through configuration, make with an order is passed to internal memory A2 is associated from internal memory A1 etc.Treat time correspondence internal memory A1 deal with data and transmitted the stand-by period of leaving its TX interface. So permitPermitted address and transfer of data that internal memory N1 receives alignment. Address is controlled similar Figure 4 and 5 and is carried out, that isBy this Memory Controller Hub 705 of configuration and set the address realm of those internal memories A1, A2, N1 and N2.

Several examples were made above-mentioned narration with reference to rear accompanying drawing formula already. Other example of kind of the present invention also feasible andPractical. This system can many multi-form examples of enumerating, and should not be regarded as mentioned reality hereinThe restriction of example.

The operation of example when above the Multi-instance of cited graphic illustration the application's case is with these. At those figureIn formula, the size of those squares is not intended to represent the size of various actual components. For appear at multiple graphic inSame components, same components symbol is used to the same components of the graphic middle appearance of annotation.

System mentioned above can be used dedicated processor systems, the micro-control in order to carry out some or all instructionsDevice processed, programmable logic assembly or microprocessor. Certain operations mentioned above can be come real by softwareExecute, other operation can be implemented by hardware.

For simplicity, aforesaid operations is discussed as various interconnect function squares or different software module. SoAnd also following situation likely: those function squares and module equivalently by set to unity logic assembly, journeyIn order or operation and clearly boundary line of tool not. In anything part, those function squares and software module or canThe characteristic at flexible interface can be implemented by itself or with the combination of other operation in other hardware or software.

Already narrated and illustrated the principle of the present invention in embodiment, should be obvious: this disclosureCan in configuration and details, modify and can be departing from aforementioned principles. Advocate according to this to apply for a patent model in aftermentionedThe modification, equivalence example and the variation example that in the spirit of enclosing and category, arrive.

Claims

1. a memory device, comprising:

One Memory Controller Hub, its through configuration to control internal memory member, wherein each in those internal memory membersComprise the one or more discrete integrated circuit with storage data through configuration;

One daisy chain bus, it is passed to those internal memory by order and data writing from this Memory Controller Hub through configurationMember, the initial internal memory member of this daisy chain bus having from this Memory Controller Hub to those internal memory membersConnect in succession always, and next internal memory member having from this initial internal memory member to those internal memory membersOne daisy chain connects; And

One point-to-point bus, it is passed to this Memory control by reading out data from those internal memory members through configurationDevice, each internal memory member that this point-to-point bus has in those internal memory members arrives one of this Memory Controller HubIndependently directly connect.

2. memory device as claimed in claim 1, wherein this initial internal memory member further comprises:

One receiver, it is connected to this daisy chain bus, this receiver through configuration with through this daisy chain busDirectly connect and directly and this Memory Controller Hub carry out communication;

One conveyer, it is connected to this point-to-point bus, this conveyer through configuration at least to see through this nextThe direct connection of individual this point-to-point bus of internal memory member process, and carry out communication with this Memory Controller Hub; And

Circuits System, its through configuration with in inside by the receiver of this initial internal memory member and this initial internal memory structureThe conveyer of part links, and transmits via the received order that retransfers that uses this conveyer.

3. memory device as claimed in claim 2, wherein this Circuits System through configuration with by receive lifeOne address realm of order and this initial internal memory member is made comparisons, and relatively transmits the life of this reception according to thisOrder.

4. memory device as claimed in claim 1, wherein last internal memory in those internal memory membersMember further comprises:

One receiver, it is connected to this daisy chain bus, this receiver through configuration with at least see through this initially inDeposit member and carry out communication through the direct connection of this daisy chain bus with this Memory Controller Hub;

One conveyer, it is connected to this point-to-point bus, and this conveyer is point-to-point total to pass through this through configurationThe direct connection of line and directly and this Memory Controller Hub carry out communication; And

Circuits System, its through configuration with in inside by the receiver of this last internal memory member and this lastThe conveyer of individual internal memory member links, via use this conveyer retransfer to transmit from this lastThe data of individual internal memory member.

5. memory device as claimed in claim 1, wherein one of a data-interface of this Memory Controller HubEffect stitch counting equals an effect stitch meter of a data-interface of an internal memory member in those internal memory membersNumber.

6. memory device as claimed in claim 1, wherein this daisy chain bus is a universal serial bus.

7. memory device as claimed in claim 1, wherein those internal memory definition of the component one address spaces,And wherein this initial internal memory member stores the data of a particular range, this particular range not with those internal memory membersIn last internal memory member one scope overlap.

8. memory device as claimed in claim 7, further comprises circuit at this initial internal memory memberSystem, this Circuits System through configuration with:

Made comparisons in the address comprising in the order of one reception and this particular range; And

Compare with this daisy chain bus of process extremely next Memory Controller Hub of this command routing according to this.

9. memory device as claimed in claim 7, wherein this daisy chain bus and the each person of this point-to-point busThere is at least one channel that is designated as cyclic redundancy check CRC transmission, wherein each internal memory member withEach cycle for the treatment of sends or receives a CRC transmission.

10. memory device as claimed in claim 1, wherein this Memory Controller Hub only has from its expansionArticle two, point to point connect, wherein a point to point connect transmits Interface Expanding from one of this Memory Controller Hub, andAnother point to point connect is from a receiving interface expansion of this Memory Controller Hub, and this Memory Controller Hub quilt whereinBe coupled to and exceed two internal memory members.

11. 1 kinds of local data storage member, comprising:

One first interface, its through configuration to be connected directly to one first teledata storage member;

One second interface, it is different from one of this first teledata storage member through configuration to be connected directly toThe second teledata storage member;

One the 3rd interface, it, wherein should to use data/address bus to be connected directly to a Memory Controller Hub through configurationData/address bus through configuration so that reading out data is directly sent to this Memory control from this local data storage memberDevice; And

Circuits System, it is specified to being somebody's turn to do to comprise in the process order that this first interface was received through configurationWhen the one extraneous address of local data storage member, by this command routing to this second interface for heavyNew transmission,

Wherein, this local data storage member and this first teledata storage member and this second is long-rangeEach in data storing member comprises the one or more discrete integrated circuit with storage data through configuration.

12. local data storage member as claimed in claim 11, wherein this local data storage memberBe connected to this first remote storage member by daisy chain, and it is interior from this to see through this first remote storage member receptionThe order of memory controller.

13. local data storage member as claimed in claim 11, wherein this first interface hasOne width is identical with a width of a translator unit of this Memory Controller Hub.

14. local data storage member as claimed in claim 11, wherein pass through the every of this second interfaceOne data transfer is alignd with a corresponding address transfer.

15. local data storage member as claimed in claim 11, wherein connect through this first interfaceCyclic redundancy check (CRC) transmission of receiving is processed as basis by endless form taking one.

16. 1 kinds of local data storage member, comprising:

One receiving interface, its through configuration to be connected directly to one first teledata storage member;

One first transmits interface, and it is different from this first teledata storage member through configuration to be connected directly toOne second teledata storage member;

One second transmit interface, its through configuration with via one independently data/address bus be connected directly to an internal memory controlDevice processed, this independently data/address bus through configuration to make this local data storage member can reading out data is straightConnect and be passed to this Memory Controller Hub; And

Circuits System, its through configuration connecing through a command routing to this transmission that this receiving interface was receivedMouth is for again transferring to this Memory Controller Hub;

17. local data storage member as claimed in claim 16, wherein this local data storage memberBe connected to this first teledata storage member by daisy chain, and the weight of this first teledata storage member of processNew transmission is to receive the order from this Memory Controller Hub.

18. local data storage member as claimed in claim 16, wherein this receiving interface hasOne width is identical with a width of a translator unit of this Memory Controller Hub.

19. local data storage member as claimed in claim 16, wherein through this second transmission interfaceTransfer of data each time align with a corresponding address transfer.

20. local data storage member as claimed in claim 16, wherein connect through this receiving interfaceCyclic redundancy check (CRC) transmission of receiving is processed as basis by endless form taking one.