CN102280993A - Circuit structure for eliminating slope compensation temperature effect in current-mode DC-DC converter - Google Patents

Abstract

The invention relates to a circuit structure for eliminating slope compensation temperature effect in a current-mode DC-DC converter, wherein an output terminal of an operational amplifier is connect with a grid terminal of a fifth MOS tube, the source terminal of the fifth MOS (metal oxide semiconductor) tube is earthed through a fourth resistor; a drain terminal of the fifth MOS tube is connected with the drain terminal of a first MOS tube, the MOS tube and the grid terminal of a second tube; the drain terminal of the second MOS tube is respectively connected with the base electrode of a first triode and the base electrode of a second triode; an emitter of the first triode is earthed through a sixth resistor; the emitter of the second triode is earthed through a first resistor; collectors of the second triode are respectively connected with the drain terminal of the third MOS tube, the grid terminal of the third MOS tube and the grid terminal of a fourth polar tube, and the grid terminal of the third MOS tube is connected with the grid terminal of the fourth MOS tube; the drain terminal of the fourth MOS tube is earthed through a second resistor, and the drain terminal of a sixth MOS tube is earthed through a third resistor. The circuit structure can improve the loading capacity of the output tape, decrease the use cost, and improve the security and the reliability.

Description

Be used for eliminating the circuit structure of current-mode DC-DC converter slope compensation temperature effect

Technical field

The present invention relates to the circuit structure in a kind of DC-DC converter, especially a kind of circuit structure that is used for eliminating current-mode DC-DC converter slope compensation temperature effect belongs to the technical field of DC-DC converter.

Background technology

The DC-DC converter can be divided into two types of voltage-mode and current-mode according to the feedback system that is adopted.Wherein, Voltage Feedback control is the most basic a kind of control technology of Switching Power Supply, belongs to the monocycle feedback controling mode.Voltage Feedback control only realizes the negative feedback of entire circuit by a voltage feedback signal, have only a feedback control loop in the The whole control circuit, is a kind of monocycle control system.Current Control can be divided into average current and peak current FEEDBACK CONTROL, because the gain of average current FEEDBACK CONTROL current amplifier at the switching frequency place has maximum constraints, and parameter designing debugging such as two closed loop amplifier bandwidth, gain are complicated, therefore seldom adopt in practice.Usually said Current Feedback Control all is meant the peak current FEEDBACK CONTROL.In the Switching Power Supply of peak current feedback mode control, when duty ratio greater than 50% the time, the output vibration can appear, therefore need the electric current of sampling be compensated; Slope compensation circuit can guarantee that the inductance average current does not change with the variation of input voltage and ON time.

As shown in Figure 1: for using the peak current feedback control structure block diagram of band slope compensation at present always.Among Fig. 1, PMOS pipe S1 represents master power switch, and NMOS pipe N1 represents synchronous rectification switch, V _iBe input voltage, FB represents the input of output voltage V out feedback signal, current detection module 1 is used for the electric current of filter inductance L is sampled, and with the input of the form of voltage as slope compensation circuit, oscillator 3 produces the clock signal of PWM controller 5 on the one hand, oscillator 3 links to each other with PWM controller 5 by rest-set flip-flop 4, is used to open power switch pipe, is provided for the sawtooth signal of slope compensation on the other hand; The V of error amplifier 7 _BREFExpression band gap reference voltage input, adder 2 is with the slope compensation voltage and the direct voltage V that produce in current detecting 1, the oscillator 3 _DCThe input back of adding up be input to the end of oppisite phase of PWM comparator 6 as slope compensation.The operation principle of system is: in normal work period, the clock signal that oscillator 3 produces all goes out to trigger rest-set flip-flop in each cycle, master power switch S1 is opened, power supply Vi by main switch to outside filter inductance L output current; During this period, 1 pair of inductive current sampling of current detection module, and be input in the PWM comparator 6.In case inductive current reaches peak value threshold, the PWM comparator output signal resets PWM controller 5, turn-offs master power switch pipe S1.Error amplifier 7 compares the back output error signal with the reference voltage of feedback voltage and the generation of inner band gap reference, and described error signal is used to set inductance peak current thresholding.When load increases, then can cause feedback voltage signal FB on the low side, thereby make the output of error amplifier 7 uprise, the peak current thresholding improves thereupon, and until average inductor current and new load current coupling, vice versa.When master power switch pipe S1 turn-offed, synchronous rectification switch pipe N1 just can carry out afterflow.

But, can change with variation of temperature in the existing slope compensation structure, after slope compensation varies with temperature, can cause DC-DC converter load capacity to descend, peak current increases, and can increase the use cost of DC-DC converter simultaneously.

Summary of the invention

The objective of the invention is to overcome the deficiencies in the prior art, a kind of circuit structure that is used for eliminating current-mode DC-DC converter slope compensation temperature effect is provided, it is simple in structure, can improve the output carrying load ability, reduces use cost, and is safe and reliable.

According to technical scheme provided by the invention, the described circuit structure that is used for eliminating current-mode DC-DC converter slope compensation temperature effect, comprise operational amplifier, the output of described operational amplifier links to each other with the gate terminal of the 5th metal-oxide-semiconductor, and the source terminal of the 5th metal-oxide-semiconductor links to each other the back by the 4th grounding through resistance with the end of oppisite phase of operational amplifier; The drain electrode end of the 5th metal-oxide-semiconductor links to each other with the drain electrode end of first metal-oxide-semiconductor, the gate terminal of first metal-oxide-semiconductor and the gate terminal of second metal-oxide-semiconductor, the gate terminal of second metal-oxide-semiconductor links to each other with the gate terminal of first metal-oxide-semiconductor, and the source terminal of second metal-oxide-semiconductor links to each other with the source terminal of first metal-oxide-semiconductor, the collector electrode of first triode; The drain electrode end of second metal-oxide-semiconductor links to each other with the base stage of first triode, the base stage and the 5th resistance of second triode respectively, and the 5th resistance is corresponding to the other end ground connection that links to each other with second metal-oxide-semiconductor; The emitter of first triode is by the 6th grounding through resistance; The emitter of second triode is by first grounding through resistance; The collector electrode of second triode links to each other with the drain electrode end of the 3rd metal-oxide-semiconductor, the gate terminal of the 3rd metal-oxide-semiconductor and the gate terminal of the 4th metal-oxide-semiconductor respectively, the gate terminal of the 3rd metal-oxide-semiconductor links to each other with the gate terminal of the 4th metal-oxide-semiconductor, the source terminal of the 3rd metal-oxide-semiconductor links to each other with the source terminal of second metal-oxide-semiconductor, and links to each other with the source terminal of the 4th metal-oxide-semiconductor and the 6th metal-oxide-semiconductor respectively; The drain electrode end of the 4th metal-oxide-semiconductor is by second grounding through resistance, and the drain electrode end of the 6th metal-oxide-semiconductor is by the 3rd grounding through resistance, and the gate terminal of the 6th metal-oxide-semiconductor links to each other with the gate terminal of the 4th metal-oxide-semiconductor.

The in-phase end of described operational amplifier is reference voltage V _REFInput.Described first metal-oxide-semiconductor, second metal-oxide-semiconductor, the 3rd metal-oxide-semiconductor, the 4th metal-oxide-semiconductor, the 5th metal-oxide-semiconductor and the 6th metal-oxide-semiconductor are P type metal-oxide-semiconductor.

Described first metal-oxide-semiconductor and second metal-oxide-semiconductor form first image source; First metal-oxide-semiconductor is identical with the breadth length ratio of the second metal-oxide-semiconductor conducting channel.

Described the 3rd metal-oxide-semiconductor, the 4th metal-oxide-semiconductor and the 6th metal-oxide-semiconductor form second image source; The breadth length ratio of the 3rd metal-oxide-semiconductor, the 4th metal-oxide-semiconductor and the 6th metal-oxide-semiconductor conducting channel is 1: K2: K4.

Described first resistance, second resistance, the 3rd resistance, the 4th resistance, the 5th resistance and the 6th resistance are the resistance of uniform temp coefficient.Described second resistance is identical with the resistance of the 3rd resistance.

Advantage of the present invention: first metal-oxide-semiconductor and second metal-oxide-semiconductor form first image source, and the 3rd metal-oxide-semiconductor, the 4th metal-oxide-semiconductor and the 6th metal-oxide-semiconductor form second image source; Operational amplifier forms voltage follower, by producing peak value threshold voltage Vclamp by first triode behind first image source; And by obtaining slope compensation voltage Vslope and direct voltage VDC behind second triode and second image source respectively, temperature coefficient according to actual corresponding resistor, after regulating corresponding ratio, can guarantee that inductive current does not change with variation of temperature, guarantee to adopt the control of peak value slope compensation not change, guarantee the load capacity of DC-DC converter with variation of temperature, simple in structure, reduced the use cost of DC-DC converter, safe and reliable.

Description of drawings

Fig. 1 is the structured flowchart of existing current-mode DC-DC converter.

Fig. 2 is circuit theory diagrams of the present invention.

Description of reference numerals: 1-current detection module, 2-adder, 3-oscillator, 4-RS divider, 5-PWM controller, 6-PWM comparator, 7-error amplifier, 8-operational amplifier, 9-first image source and 10-second image source.

Embodiment

The invention will be further described below in conjunction with concrete drawings and Examples.

As shown in Figure 2: in order to eliminate slope compensation temperature effect in the current-mode DC-DC converter, improve DC-DC converter carrying load ability, reduce the use cost of DC-DC converter, the present invention includes operational amplifier 8, the output of described operational amplifier 8 links to each other with the gate terminal of the 5th metal-oxide-semiconductor M5, and the source terminal of the 5th metal-oxide-semiconductor M5 links to each other the back by the 4th resistance R 4 ground connection with the end of oppisite phase of operational amplifier 8.The in-phase end of operational amplifier 8 is reference voltage V _REFInput, the end of oppisite phase that operational amplifier 8 the forms back formation voltage follower that links to each other with the source terminal of the 5th metal-oxide-semiconductor M5.After the output voltage of operational amplifier 8 made the 5th metal-oxide-semiconductor M5 conducting, reference voltage VREF was forming electric current I 1 by the 4th resistance R 4.Electric current I 1 can be expressed as:

$I1=\frac{V_{\mathrm{REF}}}{R4}---\left(1\right)$

The drain electrode end of the 5th metal-oxide-semiconductor M5 links to each other with the drain electrode end of the first metal-oxide-semiconductor M1, the gate terminal of the first metal-oxide-semiconductor M1 and the drain electrode end of the second metal-oxide-semiconductor M2, the gate terminal of the second metal-oxide-semiconductor M2 links to each other with the gate terminal of the first metal-oxide-semiconductor M1, the source terminal of the first metal-oxide-semiconductor M1 links to each other with the source terminal of the second metal-oxide-semiconductor M2, and the first metal-oxide-semiconductor M1 and the second metal-oxide-semiconductor M2 are P type metal-oxide-semiconductor.Form first image source 9 between the first metal-oxide-semiconductor M1 and the second metal-oxide-semiconductor M2, and corresponding conducting channel breadth length ratio is identical between the first metal-oxide-semiconductor M1 and the second metal-oxide-semiconductor M2, also is that the first metal-oxide-semiconductor M1 is identical with the drain current of the second metal-oxide-semiconductor M2.Behind the first metal-oxide-semiconductor M1 and the second metal-oxide-semiconductor M2 mirror image, obtain electric current I 1 at the drain electrode end of the second metal-oxide-semiconductor M2, after electric current I 1 produces dividing potential drops through the 5th resistance R 5, obtain voltage V1 at the drain electrode end of the second metal-oxide-semiconductor M2, voltage V1 can be expressed as:

$V1=\frac{V_{\mathrm{REF}}}{R4}*R5---\left(2\right)$

Wherein, the 4th resistance R 4 and the 5th resistance R 5 are the resistance of uniform temp coefficient; Order

Obtain

V1＝k1*V _REF (3)

The source terminal of the second metal-oxide-semiconductor M2 links to each other with the collector electrode of the first triode Q1; The drain electrode end of the second metal-oxide-semiconductor M2 links to each other with the base stage of the first triode Q1, base stage and the 5th resistance R 5 of the second triode Q2 respectively, and the 5th resistance R 5 is corresponding to the other end ground connection that links to each other with the second metal-oxide-semiconductor M2; The emitter of the first triode Q1 is by the 6th resistance R 6 ground connection; The emitter of the second triode Q2 is by first resistance R, 1 ground connection; The collector electrode of the second triode Q2 links to each other with the drain electrode end of the 3rd metal-oxide-semiconductor M3, the gate terminal of the 3rd metal-oxide-semiconductor M3 and the gate terminal of the 4th metal-oxide-semiconductor M4 respectively, the gate terminal of the 3rd metal-oxide-semiconductor M3 links to each other with the gate terminal of the 4th metal-oxide-semiconductor M4, the source terminal of the 3rd metal-oxide-semiconductor M3 links to each other with the source terminal of the second metal-oxide-semiconductor M2, and links to each other with the source terminal of the 4th metal-oxide-semiconductor M4 and the 6th metal-oxide-semiconductor M6 respectively; The drain electrode end of the 4th metal-oxide-semiconductor M4 is by second resistance R, 2 ground connection, and the drain electrode end of the 6th metal-oxide-semiconductor M6 is by the 3rd resistance R 3 ground connection, and the gate terminal of the 6th metal-oxide-semiconductor M6 links to each other with the gate terminal of the 4th metal-oxide-semiconductor M4.The 3rd metal-oxide-semiconductor M3, the 4th metal-oxide-semiconductor M4 and the 6th metal-oxide-semiconductor M6 are P type metal-oxide-semiconductor; And the 3rd metal-oxide-semiconductor M3, the 4th metal-oxide-semiconductor M4 and the 6th metal-oxide-semiconductor M6 form second image source 10, and the breadth length ratio of the 3rd metal-oxide-semiconductor M3, the 3rd metal-oxide-semiconductor M4 and the corresponding conducting channel of the 6th metal-oxide-semiconductor M6 is 1: K2: K4.The corresponding back that links to each other of the source terminal of the first metal-oxide-semiconductor M1, the first metal-oxide-semiconductor M2, the 3rd metal-oxide-semiconductor M3, the 4th metal-oxide-semiconductor M4 and the 6th metal-oxide-semiconductor M6 links to each other with corresponding bias supply.

After voltage V1 BE knot (base stage and emitter) pressure drop, on the 6th resistance R 6, form voltage Vclamp, and voltage Vclamp (for peak value threshold voltage) can be expressed as through the first triode Q1:

Vclamp＝V1-V _BE＝k1*V _REF-V _BE (4)

Simultaneously, after the BE knot pressure drop of voltage V1 through the second triode Q2, produce voltage V2 on first resistance R 1, voltage V2 forms electric current I 2 through first resistance R, 1 back, and described electric current I 2 can be expressed as:

$I2=\frac{\mathrm{<figure-callout\; id="1"\; label="k"\; filenames="HDA0000063704820000011.png,HDA0000063704820000012.png"\; state="\{\{state\}\}">k</figure-callout>}1*V_{\mathrm{REF}}-V_{\mathrm{BE}}}{R1}---\left(5\right)$

Described electric current I 2 also is the drain electrode end electric current of the 3rd metal-oxide-semiconductor M3, owing to form second image source 10 between the 3rd metal-oxide-semiconductor M3, the 4th metal-oxide-semiconductor M4 and the 6th metal-oxide-semiconductor M6, and the breadth length ratio of corresponding conducting channel is 1: K2: K4, thus can access the 4th metal-oxide-semiconductor M4 and the 6th metal-oxide-semiconductor M6 corresponding drain electrode electric current.The electric current of the 4th metal-oxide-semiconductor M4 drain electrode end is Islope, and electric current I slope can be expressed as:

Islope＝k2*I2 (6)

Then electric current I slope is slope compensation voltage Vslope and is expressed as by the voltage Vslope that second resistance R, 2 backs produce:

$\mathrm{Vslope}=R2*\mathrm{<figure-callout\; id="2"\; label="k"\; filenames="HDA0000063704820000012.png"\; state="\{\{state\}\}">k</figure-callout>}2*\mathrm{<figure-callout\; id="2"\; label="I"\; filenames="HDA0000063704820000012.png"\; state="\{\{state\}\}">I</figure-callout>}2=R2*\mathrm{<figure-callout\; id="2"\; label="k"\; filenames="HDA0000063704820000012.png"\; state="\{\{state\}\}">k</figure-callout>}2*\frac{\mathrm{<figure-callout\; id="1"\; label="k"\; filenames="HDA0000063704820000011.png,HDA0000063704820000012.png"\; state="\{\{state\}\}">k</figure-callout>}1*V_{\mathrm{REF}}-V_{\mathrm{<figure-callout\; id="1"\; label="BE\; R"\; filenames="HDA0000063704820000011.png,HDA0000063704820000012.png"\; state="\{\{state\}\}">BE</figure-callout>}}}{R}=k3*(k1*V_{\mathrm{REF}}-V_{\mathrm{BE}})---\left(7\right)$

Wherein,

In like manner, the electric current of the 6th metal-oxide-semiconductor M6 drain electrode end is I _DC, electric current I _DCCan be expressed as:

I _DC＝k4*I2 (8)

Electric current I then _DCVoltage V by 3 generations of the 3rd resistance R _DC, voltage V _DCCan be expressed as:

$V_{\mathrm{DC}}=R3*k4*\mathrm{<figure-callout\; id="2"\; label="I"\; filenames="HDA0000063704820000012.png"\; state="\{\{state\}\}">I</figure-callout>}2=R3*k4*\frac{\mathrm{<figure-callout\; id="1"\; label="k"\; filenames="HDA0000063704820000011.png,HDA0000063704820000012.png"\; state="\{\{state\}\}">k</figure-callout>}1*V_{\mathrm{REF}}-{\mathrm{<figure-callout\; id="1"\; label="V\; BE\; R"\; filenames="HDA0000063704820000011.png,HDA0000063704820000012.png"\; state="\{\{state\}\}">V</figure-callout>}}_{\mathrm{BE}}}{R}=k5*(k1*V_{\mathrm{REF}}-V_{\mathrm{BE}})---\left(9\right)$

Wherein,

The 3rd resistance R 3 is the identical resistance of resistance with second resistance R 2.

Can know voltage Vclamp, slope compensation voltage Vslope and voltage V by formula (4), (7) and (9) _DCBe (k1*V _REF-V _BE) the different proportion multiple, so their temperature coefficient is identical.

Consider the load capacity of current-mode DC-DC converter, the DC-DC converter is carried out voltage sample, obtaining corresponding sampled voltage is V _Sense, sampled voltage V wherein _SenseCan be expressed as:

Vsense＝k*I _L*R _S (10)

Wherein, R _SThe expression sampling resistor, I _LThe current value of filter inductance L is flow through in expression, and k is corresponding sample conversion coefficient.

By formula (4), (7), (9) and formula (10) as can be known, when the output loading of DC-DC converter reached peak current, PWM controller 5 turn-offed metal-oxide-semiconductor S1, i.e. the output switching activity of PWM comparator 6, at this moment,

Vclamp＝Vsense+V _DC+Vslope (11)

After in formula (4), (7), (9) and (10) substitution formula (11), can get,

$I_L=\frac{1-k5-k3}{k}*\frac{\mathrm{<figure-callout\; id="1"\; label="k"\; filenames="HDA0000063704820000011.png,HDA0000063704820000012.png"\; state="\{\{state\}\}">k</figure-callout>}1*V_{\mathrm{REF}}-V_{\mathrm{BE}}}{R_S}---\left(12\right)$

Wherein, in the formula (12), k, k1, k3 and k4 are adjustable proportionality coefficient, do not vary with temperature V _REFBe reference voltage, do not vary with temperature substantially, V _BEBe negative temperature coefficient; Then whole molecule is the voltage of positive temperature coefficient, is

$\frac{{\mathrm{<figure-callout\; id="1"\; label="k"\; filenames="HDA0000063704820000011.png,HDA0000063704820000012.png"\; state="\{\{state\}\}">k</figure-callout>}}_1*V_{\mathrm{REF}}-V_{\mathrm{BE}}}{R_S}=\frac{-\mathrm{\&Delta;}{V}_{\mathrm{BE}}}{{\mathrm{\&Delta;R}}_M}---\left(13\right)$

k ₁*V _REF-V _BE＝k ₁*V _REF-[V _BE0+(T-T ₀)*ΔV _BE]＝k ₁*V _REF-V _BE0-(T-T ₀)*ΔV _BE (14)

R _S＝k _x*R _S0*[1+(T-T ₀)*ΔR _M] (15)

Wherein, k _xBe the square resistance of metallic resistance, R _S0Be side's resistance of metallic resistance, Δ R _MTemperature coefficient for metallic resistance; V _BE0Is T for the pressure drop of BE knot in temperature ₀The time magnitude of voltage, Δ BE is the temperature coefficient of BE knot pressure drop.

A zero temperature needs that satisfy above formula satisfy following formula and get final product:

$\frac{\mathrm{<figure-callout\; id="1"\; label="k"\; filenames="HDA0000063704820000011.png,HDA0000063704820000012.png"\; state="\{\{state\}\}">k</figure-callout>}1*V_{\mathrm{REF}}-V_{\mathrm{BE}0}}{R_{S0}}=-\frac{{\mathrm{\&Delta;V}}_{\mathrm{BE}}}{\mathrm{\&Delta;}{R}_M}---\left(16\right)$

In the formula (16), Δ V _BE, Δ R _MTemperature coefficient different with different process, but can access the load current of zero temperature by the value of regulating k1 in the formula.

The load current of zero temperature is:

$I_0=\frac{\mathrm{<figure-callout\; id="1"\; label="k"\; filenames="HDA0000063704820000011.png,HDA0000063704820000012.png"\; state="\{\{state\}\}">k</figure-callout>}1*V_{\mathrm{REF}}-V_{\mathrm{BE}}}{R_S}---\left(17\right)$

Thereby also just obtained not temperature variant inductive current value

Thereby can guarantee that current-mode DC-DC converter in adopting the peak current FEEDBACK CONTROL, can guarantee the load capacity of DC-DC converter.

As shown in Figure 2: during use, sampled voltage Vsense and slope compensation voltage Vslope and direct voltage VDC are input to an end of PWM comparator after by accumulator, and the other end of PWM comparator links to each other with voltage Vcalmp.During work, oscillator links to each other with the PWM controller by rest-set flip-flop, by PWM controller control master power switch S1 conducting, power supply Vi is linked to each other with load by master power switch S1.By filter inductance L is carried out voltage sample, obtain sampled voltage Vsense; After reference voltage VREF and oscillator effect, obtain slope compensation voltage Vslope and direct voltage VDC, when load current change reach peak value threshold voltage Vclamp after, the output of PWM comparator, make the PWM controller turn-off master power switch S1, avoid damaging the DC-DC converter.By the effect of 10 of first image sources 9, second image source, and with the corresponding resistor coupling after, in the time of can avoiding the DC-DC converter to be operated in than big space rate, the load capacity of temperature effect DC-DC converter has reduced use cost, and is simple in structure, safe and reliable.

Claims (7)

1. circuit structure that is used for eliminating current-mode DC-DC converter slope compensation temperature effect, it is characterized in that: comprise operational amplifier (8), the output of described operational amplifier (8) links to each other with the gate terminal of the 5th metal-oxide-semiconductor (M5), and the source terminal of the 5th metal-oxide-semiconductor (M5) links to each other the back by the 4th resistance (R4) ground connection with the end of oppisite phase of operational amplifier (8); The drain electrode end of the 5th metal-oxide-semiconductor (M5) links to each other with the gate terminal of the drain electrode end of first metal-oxide-semiconductor (M1), first metal-oxide-semiconductor (M1) and the gate terminal of second metal-oxide-semiconductor (M2), the gate terminal of second metal-oxide-semiconductor (M2) links to each other with the gate terminal of first metal-oxide-semiconductor (M1), and the source terminal of second metal-oxide-semiconductor (M2) links to each other with the collector electrode of the source terminal of first metal-oxide-semiconductor (M1), first triode (Q1); The drain electrode end of second metal-oxide-semiconductor (M2) links to each other with the base stage of first triode (Q1), the base stage and the 5th resistance (R5) of second triode (Q2) respectively, and the 5th resistance (R5) is corresponding to the other end ground connection that links to each other with second metal-oxide-semiconductor (M2); The emitter of first triode (Q1) is by the 6th resistance (R6) ground connection; The emitter of second triode (Q2) is by first resistance (R1) ground connection; The collector electrode of second triode (Q2) links to each other with the drain electrode end of the 3rd metal-oxide-semiconductor (M3), the gate terminal of the 3rd metal-oxide-semiconductor (M3) and the gate terminal of the 4th metal-oxide-semiconductor (M4) respectively, the gate terminal of the 3rd metal-oxide-semiconductor (M3) links to each other with the gate terminal of the 4th metal-oxide-semiconductor (M4), the source terminal of the 3rd metal-oxide-semiconductor (M3) links to each other with the source terminal of second metal-oxide-semiconductor (M2), and links to each other with the source terminal of the 4th metal-oxide-semiconductor (M4) and the 6th metal-oxide-semiconductor (M6) respectively; The drain electrode end of the 4th metal-oxide-semiconductor (M4) is by second resistance (R2) ground connection, and the drain electrode end of the 6th metal-oxide-semiconductor (M6) is by the 3rd resistance (R3) ground connection, and the gate terminal of the 6th metal-oxide-semiconductor (M6) links to each other with the gate terminal of the 4th metal-oxide-semiconductor (M4).

2. according to the described circuit structure that is used for eliminating current-mode DC-DC converter slope compensation temperature effect of claim 1, it is characterized in that: the in-phase end of described operational amplifier (8) is the input of reference voltage VREF.

3. according to the described circuit structure that is used for eliminating current-mode DC-DC converter slope compensation temperature effect of claim 1, it is characterized in that: described first metal-oxide-semiconductor (M1), second metal-oxide-semiconductor (M2), the 3rd metal-oxide-semiconductor (M2), the 4th metal-oxide-semiconductor (M4), the 5th metal-oxide-semiconductor (M5) and the 6th metal-oxide-semiconductor (M6) are P type metal-oxide-semiconductor.

4. according to the described circuit structure that is used for eliminating current-mode DC-DC converter slope compensation temperature effect of claim 1, it is characterized in that: described first metal-oxide-semiconductor (M1) forms first image source (9) with second metal-oxide-semiconductor (M2); First metal-oxide-semiconductor (M1) is identical with the breadth length ratio of second metal-oxide-semiconductor (M2) conducting channel.

5. according to the described circuit structure that is used for eliminating current-mode DC-DC converter slope compensation temperature effect of claim 1, it is characterized in that: described the 3rd metal-oxide-semiconductor (M3), the 4th metal-oxide-semiconductor (M4) and the 6th metal-oxide-semiconductor (M6) form second image source (10); The breadth length ratio of the 3rd metal-oxide-semiconductor (M3), the 4th metal-oxide-semiconductor (M4) and the 6th metal-oxide-semiconductor (M6) conducting channel is 1: K2: K4.

6. according to the described circuit structure that is used for eliminating current-mode DC-DC converter slope compensation temperature effect of claim 1, it is characterized in that: described first resistance (R1), second resistance (R2), the 3rd resistance (R3), the 4th resistance (R4), the 5th resistance (R5) and the 6th resistance (R6) are the resistance of uniform temp coefficient.

7. according to the described circuit structure that is used for eliminating current-mode DC-DC converter slope compensation temperature effect of claim 6, it is characterized in that: described second resistance (R2) is identical with the resistance of the 3rd resistance (R3).

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