CN102263088A - Packaging structure comprising multiple chips - Google Patents
Packaging structure comprising multiple chips Download PDFInfo
- Publication number
- CN102263088A CN102263088A CN201110199499XA CN201110199499A CN102263088A CN 102263088 A CN102263088 A CN 102263088A CN 201110199499X A CN201110199499X A CN 201110199499XA CN 201110199499 A CN201110199499 A CN 201110199499A CN 102263088 A CN102263088 A CN 102263088A
- Authority
- CN
- China
- Prior art keywords
- chip
- chips
- mounted member
- accompanying
- pin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The invention provides a packaging structure comprising multiple chips. The packaging structure comprises a mounting part, a plurality of pins and a plurality of chips, wherein the mounting part comprises a front face and a back face; the chips are stacked on the surface of the mounting part along a direction vertical to the surface of the front face of the mounting part, and pads needed to be electrically connected with a periphery are exposed; and the exposed pads are electrically connected with corresponding pins through metal lead wires.
Description
Technical field
The present invention relates to the semiconductor packages field tests, relate in particular to a kind of encapsulating structure that comprises a plurality of chips.
Background technology
Electronic product has more and more the trend to small model development, in the power management of computer notebook etc. a kind of power supply direct current conversion twin-core sheet device is arranged at present, and two chips of this device are arranged on the lead frame side by side, generally use the SOIC8 encapsulation.
It shown in the accompanying drawing 1 a kind of typical twin-core chip package schematic diagram of prior art, comprise two chips 111 and 112, be mounted on the surface of mounted member 131 and 132 respectively, and a plurality of pins, comprise pin 150, in the present embodiment, chip 111 and 112 each field-effect transistor naturally, the number of pin 150 is 8.For the clear position that shows chip and pin, accompanying drawing 1 does not provide metal lead wire between the two, and accompanying drawing 2 is between accompanying drawing 1 chips and the electricity annexation schematic diagram of chip and each pin.
The circuit that two field-effect transistors shown in the accompanying drawing 1 constitute is widely used in the power supply direct current conversion occasions of notebook computer.Employing is similar to the prior art shown in attached Fig. 1 and 2 the circuit that two field-effect transistors constitute is encapsulated, package dimension is approximately 4.9 * 6.0 * 1.45, unit is a millimeter, the restriction that the packaging body of this size is obviously serious the thin miniaturization development of notebook.
Summary of the invention
Technical problem to be solved by this invention is, a kind of encapsulating structure that comprises a plurality of chips is provided, and can reduce package dimension, helps consumption electronic products such as notebook computer and develops to miniaturization.
In order to address the above problem, the invention provides a kind of encapsulating structure that comprises a plurality of chips, comprise a mounted member, a plurality of pin and a plurality of chip, described mounted member comprises a positive and back side, described chip is to be arranged at the mounted member surface along piling up perpendicular to the direction of mounted member front face surface, and exposing the pad that chip need connect with peripheral electricity, the pad that exposes connects by metal lead wire electricity with corresponding pin.
As optional technical scheme, the back side of described mounted member is provided with projection, and the top of described projection and the top of pin are in same horizontal plane.
As optional technical scheme, interconnect by conductive solder between described a plurality of chips and between chip and the mounted member.
The invention has the advantages that, adopt stacking method to carry out the encapsulation of multicore sheet, inner a plurality of chips have been saved the space that chip chamber keeps, thereby have been reduced the size of chip by being arranged side by side then become and pile up setting.
Description of drawings
It shown in the accompanying drawing 1 a kind of typical twin-core chip package schematic diagram of prior art.
Accompanying drawing 2 is between accompanying drawing 1 chips and the electricity annexation schematic diagram of chip and each pin.
It shown in the accompanying drawing 3 schematic perspective view of the lead frame of the described encapsulating structure that comprises a plurality of chips of the specific embodiment of the invention.
Accompanying drawing 4 is the perspective view at visual angle, the lead frame back side shown in the accompanying drawing 3.
Accompanying drawing 5 is accompanying drawing 3 and the structural representation of the lead frame shown in the accompanying drawing 4 after pasting chip.
Accompanying drawing 6 is the chip-packaging structure schematic diagrames that comprised electricity syndeton between chip shown in the accompanying drawing 5 and the pin.
Accompanying drawing 7 is that structure shown in the accompanying drawing 6 is carried out plastic packaging structural representation afterwards.
Embodiment
Below in conjunction with accompanying drawing the embodiment that comprises the encapsulating structure of a plurality of chips provided by the invention is elaborated.
Be the schematic perspective view of the lead frame of the described encapsulating structure that comprises a plurality of chips of this embodiment shown in the accompanying drawing 3, accompanying drawing 3 is the perspective view at visual angle, the lead frame back side shown in the accompanying drawing 4.With reference to the accompanying drawings 3 with accompanying drawing 4, shown in encapsulating structure comprise mounted member 30, with pin 311,312,313 and 314 the expression a plurality of pins.Described mounted member 30 comprises positive 301 and one back side 302.In the present embodiment, the back side 302 of mounted member 30 is provided with projection 350.The top of described protruding 350 top and pin 311,312,313 and 314 is in same horizontal plane, and the heat that this design helps that further chip is produced at work is dispersed in the environment by mounted member 10 and goes.
With reference to the accompanying drawings 5, be accompanying drawing 3 and the structural representation of the lead frame shown in the accompanying drawing 4 after pasting chip, described chip-packaging structure comprises a plurality of chips of representing with first chip 331 and second chip 333.Described first chip 331 and second chip 333 are to be arranged at mounted member 30 surfaces along piling up perpendicular to the direction on 301 surfaces, front of mounted member 30.Interconnect by conductive solder between first chip 331 and second chip 333 and between first chip 331 and the mounted member 30.
With reference to the accompanying drawings 6, be the chip-packaging structure schematic diagram that has comprised electricity syndeton between chip shown in the accompanying drawing 5 and the pin.First chip 331 and second chip 333 expose the pad that need be connected with peripheral electricity, and the pad that exposes connects by metal lead wire 370 electricity with corresponding pin.When first chip 331 and second chip 333 were field-effect transistor, the electricity annexation schematic diagram of these two chips can be with reference to the situation shown in the accompanying drawing in the prior art 2.For each field-effect transistor, its source electrode is separately positioned on two different surfaces of this chip with draining, and control by grid, this mounts structure and has utilized in this special structure and the circuit a transistorized source/drain electrode with another transistorized source/drain electrode connection characteristics, two chips vertically are mounted on together, have reached the effect of saving encapsulated space.In fact, for the multi-chip structure that comprises first chip and second chip, as long as all being direct electricity, lip-deep all electrodes of first chip are connected on the counter electrode on second chip, one surface, promptly can be with the surface mount of two chips together by the method, for two lip-deep electrodes all is under the situation of unitary electrode, as described in this embodiment, can both be fitted by the method for coated with conductive scolder or conductive film, if each lip-deep electrode all is a plurality of, also can be by forming patterned conductive solder or conductive film, to realize interconnected each other (being similar to flip chip bonding technology) of a plurality of electrodes in the process of mounting.
Be that structure shown in the accompanying drawing 6 is carried out structural representation after the plastic packaging shown in the accompanying drawing 7, comprise the pin 311,312,313 that exposes and 314 and the projection 350 that is provided with of mounted member 30 back sides.Because the back side 302 of mounted member 30 is provided with projection 350, and projection 350 the top and the top of pin 311,312,313 and 314 are in same horizontal plane, go so the heat that first chip 331 and second chip 333 can be produced at work after plastic packaging is dispersed in the environment by mounted member 30.
Adopt the described stacking method of this embodiment to carry out the encapsulation of multicore sheet, inner a plurality of chips have been saved the space that chip chamber keeps, thereby have been reduced the size of chip by being arranged side by side then become and pile up setting.With power supply direct current conversion twin-core sheet device is example, and chip size is reduced to 3.3 * 3.3 * 0.8 (unit: millimeter) from original 4.9 * 6.0 * 1.459.
The above only is a preferred implementation of the present invention; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the principle of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (4)
1. encapsulating structure that comprises a plurality of chips, comprise a mounted member, a plurality of pin and a plurality of chip, described mounted member comprises a positive and back side, it is characterized in that, described chip is to be arranged at the mounted member surface along piling up perpendicular to the direction of mounted member front face surface, and exposing the pad that chip need connect with peripheral electricity, the pad that exposes connects by metal lead wire electricity with corresponding pin.
2. the encapsulating structure that comprises a plurality of chips according to claim 1 is characterized in that the back side of described mounted member is provided with projection.
3. the encapsulating structure that comprises a plurality of chips according to claim 2 is characterized in that, the top of described projection and the top of pin are in same horizontal plane.
4. the encapsulating structure that comprises a plurality of chips according to claim 1 is characterized in that, interconnects by conductive solder between described a plurality of chips and between chip and the mounted member.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110199499XA CN102263088A (en) | 2011-07-15 | 2011-07-15 | Packaging structure comprising multiple chips |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110199499XA CN102263088A (en) | 2011-07-15 | 2011-07-15 | Packaging structure comprising multiple chips |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102263088A true CN102263088A (en) | 2011-11-30 |
Family
ID=45009664
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110199499XA Pending CN102263088A (en) | 2011-07-15 | 2011-07-15 | Packaging structure comprising multiple chips |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102263088A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102664175A (en) * | 2012-05-02 | 2012-09-12 | 无锡虹光半导体技术有限公司 | Multi-chip packaging structure of power conversion chip |
| CN105575941A (en) * | 2016-02-03 | 2016-05-11 | 日银Imp微电子有限公司 | High-power resonant power supply control chip realized by double-chip package |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101393908A (en) * | 2007-09-17 | 2009-03-25 | 南茂科技股份有限公司 | Encapsulation construction of multi-chip stack |
| CN101419964A (en) * | 2007-10-26 | 2009-04-29 | 英飞凌科技股份公司 | Device with a plurality of semiconductor chips |
-
2011
- 2011-07-15 CN CN201110199499XA patent/CN102263088A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101393908A (en) * | 2007-09-17 | 2009-03-25 | 南茂科技股份有限公司 | Encapsulation construction of multi-chip stack |
| CN101419964A (en) * | 2007-10-26 | 2009-04-29 | 英飞凌科技股份公司 | Device with a plurality of semiconductor chips |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102664175A (en) * | 2012-05-02 | 2012-09-12 | 无锡虹光半导体技术有限公司 | Multi-chip packaging structure of power conversion chip |
| CN105575941A (en) * | 2016-02-03 | 2016-05-11 | 日银Imp微电子有限公司 | High-power resonant power supply control chip realized by double-chip package |
| CN105575941B (en) * | 2016-02-03 | 2018-01-02 | 中芯集成电路（宁波）有限公司 | The high power resonant vibration power supply control chip that a kind of dual chip encapsulation is realized |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20080315388A1 (en) | Vertical controlled side chip connection for 3d processor package | |
| KR101801945B1 (en) | Semiconductor chip and semiconductor package having the same | |
| KR20100103418A (en) | Flexible packaging for chip-on-chip and package-on-package technologies | |
| CN101150118A (en) | Semiconductor device | |
| JP2007184385A5 (en) | ||
| TW447059B (en) | Multi-chip module integrated circuit package | |
| TWI655737B (en) | Semiconductor package including a plurality of stacked chips | |
| CN206282838U (en) | The integrated encapsulation structure of passive device and active device | |
| CN103250246A (en) | Method and system for thin multi chip stack package with film on wire and copper wire | |
| CN106653743A (en) | Integrated power module | |
| US20210098426A1 (en) | Packaging structure, and forming method and packaging method thereof | |
| KR20110056205A (en) | Semiconductor chip and stacked semiconductor package havng the same | |
| KR101096455B1 (en) | Heat dissipating uint and method for manufacturing thereof and stack package using the same | |
| CN203774293U (en) | 3D packaging structure of integrated circuit | |
| CN102263088A (en) | Packaging structure comprising multiple chips | |
| TW201517241A (en) | Package module with offset stack components | |
| TW201508895A (en) | Package module with offset stack components | |
| TW201526198A (en) | Package module with stack components | |
| KR20140148273A (en) | Semiconductor package and method for fabricating the same | |
| CN102332410A (en) | Packaging method and structure of chip | |
| US8907490B2 (en) | Semiconductor packages having the first and second chip inclined sidewalls contact with each other | |
| CN101127332A (en) | Pin ball grid array encapsulation structure of wafer | |
| KR20080067891A (en) | Multi chip package | |
| JP2007287820A5 (en) | ||
| CN204946895U (en) | A kind of encapsulating structure of multi-chip |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C12 | Rejection of a patent application after its publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20111130 |