CN102263019B - Method for manufacturing self-aligned trench power semiconductor structure - Google Patents
Method for manufacturing self-aligned trench power semiconductor structure Download PDFInfo
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- CN102263019B CN102263019B CN201010186755.7A CN201010186755A CN102263019B CN 102263019 B CN102263019 B CN 102263019B CN 201010186755 A CN201010186755 A CN 201010186755A CN 102263019 B CN102263019 B CN 102263019B
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Abstract
The invention provides a method for manufacturing a self-aligned trench power semiconductor structure. The method comprises the following steps of: a) forming a trench polysilicon grid structure in a silicon base material; b) forming a self-aligned polysilicon extension structure which extends upwards from the trench polysilicon grid structure, wherein the self-aligned polysilicon extension structure is narrower than the trench polysilicon grid structure; c) oxidizing the self-aligned polysilicon extension structure to form a silicon oxide protrusion structure above the trench polysilicon grid structure; and d) forming a spacer structure on the side edge of the silicon oxide protrusion structure to define a source contact window in the silicon base material. In the manufacturing method provided by the invention, a spacing distance between the trench polysilicon grid structure and the source contact window is shortened by using a manufacture procedure of self-alignment, so that the limit of a lithography process can be overcome, yield control of the manufacture procedure can be enhanced, the characteristic uniformity of elements at different positions of a wafer can be improved, the cost is low and the feasibility is high.
Description
Technical field
The present invention relates to a kind of manufacture method of trench power semiconductor structure, particularly the manufacture method of a kind of autoregistration (self-aligned) trench semiconductor structure.
Background technology
Figure 1A and Fig. 1 C are the making flow process of a typical trench power semiconductor structure.As shown in Figure 1A, first, on a silicon substrate 110, make gate trench 120.Subsequently, the inner surface along gate trench 120 forms a grid oxic horizon 130.Next, deposit spathic silicon material is in the surface of silicon substrate 110, and removes unnecessary polycrystalline silicon material to eat-back the mode of (etching back), forms a grid polycrystalline silicon structure 140 in this gate trench 120.
Next, as shown in Figure 1B, in implanted ions mode, implant alloy in silicon substrate 110, to form body 150 all around gate grooves 120.Then, implant the alloy of different conductivity types in body 150, to form source doping region 160 in the upper part of body layer 150.Next, as shown in Figure 1 C, deposit a dielectric layer 170 in the exposed surface of silicon substrate 110, and fill up gate trench 120.Then, in lithography mode, in dielectric layer 170 and body 150, form contact hole 180 with exposed source doping region 160.
The development of groove power semiconductor element shrink technology, can be subject to the restriction of the limit of gold-tinted micro-photographing process.Be limited to groove and the critical width (critical dimension) of contact hole and the admissible error (tolerance) of aiming at control, gate trench 120 cannot reduce arbitrarily with the distance of contact hole 180, otherwise easily produces leakage current, causes the variation of critical voltage or resistance to snowslide (UIS) ability declines.
Based on this, be limited to groove and the critical width of contact hole and the range of allowable error of aiming at control, how to increase the component density of trench power semiconductor structure, be the art problem to be solved.
Summary of the invention
Main purpose of the present invention is to provide a kind of manufacture method of high density structure of trench power semiconductor, utilize the mode of autoregistration (self alignment), overcome the critical width of gate trench and contact hole and aim at the restriction that the range of allowable error controlled causes for component density.
The invention provides a kind of manufacture method of self-aligned trench power semiconductor structure, comprise the following steps: a) to form a trench polysilicon grid structure in a silicon substrate; B) form an autoregistration polysilicon extended structure and extended upward by trench polysilicon grid structure, the width of this autoregistration polysilicon extended structure is less than the width of trench polysilicon grid structure; C) be oxidized aforementioned autoregistration polysilicon extended structure, to form the outstanding structure of silicon monoxide in trench polysilicon grid structure top; And d) form one first wall structure (spacer) in the side of the outstanding structure of silica, to define one source pole contact hole in silicon substrate.
In other words, the invention provides a kind of manufacture method of self-aligned trench power semiconductor structure, it is characterized in that, comprise the following steps:
Form a trench polysilicon grid structure in a silicon substrate;
Form an autoregistration polysilicon extended structure and extended upward by this trench polysilicon grid structure, the width of this autoregistration polysilicon extended structure is less than the width of this trench polysilicon grid structure;
Be oxidized this autoregistration polysilicon extended structure, form the outstanding structure of silicon monoxide in this trench polysilicon grid structure top; And
Form one first wall structure in the side of the outstanding structure of this silica, to define one source pole contact hole in this silicon substrate, wherein the spacing distance of this source electrode contact hole and this trench polysilicon grid structure is determined by the thickness of this first wall structure.
About the advantages and spirit of the present invention, can be further understood by means of the following detailed description and accompanying drawings.
Accompanying drawing explanation
Figure 1A and Fig. 1 C are the making flow process of a typical trench power semiconductor structure;
The first embodiment of the manufacture method that Fig. 2 A to Fig. 2 I is trench power semiconductor structure of the present invention;
The second embodiment of the manufacture method that Fig. 3 A to Fig. 3 C is trench power semiconductor structure of the present invention;
The 3rd embodiment of the manufacture method that Fig. 4 A to Fig. 4 B is trench power semiconductor structure of the present invention;
The 4th embodiment of the manufacture method that Fig. 5 A to Fig. 5 D is trench power semiconductor structure of the present invention.
[main element description of reference numerals]
Gate trench 120
Grid oxic horizon 130
Grid polycrystalline silicon structure 140
Contact hole 180
Gate trench 230
Gate dielectric 232
Trench polysilicon grid structure 240
The second wall structure 250
Autoregistration polysilicon extended structure 242
Silica is given prominence to structure 260
The first wall structure 265
Source electrode contact hole 282
Heavily doped region 285
Gate trench 330
Gate dielectric 332
Trench polysilicon grid structure 340
The second wall structure 350
Autoregistration polysilicon extended structure 342
Thick oxide layer 362
Gate trench 430
Gate dielectric 432
Polysilicon structure 440
Autoregistration polysilicon extended structure 440a
Trench polysilicon grid structure 440b
Silica is given prominence to structure 460
Embodiment
Technical characterictic of the present invention utilizes hard cover curtain layer (Hard mask) and polysilicon to eat-back (Poly etch back) rear formed height fall, in polysilicon gate top, forms wall structure (spacer).And utilize wall organization definition space out, then carry out a polysilicon deposition and eat-back (Poly deposition & etch back) step, to have formed the outstanding structure of polysilicon.Due to the thinner thickness of the outstanding structure of this polysilicon, therefore can utilize thermal oxidation processing procedure (Thermal oxide process) to be oxidized the outstanding structure of this polysilicon.The high low head of the outstanding structure of this thermal oxidation silica that processing procedure forms and silicon substrate just can be applicable to make wall structure, to define the position of contact hole.Can avoid thus traditional gold-tinted processing procedure easily to produce the shortcoming of alignment error.
The first embodiment of the manufacture method that Fig. 2 A to Fig. 2 I is trench power semiconductor structure of the present invention.As shown in Figure 2 A, first, form a cover curtain layer 220 in the upper surface of a silicon substrate 210.Cover curtain layer 220 has opening 222 definition one gate trenchs 230.This cover curtain layer 220 can adopt typical hard cover curtain layer (hard mask), and its constituent material is generally silica or silicon nitride.Subsequently, by cover curtain layer 220 etching silicon base materials 210, to form gate trench 230 in silicon substrate 210.Next, form the inner surface of gate dielectric 232 cover gate grooves 230.Subsequently, as shown in Figure 2 B, deposit spathic silicon material, on silicon substrate 210, and is inserted in gate trench 230.And then impose and eat-back processing procedure, to form trench polysilicon grid structure 240 in gate trench 230.
As shown in Figure 2 B, after forming trench polysilicon grid structure 240, on the sidewall of the direct opening 222 at cover curtain layer 220, make the second wall structure (spacer) 250.These the second wall structure 250 upper surfaces by trench polysilicon grid structure 240 extend upward.Next, as shown in Figure 2 C, in the second defined space of wall structure 250, insert polycrystalline silicon material, to form autoregistration polysilicon extended structure 242 in trench polysilicon grid structure 240 tops.By the making of the second wall structure 250, the width of autoregistration polysilicon extended structure 242 is less than the width of trench polysilicon grid structure 240, and the central authorities of autoregistration polysilicon extended structure 242 rough alignment trench polysilicon grid structures 240.
Next, as shown in Figure 2 D, remove cover curtain layer 220 and the second wall structure 250, make outside the side of autoregistration polysilicon extended structure 242 and the upper surface of trench polysilicon grid structure 240 be exposed to.This step can adopt selective etch processing procedure, reaches the object that removes cover curtain layer 220 and the second wall structure 250.With regard to a preferred embodiment, aforementioned cover curtain layer 220 and the second wall structure 250 can utilize silica material to make, to simplify this selective etch processing procedure.
Subsequently, as shown in Figure 2 E, autoregistration polysilicon extended structure 242 and the exposed surface of trench polysilicon grid structure 240 are imposed to an oxidation process, to form the outstanding structure 260 of silicon monoxide in the top of trench polysilicon grid structure 240.Due to outside the side of autoregistration polysilicon extended structure 242 is exposed to completely, and the width of autoregistration polysilicon extended structure 242 is much smaller than the width of trench polysilicon grid structure 240.Therefore, this oxidation process only can form oxide layer at the surf zone of trench polysilicon grid structure 240, and can not cause too much influence for the sectional dimension of trench polysilicon grid structure 240.Secondly, in the present embodiment, due to outside the upper surface of silicon substrate 210 is exposed to, therefore, this oxidation process can be simultaneously form an oxide layer 262 at the upper surface of silicon substrate 210, for follow-up ion implantation manufacture process.
Next, as shown in Figure 2 F, in implanted ions mode, implant the first conductivity type alloy in silicon substrate 210, to form body 270 around trench polysilicon grid structure 240.Then, in implanted ions mode, implant the second conductivity type alloy in the surf zone of silicon substrate 210, to form source doping region 280 in the upper part of body 270.Aforementioned the first conductivity type alloy and the second conductivity type alloy can be respectively P type alloy and N-type alloy, or N-type alloy and P type alloy.Then, as shown in Figure 2 F, form one first wall structure 265 in the sidewall of the outstanding structure 260 of silica, to define the position of source electrode contact hole.
Next, as shown in Fig. 2 G and Fig. 2 H, directly utilize this first wall structure 265 for shielding, etching covers the oxide layer 262 on silicon substrate 210 surfaces and the source doping region 280 of part, to form source electrode contact hole 282, extends in silicon substrate 210.Subsequently, as shown in Fig. 2 H, by the first wall structure 265, implant the first conductivity type alloy to the bottom of source electrode contact hole 282, to form a heavily doped region 285 in body 270.Finally, as shown in Fig. 2 I, form one source pole metal level 290 on silicon substrate 210, to be electrically connected to source doping region 280 and body 270.
As aforementioned, autoregistration polysilicon extended structure 242 central authorities in alignment with trench polysilicon grid structure 240.Therefore, the outstanding structure 260 of oxidation autoregistration polysilicon extended structure 242 formed silica also can be in alignment with the centre of trench polysilicon grid structure 240.The present embodiment directly utilize be made in the outstanding structure 260 of this silica sidewall the first wall structure 265 define the position of source electrode contact hole 282, can avoid the generation of the alignment error between different micro-photographing process.In addition, in the present embodiment, the spacing distance of source electrode contact hole 282 and trench polysilicon grid structure 240 is roughly that the thickness by the first wall structure 265 is determined, therefore, can avoid the restriction of the critical width of micro-photographing process.Again, the width that the present embodiment is formed at the outstanding structure 260 of silica of trench polysilicon grid structure 240 tops is less than the width of trench polysilicon grid structure 240, more contribute to reduce the spacing distance of source electrode contact hole 282 and trench polysilicon grid structure 240, to reach the object that improves component density.
The second embodiment of the manufacture method that Fig. 3 A to Fig. 3 C is trench power semiconductor structure of the present invention.Below only with regard to the difference place of the present embodiment and aforementioned the first embodiment, describe.First, as shown in Figure 3A, utilize a photoresist layer (not shown) to form a gate trench 330 in silicon substrate 310.Subsequently, form the inner surface of gate dielectric 332 cover gate grooves 330.Next, insert polycrystalline silicon material in gate trench 330 to form trench polysilicon grid structure 340.This trench polysilicon grid structure 340 is positioned at the lower part of gate trench 330, upper surface interval one predeterminable range of its upper surface and silicon substrate 310.Subsequently, form the second wall structure 350 in gate trench 330.This second wall structure 350 is positioned on the sidewall of upper part of gate trench 330.
Next, as shown in Figure 3 B, insert polycrystalline silicon material in the second defined space of wall structure 350, and impose and eat-back processing procedure, to form autoregistration polysilicon extended structure 342 in trench polysilicon grid structure 340 tops.Subsequently, as shown in Figure 3 C, form the upper surface that a protective layer 352 covers autoregistration polysilicon extended structure 342.And then with mode of oxidizing, form a thick oxide layer 362 in the surf zone of silicon substrate 310.Protective layer 352 is oxidized to silica in order to prevent autoregistration polysilicon extended structure 342 in the oxidation step of Fig. 3 C.Therefore, protective layer 352 can be by silicon nitride, silica or other effectively the material of isolating oxygen atom formed.
Next, remove the thick oxide layer 362, the second wall structure 350 and protective layer 352 that are positioned at silicon substrate 310 upper surfaces, make outside autoregistration polysilicon extended structure 342 is exposed to, and protrude from the upper surface of silicon substrate 310.When the second wall structure 350 and protective layer 352 are all while being consisted of silica, can pass through etching mode, remove thick oxide layer 362, the second wall structure 350 and protective layer 352 simultaneously.When the second wall structure 350 and protective layer 352 are all while being consisted of silicon nitride, can first utilize the mode of selective etch to remove thick oxide layer 362, and then remove the second wall structure 350 and protective layer 352.Certainly, aforementioned the second wall structure 350 is consisted of different materials from protective layer 352.The successive process of the present embodiment, as first embodiment of the invention (please refer to Fig. 2 D), does not repeat them here.
The 3rd embodiment of the manufacture method that Fig. 4 A and Fig. 4 B are trench power semiconductor structure of the present invention.Below only with regard to the difference place of the present embodiment and aforementioned the second embodiment, describe.The step of Fig. 4 A is accepted Fig. 3 B.As shown in Figure 4 A, to form autoregistration polysilicon extended structure 342 after the step of trench polysilicon grid structure 340 tops, form the upper surface that a protective layer 352 covers autoregistration polysilicon extended structure 342.Next; shown in comparison diagram 3C and Fig. 4 B; the present embodiment does not adopt mode of oxidizing to form thick oxide layer 362; but directly utilize protective layer 352 and the second wall structure 350, be shielding, by the upper surface of silicon substrate 310, for example, with etching mode (selective etch mode), cut down the thickness of silicon substrate 310.Make autoregistration polysilicon extended structure 342 protrude from the upper surface of silicon substrate 310.Then, then remove protective layer 352 and the second wall structure 350, make outside autoregistration polysilicon extended structure 342 is exposed to.Aforesaid protective layer 352 and the second wall structure 350 are consisted of materials such as silica or silicon nitrides, are beneficial to adopt etching mode to cut down the thickness of silicon substrate 310.
It is shielding etching silicon base material 310 that previous embodiment is utilized protective layer 352 and the second wall structure 350.But, the present invention is not limited to this.The present embodiment can also only utilize the protective layer 352 that is positioned at autoregistration polysilicon extended structure 342 tops for shielding, and the directive etching technique of collocation tool, as reactive ion etching (RIE), carrys out etching silicon base material 310.
The 4th embodiment of the manufacture method that Fig. 5 A to Fig. 5 D is trench power semiconductor structure of the present invention.Below only with regard to the difference place of the present embodiment and aforementioned the first embodiment, describe.As shown in Figure 5A, first, form a cover curtain layer 420 in the upper surface of a silicon substrate 410.Subsequently, by cover curtain layer 420 etching silicon base materials 410, to form gate trench 430 in silicon substrate 410.Next, form the inner surface of gate dielectric 432 cover gate grooves 430.Subsequently, deposit spathic silicon material, on silicon substrate 410, and is inserted in the opening 422 of gate trench 430 and cover curtain layer 420.And then polycrystalline silicon material is imposed and eat-backs processing procedure, to form a polysilicon structure 440.This polysilicon structure 440 is extended upwardly in cover curtain layer 420 by gate trench 430.
Next, as shown in Figure 5 B, remove cover curtain layer 420, make outside the upper part of polysilicon structure 440 is exposed to.Then, utilize the exposed surface of one oxidation process oxidation polysilicon structure 440.Next, as shown in Figure 5 C, in etched mode, remove the part of polysilicon structure 440 surface oxidations, to cut down the width of the upper part of polysilicon structure 440.As shown in FIG., outside the upper part of this polysilicon structure 440 is exposed to, lower part is to be positioned at silicon substrate 410.Therefore, after peroxidating and etched processing procedure, upper part at this polysilicon structure 440 can form the upper surface that the narrower autoregistration polysilicon extended structure 440a of a width protrudes from silicon substrate 410, and lower part forms a trench polysilicon grid structure 440b and is positioned at silicon substrate 410.
Aforementioned manufacturing process first utilizes one oxidation process oxidation to be exposed to outer polysilicon structure 440, and then with etching mode, cuts down the width of the upper part of polysilicon structure 440.But, the present invention is not limited to this.With regard to an embodiment, please refer to shown in Fig. 5 A, after removing cover curtain layer 420, can directly for being exposed to outer polysilicon structure 440, carry out etching, to form autoregistration polysilicon extended structure 440a as shown in Figure 5 C.
Subsequently, as shown in Figure 5 D, then carry out once oxidation processing procedure, make autoregistration polysilicon extended structure 440a completely oxidized, to form the outstanding structure 460 of silica, be covered in trench polysilicon grid structure 440b top.The subsequent step of the present embodiment and first embodiment of the invention (please refer to Fig. 2 E) are similar, do not repeat them here.
As aforementioned, manufacture method provided by the present invention utilizes the processing procedure of autoregistration (Self-Alignment) to dwindle the spacing distance between trench polysilicon grid structure and source electrode contact hole, therefore, can overcome the limit of micro-photographing process.Secondly, manufacture method provided by the present invention also contributes to the yield that promotes processing procedure to control, and improves the uniformity of the element characteristic of the upper diverse location of wafer (Wafer).In addition, manufacture method provided by the present invention is also easily arranged in pairs or groups at existing groove power semiconductor processing procedure, is specially adapted to the processing procedure of narrow groove, therefore, has advantages of that cost is low and feasibility is high.
The above; it is only preferred embodiment of the present invention; when not limiting the claims in the present invention protection range with this, i.e. all simple equivalences of doing according to the claims in the present invention and invention description content change and revise, and all still belong in the scope that the claims in the present invention contain.Arbitrary embodiment of the present invention or claim must not reach disclosed whole objects or advantage or feature in addition.In addition, summary part and title are only for the use of auxiliary patent document search, are not used for limiting claim protection range of the present invention.
Claims (13)
1. a manufacture method for self-aligned trench power semiconductor structure, is characterized in that, comprises the following steps:
Form a trench polysilicon grid structure in a silicon substrate;
Form an autoregistration polysilicon extended structure and extended upward by this trench polysilicon grid structure, the width of this autoregistration polysilicon extended structure is less than the width of this trench polysilicon grid structure;
Be oxidized this autoregistration polysilicon extended structure, form the outstanding structure of silicon monoxide in this trench polysilicon grid structure top; And
Form one first wall structure in the side of the outstanding structure of this silica, to define one source pole contact hole in this silicon substrate, wherein the spacing distance of this source electrode contact hole and this trench polysilicon grid structure is determined by the thickness of this first wall structure.
2. the manufacture method of self-aligned trench power semiconductor structure as claimed in claim 1, is characterized in that, the step that forms this trench polysilicon grid structure comprises:
Form a cover curtain layer in the upper surface of this silicon substrate, this cover curtain layer has an opening and defines a gate trench;
By this this silicon substrate of cover curtain layer etching, to form this gate trench in this silicon substrate;
Form the inner surface that a gate dielectric covers this gate trench; And
Insert polycrystalline silicon material in this gate trench.
3. the manufacture method of self-aligned trench power semiconductor structure as claimed in claim 2, is characterized in that, the step that forms this autoregistration polysilicon extended structure comprises:
Form one second wall structure in the side of this opening of this cover curtain layer; And
Insert polycrystalline silicon material in this opening, to form this autoregistration polysilicon extended structure.
4. the manufacture method of self-aligned trench power semiconductor structure as claimed in claim 3, is characterized in that, this second wall structure is consisted of silica or silicon nitride.
5. the manufacture method of self-aligned trench power semiconductor structure as claimed in claim 2, is characterized in that, this cover curtain layer is consisted of silica.
6. the manufacture method of self-aligned trench power semiconductor structure as claimed in claim 1, is characterized in that, this autoregistration polysilicon extended structure is completely oxidized, to form the upper surface of outstanding this silicon substrate of the outstanding structure of this silica.
7. the manufacture method of self-aligned trench power semiconductor structure as claimed in claim 1, is characterized in that, is oxidized the upper surface of this trench polysilicon grid structure of step simultaneous oxidation of this autoregistration polysilicon extended structure.
8. the manufacture method of self-aligned trench power semiconductor structure as claimed in claim 2, it is characterized in that, this polycrystalline silicon material is inserted this gate trench and this opening to form a polysilicon structure, the lower part of this polysilicon structure forms this trench polysilicon grid structure, and the step that forms this autoregistration polysilicon extended structure comprises:
Remove this cover curtain layer, make outside the upper part of this polysilicon structure is exposed to; And
Cut down the width of this upper part of this polysilicon structure, to form outstanding this silicon substrate of this autoregistration polysilicon extended structure.
9. the manufacture method of self-aligned trench power semiconductor structure as claimed in claim 8, is characterized in that, the step of width of cutting down this upper part of this polysilicon structure comprises:
With mode of oxidizing, form an oxide layer in the surface of this upper part of this polysilicon structure; And
Remove this oxide layer, to form outstanding this silicon substrate of this autoregistration polysilicon extended structure.
10. the manufacture method of self-aligned trench power semiconductor structure as claimed in claim 1, is characterized in that, the step that forms this trench polysilicon grid structure comprises:
Utilize a photoresist layer to form a gate trench in this silicon substrate;
Form the inner surface that a gate dielectric covers this gate trench; And
Insert polycrystalline silicon material in this gate trench, to form this trench polysilicon grid structure in the lower part of this gate trench.
The manufacture method of 11. self-aligned trench power semiconductor structures as claimed in claim 10, is characterized in that, the step that forms this autoregistration polysilicon extended structure comprises:
Form one second wall structure in the side of the upper part of this gate trench;
Insert polycrystalline silicon material in this upper part of this gate trench, to form this autoregistration polysilicon extended structure; And
By the upper surface of this silicon substrate, cut down the thickness of this silicon substrate, make this autoregistration polysilicon extended structure give prominence to this silicon substrate.
The manufacture method of 12. self-aligned trench power semiconductor structures as claimed in claim 11, is characterized in that, the step of being cut down the thickness of this silicon substrate by the upper surface of this silicon substrate comprises:
With mode of oxidizing, form a thick oxide layer in the surf zone of this silicon substrate; And
Remove this thick oxide layer, make this autoregistration polysilicon extended structure give prominence to this silicon substrate.
The manufacture method of 13. self-aligned trench power semiconductor structures as claimed in claim 11; it is characterized in that; the step of being cut down the thickness of this silicon substrate by the upper surface of this silicon substrate is to form a protective layer to cover this autoregistration polysilicon extended structure, and utilizes this protective layer for this silicon substrate of shielding etching.
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| CN1610089A (en) * | 2003-10-21 | 2005-04-27 | 上海宏力半导体制造有限公司 | Method for producing shallow ridge isolation structure to improve smiling effect |
| CN1726587A (en) * | 2002-12-14 | 2006-01-25 | 皇家飞利浦电子股份有限公司 | Manufacture of a trench-gate semiconductor device |
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| US7109552B2 (en) * | 2004-11-01 | 2006-09-19 | Silicon-Based Technology, Corp. | Self-aligned trench DMOS transistor structure and its manufacturing methods |
| US8878292B2 (en) * | 2008-03-02 | 2014-11-04 | Alpha And Omega Semiconductor Incorporated | Self-aligned slotted accumulation-mode field effect transistor (AccuFET) structure and method |
| CN101656226A (en) * | 2009-07-22 | 2010-02-24 | 上海宏力半导体制造有限公司 | Method for forming shallow trench isolation structure |
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| CN1610089A (en) * | 2003-10-21 | 2005-04-27 | 上海宏力半导体制造有限公司 | Method for producing shallow ridge isolation structure to improve smiling effect |
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